1.0 Final spec. release May 8, 2001 Final
Add -10 spec. Change ICC1 from 120mA to 220mA (-12) Change ICC1 from 100mA to 210mA (-15) Change ISB1 from 8mA to 12mA Change ICDR from 1mA to 5mA Add tBE, tBLZ, tBHZ, tBW parameters
1.1
Add -25°C ~ +85°C grade
July 17, 2002
(July, 2002, Version 1.1)AMIC Technology, Inc.
Page 2
A61L6316 Series
64K X 16 BIT HIGH SPEED CMOS SRAM
Features General Description
n Center power pinout
n Supply voltage: -10: 3.3V+10%, -5%
-12, -15: 3.3V±10%
n Access times: 10/12/15 ns (max.)
n Current: Operating: -10: 230mA (max)
-12: 220mA (max.)
-15: 210mA (max.)
Standby: TTL: 25mA (max.)
CMOS: 12mA (max.)
n Extended operating temperature range: -25°C to 85°C
for -I series
n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL-compatible
n Common I/O using three-state output
n Data retention voltage: 2V (min.)
n Available in 44-pin 400mil SOJ and 44-pin 400mil
TSOP(II) forward packages.
The A61L6316 is a high speed 1,048,576-bit static
random access memory organized as 65,536 words by 16
bits and operates on low power supply voltage from 3.0V
to 3.6V. It is built using AMIC’s high performance CMOS
process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
The chip enable input is provided for POWER-DOWN, to
disable the device. Two byte enable inputs and an output
enable input are included for easy interfacing.
Data retention is guaranteed at a power supply voltage as
low as 2V.
Product Family
Product
Family
A61L6316
Operating
Temperature
0°C ~ +70°C
-25°C ~ +85°C
1. Typical values are measured at VCC = 3.3V, TA = 25°C and not 100% tested.
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
DC Electrical Characteristics (TA = 0°C to + 70°C or -25°C to +85°C, -10: 3.3V+10%, -5%; -12, -15: 3.3V±10%)
Symbol Parameter
Min. Max. Min. Max. Min. Max.
ILI
ILO
Input Leakage - 2 - 2 - 2
Output Leakage - 2 - 2 - 2
ICC1 (2) Dynamic Operating
Current
ISB- 25 - 25 - 25 mA
ISB1
Standby Power
Supply Current
A61L6316-10 A61L6316-12 A61L6316-15
- 230 - 220 - 210 mA
-
12
12
-
-
12
Unit Conditions
VIN = GND to VCC
µA
CE = VIH, OE = VIH
µA
VI/O = GND to VCC
CE = VIL, II/O = 0 mA
Min. Cycle, Duty = 100%
CE = VIH
mA
CE ≥ VCC - 0.2V,
VIN≥ VCC -0.2V or
VIN≤ 0.2V
VOLOutput Low Voltage - 0.4 - 0.4 - 0.4 V IOL = 8 mA
VOHOutput High Voltage 2.4 - 2.4 - 2.4 - V IOH = -4 mA
Notes: 1. VIL = -3.0V for pulses less than 20 ns.
2. ICC1 is dependent on output loading, cycle rates, and Read/Write patterns.
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A61L6316 Series
CE OE WE LB HB
Truth Table
I/O0 to I/O7 Mode I/O8 to I/O15 Mode VCC Current
H X X X X Not selected Not selected ISB1, ISB
L L Read Read ICC1, ICC2, ICC
L L H L H Read High - Z ICC1, ICC2, ICC
H L High - Z Read ICC1, ICC2, ICC
L L Write Write ICC1, ICC2, ICC
L X L L H Write Not Write/Hi - Z ICC1, ICC2, ICC
H L Not Write/Hi - Z Write ICC1, ICC2, ICC
L X High - Z High - Z ICC1, ICC2, ICC
L H H
X L High - Z High - Z ICC1, ICC2, ICC
X X X H H Not selected Not selected ISB1, ISB
Note: X = H or L
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol Parameter Min. Max. Unit Conditions
CIN* Input Capacitance - 6 pF VIN = 0V
CI/O* Input/Output Capacitance - 8 pF VI/O = 0V
* These parameters are sampled and not 100% tested.
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A61L6316 Series
AC Characteristics (TA = 0°C to +70°C or -25°C to +85°C, -10: 3.3V+10%, -5%; -12, -15: 3.3V±10%)
Symbol Parameter A61L6316-10 A61L6316-12 A61L6316-15 Unit
Min. Max. Min. Max. Min. Max.
Read Cycle
tRCRead Cycle Time 10 - 12 - 15 - ns
tAAAddress Access Time - 10 - 12 - 15 ns
tACEChip Enable Access Time - 10 - 12 - 15 ns
tBEByte Enable Access Time - 5 - 6 - 8 ns
tOEOutput Enable to Output Valid - 5 - 6 - 8 ns
tCLZChip Enable to Output in Low Z 3 - 3 - 3 - ns
tOLZOutput Enable to Output in Low Z 0 - 0 - 0 - ns
tBLZByte Enable to Output in Low Z 0 - 0 - 0 - ns
tCHZChip Disable Output in High Z 0 5 0 6 - 8 ns
tBHZByte Disable to Output in High Z 0 5 0 6 0 8 ns
tOHZOutput Disable to Output in High Z 0 5 0 6 0 8 ns
tOHOutput Hold from Address Change 3 - 3 - 3 - ns
Write Cycle
tWCWrite Cycle Time 10 - 12 - 15 - ns
tCWChip Enable to End of Write 8 - 10 - 12 - ns
tBWByte Enable to End of Write 8 - 10 - 12 - ns
tASAddress Setup Time of Write 0 - 0 - 0 - ns
tAWAddress Valid to End of Write 8 - 10 - 12 - ns
tWPWrite Pulse Width 8 - 10 - 12 - ns
tWRWrite Recovery Time 0 - 0 - 0 - ns
tWHZWrite to Output in High Z 0 5 0 6 0 8 ns
tDWData to Write Time Overlap 5 - 6 - 7 - ns
tDHData Hold from Write Time 0 - 0 - 0 - ns
tOWOutput Active from End of Write 3 - 3 - 3 - ns
Notes: tCHZ, tBHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels.
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A61L6316 Series
Timing Waveforms
Read Cycle 1
Address
DOUT
(1, 2, 4)
tRC
tAA
tOH
tOH
Read Cycle 2
Address
HB, LB
OE
DOUT
CE
(1, 2, 3)
tRC
tAA
tCLZ
tACE
5
tBE
5
tBLZ
tOE
5
tOLZ
tOHZ
5
tBHZ
tCHZ
5
5
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled CE = VIL, HB = VIL and, or LB = VIL.
3. Address valid prior to or coincident with CE and (HB and, or LB) transition low.
4. OE = VIL.
5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
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A61L6316 Series
Timing Waveforms (continued)
Write Cycle 1
(Write Enable Controlled)
tWC
Address
3
tAW
tCW
CE
tBW
HB, LB
tWR
WE
DATA IN
DATA OUT
1
tAS
4
tWHZ
tWP
2
tDW
tDH
tOW
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A61L6316 Series
Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
tWC
Address
CE
HB, LB
WE
DATA IN
DATA OUT
tAW
tWP
tCW
2
tBW
tDW
1
tAS
4
tWHZ
tWR
3
tDH
tOW
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A61L6316 Series
Timing Waveforms (continued)
Write Cycle 3
(Byte Enable Controlled)
tWC
Address
tAW
tCW
CE
3
tWR
HB, LB
WE
tWP
tBW
2
1
tAS
tDH
tOW
DATA IN
DATA OUT
tWHZ
tDW
4
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP, tBW) of a low CE , WE and (HB and, or LB).
3. tWR is measured from the earliest of CE or WE or (HB and, or LB) going high to the end of the Write cycle.
4. OE level is high or low.
5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.