Datasheet A61L6316V-15I, A61L6316V-15, A61L6316V-12I, A61L6316V-12, A61L6316V-10I Datasheet (AMICC)
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A61L6316 Series
64K X 16 BIT HIGH SPEED CMOS SRAM
Document Title
64K X 16 BIT HIGH SPEED CMOS SRAM
Revision History
Rev. No. History Issue Date Remark
0.0 Initial issue July 14, 2000 Preliminary
1.0 Final spec. release May 8, 2001 Final
Add -10 spec.
Change ICC1 from 120mA to 220mA (-12)
Change ICC1 from 100mA to 210mA (-15)
Change ISB1 from 8mA to 12mA
Change ICDR from 1mA to 5mA
Add tBE, tBLZ, tBHZ, tBW parameters
1.1
Add -25°C ~ +85°C grade
July 17, 2002
(July, 2002, Version 1.1) AMIC Technology, Inc.
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A61L6316 Series
64K X 16 BIT HIGH SPEED CMOS SRAM
Features General Description
n Center power pinout
n Supply voltage: -10: 3.3V+10%, -5%
-12, -15: 3.3V±10%
n Access times: 10/12/15 ns (max.)
n Current: Operating: -10: 230mA (max)
-12: 220mA (max.)
-15: 210mA (max.)
Standby: TTL: 25mA (max.)
CMOS: 12mA (max.)
n Extended operating temperature range: -25°C to 85°C
for -I series
n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL-compatible
n Common I/O using three-state output
n Data retention voltage: 2V (min.)
n Available in 44-pin 400mil SOJ and 44-pin 400mil
TSOP(II) forward packages.
The A61L6316 is a high speed 1,048,576-bit static
random access memory organized as 65,536 words by 16
bits and operates on low power supply voltage from 3.0V
to 3.6V. It is built using AMIC’s high performance CMOS
process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
The chip enable input is provided for POWER-DOWN, to
disable the device. Two byte enable inputs and an output
enable input are included for easy interfacing.
Data retention is guaranteed at a power supply voltage as
low as 2V.
Product Family
Product
Family
A61L6316
Operating
Temperature
0°C ~ +70°C
-25°C ~ +85°C
1. Typical values are measured at VCC = 3.3V, TA = 25°C and not 100% tested.
2. Data retention current VCC = 2.0V.
VCC Range
Speed
Data Retention
(ICCDR, Typ.)
3.0V ~ 3.6V 10/12/15 ns 3mA 5mA
Pin Configuration
n SOJ / TSOP (II)
CE
I/O0
I/O1
I/O2
I/O3
VCC
GND
I/O4
I/O5
I/O6
I/O7
WE
NC
1A0
A1
2
A2
3
4
A3
A4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
A5
19
A6
20
A7
21
A8
22
44
A15
43
A14
42
A13
41
OE
40
HB
39
LB
38
A61L6316S(V)
I/O15
37
I/O14
36
I/O13
35
I/O12
34
GND
33
VCC
32
I/O11
31
I/O10
30
I/O9
I/O8
29
28
NC
27
A12
26
A11
25
A10
24
A9
23
NC
Power Dissipation
Standby
(ISB1, Typ.)
Package
Type
44L SOP
44L TSOP(II)
(July, 2002, Version 1.1) 1 AMIC Technology, Inc.
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A61L6316 Series
Block Diagram
A0
A14
A15
I/O
I/O
VCC
GND
DECODER
0
INPUT
DATA
CIRCUIT
7
1,048,576-BIT
MEMORY ARRAY
COLUMN I/O
INPUT
DATA
CIRCUIT
I/O
I/O
8
15
CE
LB
HB
OE
WE
CONTROL
CIRCUIT
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A61L6316 Series
Pin Description - SOJ/TSOP(II)
Pin No. Symbol Description
1 - 5, 18 - 21,
24 - 27,42 - 44
6
7 - 10, 13 - 16,
29 - 32, 35 - 38
17
39
40
41
11, 33 VCC Power
12, 34 GND Ground
22 , 23, 28 NC No Connection
A0 - A15 Address Inputs
CE
I/O0 - I/O15 Data Input/Outputs
WE
LB
HB
OE
Chip Enable Input
Write Enable Input
Byte Enable Input (I/O0 to I/O7)
Byte Enable Input (I/O8 to I/O15)
Output Enable Input
Recommended DC Operating Conditions
(TA = 0°C to + 70°C or -25°C to +85°C)
Symbol Parameter Min. Typ. Max. Unit
*VCC Supply Voltage 3.0 3.3 3.6 V
GND Ground 0 0 0 V
VIH Input High Voltage 2.2 - VCC + 0.3 V
VIL Input Low Voltage -0.3 - 0.8 V
CL Output Load - - 30 pF
* -10 VCCmin: 3.135V
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A61L6316 Series
Absolute Maximum Ratings*
VCC to GND . . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V
IN, IN/OUT Volt to GND . . . . . . . . -0.5V to VCC + 0.5V
Operating Temperature, Topr . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 0°C to +70°C or -25°C to +85°C
Storage Temperature, Tstg . . . . . . . . . -55°C to +125°C
Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . 0.7W
Soldering Temp. & Time . . . . . . . . . . . . . 260°C, 10 sec
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
DC Electrical Characteristics (TA = 0°C to + 70°C or -25°C to +85°C, -10: 3.3V+10%, -5%; -12, -15: 3.3V±10%)
Symbol Parameter
Min. Max. Min. Max. Min. Max.
ILI
ILO
Input Leakage - 2 - 2 - 2
Output Leakage - 2 - 2 - 2
ICC1 (2) Dynamic Operating
Current
ISB - 25 - 25 - 25 mA
ISB1
Standby Power
Supply Current
A61L6316-10 A61L6316-12 A61L6316-15
- 230 - 220 - 210 mA
-
12
12
-
-
12
Unit Conditions
VIN = GND to VCC
µA
CE = VIH, OE = VIH
µA
VI/O = GND to VCC
CE = VIL, II/O = 0 mA
Min. Cycle, Duty = 100%
CE = VIH
mA
CE ≥ VCC - 0.2V,
VIN ≥ VCC -0.2V or
VIN ≤ 0.2V
VOL Output Low Voltage - 0.4 - 0.4 - 0.4 V IOL = 8 mA
VOH Output High Voltage 2.4 - 2.4 - 2.4 - V IOH = -4 mA
Notes: 1. VIL = -3.0V for pulses less than 20 ns.
2. ICC1 is dependent on output loading, cycle rates, and Read/Write patterns.
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A61L6316 Series
CE OE WE LB HB
Truth Table
I/O0 to I/O7 Mode I/O8 to I/O15 Mode VCC Current
H X X X X Not selected Not selected ISB1, ISB
L L Read Read ICC1, ICC2, ICC
L L H L H Read High - Z ICC1, ICC2, ICC
H L High - Z Read ICC1, ICC2, ICC
L L Write Write ICC1, ICC2, ICC
L X L L H Write Not Write/Hi - Z ICC1, ICC2, ICC
H L Not Write/Hi - Z Write ICC1, ICC2, ICC
L X High - Z High - Z ICC1, ICC2, ICC
L H H
X L High - Z High - Z ICC1, ICC2, ICC
X X X H H Not selected Not selected ISB1, ISB
Note: X = H or L
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol Parameter Min. Max. Unit Conditions
CIN* Input Capacitance - 6 pF VIN = 0V
CI/O* Input/Output Capacitance - 8 pF VI/O = 0V
* These parameters are sampled and not 100% tested.
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A61L6316 Series
AC Characteristics (TA = 0°C to +70°C or -25°C to +85°C, -10: 3.3V+10%, -5%; -12, -15: 3.3V±10%)
Symbol Parameter A61L6316-10 A61L6316-12 A61L6316-15 Unit
Min. Max. Min. Max. Min. Max.
Read Cycle
tRC Read Cycle Time 10 - 12 - 15 - ns
tAA Address Access Time - 10 - 12 - 15 ns
tACE Chip Enable Access Time - 10 - 12 - 15 ns
tBE Byte Enable Access Time - 5 - 6 - 8 ns
tOE Output Enable to Output Valid - 5 - 6 - 8 ns
tCLZ Chip Enable to Output in Low Z 3 - 3 - 3 - ns
tOLZ Output Enable to Output in Low Z 0 - 0 - 0 - ns
tBLZ Byte Enable to Output in Low Z 0 - 0 - 0 - ns
tCHZ Chip Disable Output in High Z 0 5 0 6 - 8 ns
tBHZ Byte Disable to Output in High Z 0 5 0 6 0 8 ns
tOHZ Output Disable to Output in High Z 0 5 0 6 0 8 ns
tOH Output Hold from Address Change 3 - 3 - 3 - ns
Write Cycle
tWC Write Cycle Time 10 - 12 - 15 - ns
tCW Chip Enable to End of Write 8 - 10 - 12 - ns
tBW Byte Enable to End of Write 8 - 10 - 12 - ns
tAS Address Setup Time of Write 0 - 0 - 0 - ns
tAW Address Valid to End of Write 8 - 10 - 12 - ns
tWP Write Pulse Width 8 - 10 - 12 - ns
tWR Write Recovery Time 0 - 0 - 0 - ns
tWHZ Write to Output in High Z 0 5 0 6 0 8 ns
tDW Data to Write Time Overlap 5 - 6 - 7 - ns
tDH Data Hold from Write Time 0 - 0 - 0 - ns
tOW Output Active from End of Write 3 - 3 - 3 - ns
Notes: tCHZ, tBHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not
referred to output voltage levels.
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A61L6316 Series
Timing Waveforms
Read Cycle 1
Address
DOUT
(1, 2, 4)
tRC
tAA
tOH
tOH
Read Cycle 2
Address
HB, LB
OE
DOUT
CE
(1, 2, 3)
tRC
tAA
tCLZ
tACE
5
tBE
5
tBLZ
tOE
5
tOLZ
tOHZ
5
tBHZ
tCHZ
5
5
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled CE = VIL, HB = VIL and, or LB = VIL.
3. Address valid prior to or coincident with CE and (HB and, or LB) transition low.
4. OE = VIL.
5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
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A61L6316 Series
Timing Waveforms (continued)
Write Cycle 1
(Write Enable Controlled)
tWC
Address
3
tAW
tCW
CE
tBW
HB, LB
tWR
WE
DATA IN
DATA OUT
1
tAS
4
tWHZ
tWP
2
tDW
tDH
tOW
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A61L6316 Series
Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
tWC
Address
CE
HB, LB
WE
DATA IN
DATA OUT
tAW
tWP
tCW
2
tBW
tDW
1
tAS
4
tWHZ
tWR
3
tDH
tOW
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A61L6316 Series
Timing Waveforms (continued)
Write Cycle 3
(Byte Enable Controlled)
tWC
Address
tAW
tCW
CE
3
tWR
HB, LB
WE
tWP
tBW
2
1
tAS
tDH
tOW
DATA IN
DATA OUT
tWHZ
tDW
4
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP, tBW) of a low CE , WE and (HB and, or LB).
3. tWR is measured from the earliest of CE or WE or (HB and, or LB) going high to the end of the Write cycle.
4. OE level is high or low.
5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
(July, 2002, Version 1.1) 10 AMIC Technology, Inc.
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A61L6316 Series
AC Test Conditions
Input Pulse Levels 0V to 3.0V
Input Rise And Fall Time 3 ns
Input and Output Timing Reference Levels 1.5 V
Output Load See Figures 1 and 2
+3.3V
317
Ω
OUTPUT
ZO=50
RL=50
Ω
VT=1.5V
Ω
I/O
* Including scope and jig.
351
Ω
5pF*
Figure 1. Output Load Figure 2. Output Load for tCLZ, tOLZ,
tCHZ, tOHZ, tWHZ, and tOW
Data Retention Characteristics (TA = 0°C to 70°C or -25°C to +85°C)
Symbol Parameter Min. Max. Unit Conditions
VDR VCC for Data Retention 2 3.6 V
ICCDR Data Retention Current
tCDR
Chip Disable to Data Retention
Time
-
5
mA
0 - ns
tR Operation Recovery Time TRC* - ms
≥ VCC - 0.2V
CE
VCC = 2.0V
≥ VCC - 0.2V
CE
VIN ≥ VCC - 0.2V or
VIN ≤ 0.2V
See Retention Waveform
tRC = Read Cycle Time
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A61L6316 Series
Low VCC Data Retention Waveform
DATA RETENTION MODE
VCC
CE
3.0V
tCDR
VIH
VDR ≥ 2V
CE ≥ VDR - 0.2V
3.0V
tR
tVR
VIH
Ordering Information
Part No. Access Time (ns)
Operating Current
Max. (mA)
A61L6316S-10 44L SOJ
A61L6316S-10I 44L SOJ
10 230 12
A61L6316V-10 44L TSOP(II)
A61L6316V-10I
A61L6316S-12 44L SOJ
A61L6316S-12I 44L SOJ
12 220 12
A61L6316V-12 44L TSOP(II)
Standby Current
Max. (mA)
Package
44L TSOP(II)
A61L6316V-12I
44L TSOP(II)
A61L6316S-15 44L SOJ
A61L6316S-15I 44L SOJ
15 210 12
A61L6316V-15 44L TSOP(II)
A61L6316V-15I
44L TSOP(II)
* I series for -25°C to +85°C
(July, 2002, Version 1.1) 12 AMIC Technology, Inc.
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A61L6316 Series
Package Information
SOJ 44L Outline Dimensions unit: inches/mm
D
44 23
E1
221
E
C
A2
y
b
b1
Seating Plane
e
Min
0.025"
0.004
y
D
Symbol
A 0.128 0.138 0.148 3.25 3.51 3.76
A1 0.082 - - 2.08 - A2 0.105 0.110 0.115 2.67 2.79 2.92
b 0.015 - 0.020 0.38 - 0.51
b1 0.026 0.028 0.032 0.66 0.71 0.81
C 0.007 - 0.013 0.18 - 0.21
D 1.120 1.125 1.130 28.45 28.58 28.70
E 0.435 0.440 0.445 11.05 11.18 11.30
E1
E2
e 0.050 BSC 1.27 BSC
R1 0.030 0.035 0.040 0.76 0.89 1.02
θ 0°
Dimensions in inches Dimensions in mm
Min Nom Max Min Nom Max
0.394 0.400 0.405 10.01 10.16 10.29
0.370 BSC 9.40 BSC
-
10° 0°
A
A1
R1
-
10°
E2
θ
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension E1 is for PC Board surface mount pad pitch design
reference only.
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A61L6316 Series
Package Information
TSOP 44L (Type II) Outline Dimensions unit: inches/mm
44
E
E1
θ
L
1
D
A
L1
c
L1
ZD
b
e
y
D
A1 A2
L
Symbol
A - - 0.047 - - 1.20
A1 0.002 - 0.006 0.05 - 0.15
A2 0.037 0.039 0.041 0.95 1.00 1.05
b 0.012 - 0.018 0.30 - 0.45
c 0.005 - 0.008 0.12 - 0.21
D 0.720 0.725 0.730 18.28 18.41 18.54
ZD 0.032 REF 0.805 REF
E 0.455 0.463 0.471 11.56 11.76 11.96
E1 0.395 0.400 0.405 10.03 10.16 10.29
L 0.019 0.023 0.027 0.49 0.59 0.69
L1 0.031 REF 0.80 REF
e 0.031 BSC 0.80 BSC
y - - 0.004 - - 0.10
θ
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E1 does not include resin fins.
3. Dimension ZD includes end flash.
Dimensions in inches Dimensions in mm
Min Nom Max Min Nom Max
0° - 5° 0° - 5°
(July, 2002, Version 1.1) 14 AMIC Technology, Inc.
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