The A616316 is a high speed 1,048,576-bit static random
access memory organized as 65,536 words by 16 bits
and operates on supply voltage 5V. It is built using
AMIC’s high performance CMOS process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Pin Configuration
n SOJ / TSOP(II)
n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL-compatible
n Common I/O using three-state output
n Data retention voltage: 3V (min.)
n Available in 44-pin 400mil SOJ and 44-pin 400mil
TSOP(II) forward packages.
The chip enable input is provided for POWER-DOWN, to
disable the device. Two byte enable inputs and an output
enable input are included for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 3V.
CE
I/O0
I/O1
I/O2
I/O3
VCC
GND
I/O4
I/O5
I/O6
I/O7
WE
NC
1A0
A1
2
A2
3
4
A3
A4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
A5
19
A6
20
A7
21
A8
22
A616316S(V)
44
A15
43
A14
42
A13
41
OE
40
HB
39
LB
38
I/O15
37
I/O14
36
I/O13
35
I/O12
34
GND
33
VCC
32
I/O11
31
I/O10
30
I/O9
I/O8
29
28
NC
27
A12
26
A11
25
A10
24
A9
23
NC
PRELIMINARY (July, 2000, Version 0.0) 1 AMIC Technology, Inc.
Page 3
A616316 Series
Block Diagram
A0
A14
A15
I/O
I/O
VCC
GND
DECODER
0
INPUT
DATA
CIRCUIT
7
1,048,576-BIT
MEMORY ARRAY
COLUMN I/O
INPUT
DATA
CIRCUIT
I/O
I/O
8
15
CE
LB
HB
OE
WE
CONTROL
CIRCUIT
PRELIMINARY (July, 2000, Version 0.0)2 AMIC Technology, Inc.
Page 4
A616316 Series
Pin Description - SOJ/TSOP(II)
Pin No. Symbol Description
1 - 5, 18 - 21,
24 - 27,42 - 44
6
7 - 10, 13 - 16,
29 - 32, 35 - 38
17
39
40
41
11, 33 VCC Power
12, 34 GND Ground
22 , 23, 28 NC No Connection
A0 - A15 Address Inputs
CE
I/O0 - I/O15Data Input/Outputs
WE
LB
HB
OE
Chip Enable Input
Write Enable Input
Byte Enable Input (I/O0 to I/O7)
Byte Enable Input (I/O8 to I/O15)
Output Enable Input
Recommended DC Operating Conditions
(TA = 0°C to + 70°C)
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 4.5 5.0 5.5 V
GND Ground 0 0 0 V
VIHInput High Voltage 2.2 - VCC + 0.3 V
VILInput Low Voltage -0.3 - 0.8 V
CLOutput Load - - 30 pF
PRELIMINARY (July, 2000, Version 0.0)3 AMIC Technology, Inc.
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
DC Electrical Characteristics (TA = 0°C to + 70°C, VCC = 5V±10%, GND = 0V)
Symbol Parameter
Min. Max. Min. Max.
ILI
ILO
ICC1 (2) Dynamic Operating
ISB- 25 - 25 mA
ISB1
Input Leakage - 2 - 2
Output Leakage - 2 - 2
Current
Standby Power
Supply Current
A616316-12 A616316-15
- 170 - 165 mA
-
8
-
8
Unit Conditions
µA
µA
mA
VIN = GND to VCC
CE = VIH, OE = VIH
VI/O = GND to VCC
CE = VIL, II/O = 0 mA
Min. Cycle, Duty = 100%
CE = VIH
CE ≥ VCC - 0.2V,
VIN≥ VCC -0.2V or VIN≤ 0.2V
VOLOutput Low Voltage - 0.4 - 0.4 V IOL = 8 mA
VOHOutput High Voltage 2.4 - 2.4 - V IOH = -4 mA
Notes: 1. VIL = -3.0V for pulses less than 20 ns.
2. ICC1 is dependent on output loading, cycle rates, and Read/Write patterns.
PRELIMINARY (July, 2000, Version 0.0)4 AMIC Technology, Inc.
Page 6
A616316 Series
CE OE WE LB HB
Truth Table
I/O0 to I/O7 Mode I/O8 to I/O15 Mode VCC Current
H X X X X Not selected Not selected ISB1, ISB
L L Read Read ICC1, ICC2, ICC
L L H L H Read High - Z ICC1, ICC2, ICC
H L High - Z Read ICC1, ICC2, ICC
L L Write Write ICC1, ICC2, ICC
L X L L H Write Not Write/Hi - Z ICC1, ICC2, ICC
H L Not Write/Hi - Z Write ICC1, ICC2, ICC
L X High - Z High - Z ICC1, ICC2, ICC
L H H
X L High - Z High - Z ICC1, ICC2, ICC
X X X H H Not selected Not selected ISB1, ISB
Note: X = H or L
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol Parameter Min. Max. Unit Conditions
CIN* Input Capacitance - 6 pF VIN = 0V
CI/O* Input/Output Capacitance - 8 pF VI/O = 0V
* These parameters are sampled and not 100% tested.
PRELIMINARY (July, 2000, Version 0.0)5 AMIC Technology, Inc.
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A616316 Series
AC Characteristics (TA = 0°C to +70°C, VCC = 5V±10%)
Symbol Parameter
Min. Max. Min. Max.
Read Cycle
tRCRead Cycle Time 12 - 15 - ns
tAAAddress Access Time - 12 - 15 ns
tACEChip Enable Access Time - 12 - 15 ns
tOEOutput Enable to Output Valid - 6 - 8 ns
tCLZChip Enable to Output in Low Z 3 - 3 - ns
tOLZOutput Enable to Output in Low Z 0 - 0 - ns
tCHZChip Disable Output in High Z 0 6 - 8 ns
tOHZOutput Disable to Output in High Z 0 6 0 8 ns
tOHOutput Hold from Address Change 3 - 3 - ns
Write Cycle
tWCWrite Cycle Time 12 - 15 - ns
A616316-12 A616316-15
Unit
tCWChip Enable to End of Write 10 - 12 - ns
tASAddress Setup Time of Write 0 - 0 - ns
tAWAddress Valid to End of Write 10 - 12 - ns
tWPWrite Pulse Width 10 - 12 - ns
tWRWrite Recovery Time 0 - 0 - ns
tWHZWrite to Output in High Z 0 6 0 8 ns
tDWData to Write Time Overlap 6 - 7 - ns
tDHData Hold from Write Time 0 - 0 - ns
tOWOutput Active from End of Write 3 - 3 - ns
Notes: tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels.
PRELIMINARY (July, 2000, Version 0.0)6 AMIC Technology, Inc.
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A616316 Series
Timing Waveforms
Read Cycle 1
Address
DOUT
(1, 2, 4)
tRC
tAA
tOH
tOH
Read Cycle 2
Address
CE
HB, LB
OE
DOUT
(1, 2, 3)
tRC
tAA
tCLZ
tACE
5
tBE
5
tBLZ
tOE
5
tOLZ
tOHZ
5
tBHZ
tCHZ
5
5
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled CE = VIL, HB = VIL and, or LB = VIL.
3. Address valid prior to or coincident with CE and (HB and, or LB ) transition low.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY (July, 2000, Version 0.0)7 AMIC Technology, Inc.
Page 9
A616316 Series
Timing Waveforms (continued)
Write Cycle 1
(Write Enable Controlled)
tWC
Address
3
tAW
tCW
CE
tBW
HB, LB
tWR
WE
DATA IN
DATA OUT
1
tAS
4
tWHZ
tWP
2
tDW
tDH
tOW
PRELIMINARY (July, 2000, Version 0.0)8 AMIC Technology, Inc.
Page 10
A616316 Series
Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
tWC
Address
CE
HB, LB
WE
DATA IN
DATA OUT
tAW
tWP
tCW
tBW
2
tDW
1
tAS
4
tWHZ
tWR
3
tDH
tOW
PRELIMINARY (July, 2000, Version 0.0)9 AMIC Technology, Inc.
Page 11
A616316 Series
Timing Waveforms (continued)
Write Cycle 3
(Byte Enable Controlled)
tWC
Address
tAW
tCW
CE
3
tWR
HB, LB
WE
tWP
tBW
2
1
tAS
tDH
tOW
DATA IN
DATA OUT
tWHZ
tDW
4
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP, tBW) of a low CE , WE and (HB and, or LB ).
3. tWR is measured from the earliest of CE or WE or (HB and, or LB ) going high to the end of the Write cycle.
4. OE level is high or low.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY (July, 2000, Version 0.0)10 AMIC Technology, Inc.