Datasheet A5817SEP Datasheet (Allegro)

5817

ADDRESSABLE
28-LINE DECODER/DRIVER

Data Sheet

26186.20

5817

DISCONTINUED PRODUCT

Shown for Reference Only

Replaced by A6817SEP

B

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

GND

B0

OUTPUT ENABLE

OUT

CHIP ENABLE

6

4

5

7

B1

8

B2

9

B3

10

B4

11

B5

12

B6

13

B7

B8

B9

IC

14

15

16

17

OUTPUT DRIVER BANK B

19

20

18

IC

IC

B10

OUT

GND

3

21

B11

OUT

D

IN (MSB)

LOGIC SUPPLY

2

1

DD

V

4-TO-14 LINE DECODER

23

22

B13

B12

OUT

OUT

IN

44

24

OUT

B

C

A13

IN

43

25

OUT

A12

A

IN (LSB)

GND

424140

27

26

A11

A10

OUT

OUT

A

OUTPUT ENABLE

39

OUT

A0

38

OUT

A1

37

OUT

A2

36

OUT

A3

OUT

35

A4

34

OUT

A5

33

OUT

32

OUT

OUT

31

30

OUT

GND

29

Dwg. PP-050

A6

A7

A8

A9

OUTPUT DRIVER BANK A

28

NC

ADDRESSABLE

28-LINE DECODER/DRIVER

Intended for use in ink-jet printer applications, the A5817SEP
addressable 28-line decoder/driver combines low-power CMOS inputs
and logic with 28 high-current, high-voltage bipolar outputs. A 4-to-14
line decoder determines the selected output driver (n) in each
14-driver bank. Two independent output enable inputs (active low)
then provide the final decoding to activate 1- or 2-of-28 outputs
(OUTAn and/or OUTBn). Special internal circuitry is programmed at the
time of manufacture to adjust the output pulse timing and thereby the
energy the device delivers to the ink-jet print head.

The CMOS inputs cause minimal loading and are compatible with
standard CMOS, PMOS, and NMOS logic. Use with TTL or DTL
circuits may require appropriate pull-up resistors to ensure an input
logic high. The internal CMOS logic operates from a 5 V supply.
A CHIP ENABLE function is provided to lock out the drivers during
system power up. The 28 bipolar power outputs are open-collector
30 V Darlington drivers capable of sinking 500 mA at ambient
temperatures up to 85°C.

The A5817SEP is furnished in a 44-lead plastic chip carrier
(quad pack) for minimum-area, surface-mount applications.

ABSOLUTE MAXIMUM RATINGS

at T

= 25°C

A

Output Voltage, VCE............................. 30 V

Logic Supply Voltage, V
Input Voltage Range,

V

....................... -0.3 V to VDD + 0.3 V

IN

Output Current, I

........................... 600 mA

C

Package Power Dissipation, P
Operating Temperature Range,

T

................................. -20°C to +85°C

A

Storage Temperature Range,

T

.............................. -55°C to +150°C

S

*Derate at rate of 22 mW/°C above TA = 25°C.

Caution: CMOS devices have input static
protection but are susceptible to damage
when exposed to extremely high static
electrical charges.

.................. 7.0 V

DD

..... 2.70 W*

D

FEATURES

■ Controlled Characteristics for Ink-Jet Printers

■ Addressable Data Entry

■ 30 V Minimum V

■ CMOS, PMOS, NMOS Compatible Inputs

■ Low-Power CMOS Logic

Always order by complete part number: A5817SEP .

(BR)CEX

5817

ADDRESSABLE
28-LINE DECODER/DRIVER

FUNCTIONAL BLOCK DIAGRAM

A

B

OUTPUT ENABLE

DELAY

TURN-ON

A0

A1

OUT

OUT

LOGIC SUPPLY

OUT

CHIP ENABLE

A2

A11

OUT

B

A

IN (LSB)

IN

4-TO-14 LINE DECODER

A12

OUT

A13

OUT

OUT

IN

B0

C

D

IN (MSB)

B1

OUT

B2

OUT

B11

OUT

OUTPUT ENABLE

DELAY

TURN-ON

B12

B13

OUT

OUT

Dwg. FP-032

TYPICAL INPUT CIRCUIT TYPICAL OUTPUT DRIVER

V

DD

OUT

N

IN

Dwg. EP-021-7

Dwg. EP-010-1

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

W
Copyright © 1993, Allegro MicroSystems, Inc.

5817

ADDRESSABLE
28-LINE DECODER/DRIVER

ELECTRICAL CHARACTERISTICS at T

= +25°C, V

A

= 5.0 V.

DD

Limits
Characteristic Symbol Test Conditions Min Typ Max Units
Output Drivers

V

Output Leakage Current I
Output Saturation Voltage V

Output Breakdown Voltage V

CEX

CE(SAT)

(BR)CEX

Unclamped Inductive — V
Load Current I

Turn-On Time t
Fall Time t
Turn-Off Time t
Rise Time t

PHL

f

PLH

r

= 30 V — <1.0 100 µA

CE

I

= 450 mA 0.85 1.15 1.45 V

OUT

= 400 mA 0.8 1.1 1.4 V

I

OUT

RL = 56 Ω 30 — — V

= 30 V, L = 3 µH, RL = 56 Ω, See Note —

CC

= 500 mA, Test Fig.

L

VCC = 21 V, RL = 39 Ω 125 225 475 ns
VCC = 21 V, RL = 39 Ω —20—ns
VCC = 21 V, RL = 39 Ω 175 250 400 ns
VCC = 21 V, RL = 39 Ω —50—ns

Control Logic

Logic Input Voltage V

Logic Input Current I

Input Resistance R
Supply Current I

IN(1)

V

IN(0)

IN(1)

I

IN(0)

IN

DD(ON)

I

DD(OFF)

VIN = 5.0 V — <1.0 100 µA
VIN = 0 V — <-1.0 -100 µA

Two Outputs ON — 6.0 10.0 mA
All Drivers OFF, All Inputs = 0 V, — — 600 µA

OE

Note: Device will turn off and meet all specifications after test.

= OEB = V

A

DD

3.5 — — V
— — 0.8 V

50 — — kΩ

5817

ADDRESSABLE
28-LINE DECODER/DRIVER

IN

A-D

OUTPUT ENABLE

(A and/or B)

OUT

L

N

I

L

R

Dwg. EP-044

UNCLAMPED INDUCTIVE LOAD CURRENT TEST FIGURE

A B

t

ENABLE

V

CC

OUTPUT VOLTAGE

t

PHL

90%

N

10%

50%

t

f

t

OUT

t

PLH

TIMING CONDITIONS

(Logic Levels are VDD and Ground)

A. Minimum Data Active Time Before Output Enable (Data Set-Up Time) ............ 150 ns

B. Minimum Data Hold Time After Output Enable (Data Hold Time) ..................... 250 ns

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

50%

Dwg. WP-017

90%
10%

t

r

5817

ADDRESSABLE
28-LINE DECODER/DRIVER

APPLICATIONS INFORMATION

This device is intended specifically for, although
certainly not limited to, driving ink-jet print heads. In
this application, a certain minimum energy (a function
of load voltage and output pulse duration) is required
for proper operation, while excessive energy will
degrade the life of the print head. The output pulse
duration (t
t

is adjusted during manufacture to compensate for

PHL

variations in the output saturation voltage (V

For the A5817SEP, the relationship between t
and t

ENABLE

t

OUT

x 330 ns) + 25 ns + 110 ns.

For most applications, this will result in a driver­contribution-to-energy-error of less than ±4%.

A logic low on the CHIP ENABLE input will
prevent the drivers from turning ON, regardless of the
state of other inputs or the logic supply voltage. The
CHIP ENABLE input has a slow response time and
should not be used as a high-speed control line. For
proper operation, all ground terminals should be
connected to a common ground on the printed wiring
board. The IC (Internal Connection) terminals are
used to program the turn-on time of the device and
MUST be left electrically unconnected (floating) for
proper operation.

) is equal to t

OUT

at TA = 25°C is:

= t

ENABLE

([V

CE(SAT)

+ t

ENABLE

(actual) – V

PLH

– t

PHL

CE(SAT)

, where

CE(SAT)

(typical)]

).

OUT

DECODER TRUTH TABLE

IN

D

(MSB) (LSB) N

00000
00011
00102
00113
01004
01015
01106
01117
10008
10019
101010
101111
110012
110113
1110ALL OFF
1111ALL OFF

Depending on the four address inputs, the 4-to-14 line
decoder selects one driver from each of the 14 output A
and B banks of sink drivers according to the Decoder
Truth Table. The state of the selected outputs is deter­mined by the OUTPUT ENABLE inputs as shown in the
Enable Truth Table.

IN

C

IN

B

IN

A

ENABLE TRUTH TABLE

CHIP OUTPUT OUTPUT OUTPUTS (OFF unless otherwise specified.

ENABLE ENABLE

0 X X ALL OFF
1 1 1 ALL OFF
1 0 1 OUT
1 1 0 OUT
1 0 0 OUT

X = Irrelevant

A

ENABLE

B

For the value of N see the Decoder Truth Table)

ON

AN

ON

BN

ON, OUT

AN

BN

ON

5817

ADDRESSABLE
28-LINE DECODER/DRIVER

Dimensions in Inches

(for reference only)

28

18

0.319

0.291

0.319

0.291

8.10

7.39

8.10

7.39

0.021

0.013

0.050

BSC

0.533

0.331

1.27

BSC

0.020

MIN

0.180

0.165

29

0.032

0.026

0.695

0.685

0.656

0.650

39

40

Dimensions in Millimeters

(controlling dimensions)

28

29

0.812

0.661

17.65

17.40

16.662

16.510

0.656

0.650

144

0.695

0.685

2

17

INDEX AREA

7

6

Dwg. MA-005-44A in

18

17

INDEX AREA

39

0.51

MIN

4.57

4.20

NOTES: 1. Exact body and lead configuration at vendor’s option within

limits shown.

2. Lead spacing tolerance is non-cumulative.

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

7

144

17.65

17.40

2

6

Dwg. MA-005-44A mm

40

16.662

16.510

Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be required
to permit improvements in the design of its products.

The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsibil­ity for its use; nor for any infringements of patents or other rights of third
parties which may result from its use.