Datasheet A45L9332AF-8, A45L9332AF-7, A45L9332AF, A45L9332AE-8, A45L9332AE Datasheet (AMICC)

A45L9332A Series

Preliminary 256K X 32 Bit X 2 Banks Synchronous Graphic RAM

Document Title
256K X 32Bit X 2 Banks Synchronous Graphic RAM

Revision History

Rev. No. History Issue Date Remark

0.0 Initial issue August 21, 2001 Preliminary

0.1 Update AC and DC data specification October 22, 2001

PRELIMINARY (October, 2001, Version 0.1) AMIC Technology, Inc.

A45L9332A Series

Preliminary 256K X 32 Bit X 2 Banks Synchronous Graphic RAM

Features

n JEDEC standard 3.3V power supply
n LVTTL compatible with multiplexed address

n Dual banks / Pulse RAS
n MRS cycle with address key programs

- CAS Latency (2,3)

- Burst Length (1,2,4,8 & full page)

- Burst Type (Sequential & Interleave)

n All inputs are sampled at the positive going edge of the

system clock

n Burst Read Single-bit Write operation
n DQM 0-3 for byte masking
n Auto & self refresh
n 32ms refresh period (2K cycle)

General Description

The A45L9332A is 16,777,216 bits synchronous high data
rate Dynamic RAM organized as 2 X 262,144 words by 32
bits, fabricated with AMIC’s high performance CMOS
technology. Synchronous design allows precise cycle
control with the use of system clock. I/O transactions are
possible on every clock cycle. Range of operating

n 100 Pin QFP, LQFP (14 X 20 mm)

Graphics Features

n SMRS cycle

- Load mask register

- Load color register

n Write Per Bit (Old Mask)
n Block Write (8 Columns)

frequencies, programmable latencies allows the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
Write per bit and 8 columns block write improves
performance in graphics system.

PRELIMINARY (October, 2001, Version 0.1) 1 AMIC Technology, Inc.

A45L9332A Series

Pin Configuration

VDDQ

DQ4

DQ5

VSSQ

DQ6
DQ7

VDDQ

DQ16
DQ17

VSSQ

DQ18
DQ19

VDDQ

VDD

VSS
DQ20
DQ21

VSSQ

DQ22

DQ23

VDDQ

DQM0
DQM2

WE

CAS
RAS

BA(A10)

CS

A8

DQ2

DQ1

98

99

100

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

17
18

19
20
21
22
23
24
25
26
27
28
29
30

33

32

31

NC

VDD

NCNCNCNCNCNCNCNCNC

88

89

90

91

92

93

94

95

96

97

VSS

85

86

87

A45L9332AE
A45L9332AF

35

36

34

39

38

37

43

424041

46

45

44

DQ0

VSSQ

VSSQ

DQ31

DQ30

DQ29

81

82

83

84

47

80

DQ28DQ3

79

VDDQ

78

DQ

27

77

DQ

26

76

VSSQ
DQ25

75
74

DQ24

73

VDDQ

72

DQ15
DQ14

71

VSSQ

70

DQ13

69
68

DQ12
VDDQ

67

VSS

66
65

VDD

64

DQ11

63

DQ10
VSSQ

62

DQ9

61
60

DQ8

59

VDDQ

58

NC

57

DQM3
DQM1

56
55

CLK

54

CKE

53

DSF
NC

52

A9

51

50

49

48

A1

A0

A2

A3

NCNCNCNCNCNCNCNCNC

VDD

NC

VSS

A4

A7

A6

A5

PRELIMINARY (October, 2001, Version 0.1) 2 AMIC Technology, Inc.

A45L9332A Series

Block Diagram

CLK

CKE

CS

RAS

CAS

WE

DSF

DQMi

DQMi

BLOCK
WRITE

CONTROL

LOGIC

COLUMN

MASK

TIMMING REGISTER

REGISTER

PROGRAMING

MASK

LATENCY &

BURST LENGTH

COLUMN

WRITE

CONTROL

LOGIC

DECORDER

SENSE AMPLIFIER

MUX

256K x 32

CELL

ARRAY

ROW DECORDER

BANK SELECTION

MASK

REGISTER

CLOCK

REGISTER

256K x 32

CELL

ARRAY

INPUT BUFFER

DQi

(i=0~31)

DQMi

INPUT BUFFER

SERIAL

COUNTER

COLUMN ADDRESS

BUFFER

CLOCK ADDRESS (A0~A10)

ROW

ADDRESS

BUFFER

ADDRESS REGISTER

REFRESH
COUNTER

PRELIMINARY (October, 2001, Version 0.1) 3 AMIC Technology, Inc.

A45L9332A Series

Pin Descriptions

Symbol Name Description

CLK System Clock Active on the positive going edge to sample all inputs.

CS

CKE Clock Enable

A0~A9 Address

A10(BA) Bank Select Address

RAS

CAS

WE

DQMi Data Input/Output Mask

Chip Select

Row Address Strobe

Column Address Strobe

Write Enable Enables write operation and Row precharge.

Disables or Enables device operation by masking or enabling all inputs except
CLK, CKE and DQMi

Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one clock + t ss prior to new command.
Disable input buffers for power down in standby.
Row / Column addresses are multiplexed on the same pins.
Row address : RA0~RA9, Column address: CA0~CA7
Selects bank to be activated during row address latch time.
Selects band for read/write during column address latch time.

Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.

Makes data output Hi-Z, t SHZ after the clock and masks the output.

Blocks data input when DQM active. (Byte Masking)
DQi Data Input/Output Data inputs/outputs are multiplexed on the same pins.
DSF Define Special Function Enables write per bit, block write and special mode register set.
VDD/VSS Power Supply/Ground
VDDQ/VS

SQ
NC No Connection

PRELIMINARY (October, 2001, Version 0.1) 4 AMIC Technology, Inc.

Data Output
Power/Ground

Power Supply: +3.3V±0.3V/Ground

Provide isolated Power/Ground to DQs for improved noise immunity.

A45L9332A Series

WE

Absolute Maximum Ratings*

Voltage on any pin relative to VSS (Vin, Vout ) . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +4.6V

Voltage on VDD supply relative to VSS (VDD, VDDQ )

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +4.6V

Storage Temperature (TSTG) . . . . . . . . . -55°C to +150°C

Soldering Temperature X Time (TSLODER) . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C X 10sec

Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . 1W

Short Circuit Current (Ios) . . . . . . . . . . . . . . . . . . . 50mA

*Comments

Permanent device damage may occur if “Absolute Maximum
Ratings” are exceeded.
Functional operation should be restricted to recommended
operating condition.
Exposure to higher than recommended voltage for extended
periods of time could affect device reliability.

Capacitance (TA=25°C, f=1MHz)

Parameter Symbol Condition Min Typ Max Unit

Input Capacitance CI1 A0 to A9, BA 2 4 pF
CI2

Data Input/Output Capacitance CI/O DQ0 to DQ15 2 6 pF

CLK, CKE,
DQMi, DSF

CS, RAS,CAS

,

2 4 pF

,

DC Electrical Characteristics

Recommend operating conditions (Voltage referenced to VSS = 0V)

Parameter Symbol Min Typ Max Unit Note

Supply Voltage VDD,VDDQ 3.0 3.3 3.6 V
Input High Voltage VIH 2.0 3.0 VDD+0.3 V
Input Low Voltage VIL -0.3 0 0.8 V Note 1
Output High Voltage VOH 2.4 - - V IOH = -2mA
Output Low Voltage VOL - - 0.4 V IOL = 2mA
Input Leakage Current IIL -5 - 5
Output Leakage Current IOL -5 - 5
Output Loading Condition See Figure 1

µA
µA

Note 2
Note 3

Note: 1. VIL (min) = -1.5V AC (pulse width ≤ 5ns).

2. Any input 0V ≤ VIN ≤ VDD + 0.3V, all other pins are not under test = 0V

3. Dout is disabled, 0V ≤ Vout ≤ VDD

Decoupling Capacitance Guide Line

Recommended decoupling capacitance added to power line at board.

Parameter Symbol Value Unit

Decoupling Capacitance between VDD and VSS CDC1 0.1 + 0.01
Decoupling Capacitance between VDDQ and VSSQ CDC2 0.1 + 0.01

Note: 1. VDD and VDDQ pins are separated each other.

All VDD pins are connected in chip. All VDDQ pins are connected in chip.

2. VSS and VSSQ pins are separated each other

All VSS pins are connected in chip. All VSSQ pins are connected in chip.

PRELIMINARY (October, 2001, Version 0.1) 5 AMIC Technology, Inc.

µF
µF

A45L9332A Series

DC Electrical Characteristics

(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)

Symbol Parameter Test Conditions

Icc1

Icc2 P

Icc2 PS

ICC2N

ICC2NS

ICC3 P

ICC3 PS

ICC3N

ICC3NS

Operating Current
(One Bank Active)

Precharge Standby
Current in power­down mode

Precharge Standby

Current in non

power-down mode

Active Standby
Current in power­down mode

Active Standby
current in non
power-down mode
(One Bank Active)

Burst Length = 1
tRC ≥ tRC(min), tCC ≥ tCC(min), IOL = 0mA

CKE ≤ VIL(max), tCC = 15ns
CKE ≤ VIL(max), CKL ≤ VIL(max), tCC = ∞

CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns

CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable.

CKE ≤ VIL(max), tCC = 15ns
CKE ≤ VIL(max), CKE ≤ VIL(max) tCC = ∞

CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns

CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable.

CAS

Latency

3 230 210 170
2 - 260 160

Speed

-6 -7 -8

4
4

35

15

6
6

60

40

Unit Notes

mA 1

mA

mA

mA

mA

ICC4

ICC5 Refresh Current

ICC6 Self Refresh Current

ICC7 Operating Current

Note: 1. Measured with outputs open. Addresses are changed only one time during tCC(min).

Operating Current
(Burst Mode)

(One Bank Block
Write)

2. Refresh period is 32ms. Addresses are changed only one time during tCC(min).

IOL = 0mA, Page Burst
All bank Activated, tCCD = tCCD (min)

tRC ≥ tRC (min)

CKE ≤ 0.2V

tCC ≥ tCC (min), IOL=0mA, tBWC(min)

3

2

3 150 120 120
2 - 180 120

310 280 250

- 230 210

240 220 190 mA

mA 1

mA 2

4 mA

PRELIMINARY (October, 2001, Version 0.1) 6 AMIC Technology, Inc.

A45L9332A Series

AC Operating Test Conditions

(VDD = 3.3V ±0.3V, TA = 0°C to +70°C)

Parameter Value

AC input levels VIH/VIL = 2.4V/0.4V
Input timing measurement reference level 1.4V
Input rise and all time (See note3) tr/tf = 1ns/1ns
Output timing measurement reference level 1.4V
Output load condition See Fig.2

3.3V

Output

870

VOH(DC) = 2.4V, IOH = -2mA

1200

Ω

VOL(DC) = 0.4V, IOL = 2mA

ZO=50

OUTPUT

Ω

3pF

Ω

VTT =1.4V
50

Ω

30pF

(Fig. 1) DC Output Load Circuit

(Fig. 2) AC Output Load Circuit

AC Characteristics

(AC operating conditions unless otherwise noted)

Symbol Parameter CAS

Latency

3 6 7 8

tCC CLK cycle time

2 -

CLK to valid

3 - 5.5 - 6 - 6.5

tSAC

Output delay

2 - - - 7.5 - 7

tOH Output data hold time 2.5 2.5 2.5 ns 2

3 2.5 2.5 3

tCH CLK high pulse width

2 -

-6 -7 -8

Min Max Min Max Min Max

1000

-

1000

8

-

3

1000 ns 1

10

- ns 3

3

Unit Note

ns 1,2

PRELIMINARY (October, 2001, Version 0.1) 7 AMIC Technology, Inc.

A45L9332A Series

AC Characteristics (continued)

(AC operating conditions unless otherwise noted)

Symbol Parameter CAS

Latency

3 2.5 2.5

tCL CLK low pulse width

2 -

3 2 2

tSS Input setup time

2 -

3

tSH Input hold time

2

3

tSLZ CLK to output in Low-Z

2

tSHZ

CLK to output

In Hi-Z

Note : 1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.

3 - 5.5 - 6 - 6.5

2 - - - 7.5 - 7

-6 -7 -8

Min Max Min Max Min Max

­3

-

2.5

1 - 1 - 1 - ns 3

1 - 1 - 1 - ns 2

*All AC parameters are measured from half to half.

Unit Note

- 3 - ns 3

- 2.5 - ns 3

ns

PRELIMINARY (October, 2001, Version 0.1) 8 AMIC Technology, Inc.

A45L9332A Series

Operating AC Parameter

(AC operating conditions unless otherwise noted)

tRRD(min) Row active to row active delay

tRCD(min)

tRP(min) Row precharge time

tRAS(min)

tRAS(max)

tRC(min) Row cycle time

tCDL(min) Last data in new col. Address delay

tRDL(min) Last data in row precharge

tBDL(min) Last data in to burst stop

tCCD(min) Col. Address to col. Address delay

tBPL(min) Block write data-in to PRE command

tBWC(min) Block write cycle time

Number of valid output data

RAS to

Row active time

CAS

delay

Version Symbol Parameter CAS

Latency

3
2
3 3 3 2
2 - 2 2
3 3 3 2
2 - 3 2
3 8 7 6
2 - 5 5
3
2
3 11 10 9
2 - 7 7
3
2
3 2 2 2
2 - 2 2
3
2
3
2
3
2
3
2
3 2 CLK 4
2 1 CLK

-6 -7 -8

2 2 2 CLK 1

100

1 CLK 2

1 CLK 2

1 CLK 3

2 CLK

1 CLK 1,3

Unit Note

CLK 1

CLK 1

CLK 1

µs

CLK 1

CLK 2

Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. This parameter means minimum

4. In case of row precharge interrupt, auto precharge and read burst stop.

PRELIMINARY (October, 2001, Version 0.1) 9 AMIC Technology, Inc.

CAS

to

delay at block write cycle only.

CAS

A45L9332A Series

RAS

WE

Simplified Truth Table

Command CKEn-1 CKEn

Refresh

& Row Addr.

Column Addr.

Column Addr.

Column Addr.
Burst Stop H X L H H L L X X 7

Precharge

Clock Suspend or
Active Power Down

Precharge Power Down Mode

DQM H X V X 8
No Operation Command H X

Mode Register Set L 1,2 Register
Special Mode Register Set
Auto Refresh H

Self
Refresh

Write Per Bite Disable L 4,5 Bank Active
Write Per Bit Enable
Auto Precharge Disable L 4 Read &
Auto Precharge Enable
Auto Precharge Disable L 4,5 Write &
Auto Precharge Enable
Auto Precharge Disable L 4,5 Block Write &
Auto Precharge Enable

Bank Selection V L
Both Banks

Entry

Exit L H

Entry

Exit L H X X X X X X

Entry H L

Exit L H

H X L L L L

H

H X L L H H

H X L H L H L X V

H X L H L L L X V

H X L H L L H X V

H X L L H L L X

H L

CS

L L L H L X X

L

L H H H 3

H X X X

L H H H

H X X X

L H H H

H X X X

L V V V V

H X X X X

L H H H

H X X X

CAS

DSF DQM A10 A9 A8~A0 Notes

X OP CODE

H

X X X

X V Row Addr.

H

H

H

H

X H

X X

X

X X

X

X

X X X

Column

Addr.

Column

Addr.

Column

Addr.

1,2,7

4,5,9

4,5,6,9

4,5,6,9

X

3
3

3

4,6

(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)

Note : 1. OP Code : Operand Code

A0~A10 : Program keys. (@MRS)
Color register exists only one per DQi which both banks share.
So dose Mask Register.
Color or mask is loaded into chip through DQ pin.

2. MRS can be issued only at both banks precharge state.
SMRS can be issued only if DQ’s are idle.
A new command can be issued at the next clock of MRS/SMRS.

3. Auto refresh functions as same as CBR refresh of DRAM.

The automatical precharge without Row precharge command is meant by “Auto”.
Auto/Self refresh can be issued only at both precharge state.

PRELIMINARY (October, 2001, Version 0.1) 10 AMIC Technology, Inc.

A45L9332A Series

Simplified Truth Table

4. A10 : Bank select address.

If “Low” at read, (block) write, Row active and precharge, bank A is selected.
If “High” at read, (block) write, Row active and precharge, bank B is selected.
If A9 is “High” at Row precharge, A10 is ignored and both banks are selected.

5. It is determined at Row active cycle.

whether Normal/Block write operates in write per bit mode or not.
For A bank write, at A bank Row active, for B bank write, at B bank Row active.
Terminology : Write per bit = I/O mask

(Block) Write with write per bit mode = Masked (Block ) Write

6. During burst read or write with auto precharge, new read/ (block) write command cannot be issued.

Another bank read/(block) write command can be issued at tPR after the end of burst.

7. Burst stop command is valid only t full page burst length.

8. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0),

but makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)

9. Graphic features added to SDRAM’s original features.

If DSF is tied to low, graphic functions are disabled and chip operates as a 16M SDRAM with 32 DQ’s.

SGRAM vs SDRAM

Function MRS Bank Active Write

DSF L H L H L H

Bank Active

SGRAM

Function

IF DSF is low, SGRAM functionality is identical to SDRAM functionality.

MRS SMRS

with

Write per bit

Disable

Bank Active

with

Write per bit

Enable

Normal

Write

SGRAM can be used as an unified memory by the appropriate DSF control
→SDRAM = Graphic Memory + main Memory

Block
Write

PRELIMINARY (October, 2001, Version 0.1) 11 AMIC Technology, Inc.

A45L9332A Series

Mode Register Filed Table to Program Modes

Register Programmed with MRS

Address A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Function RFU W.B.L TM CAS Latency BT Burst Length

(Note 1) (Note 2)

Test Mode CAS Latency Burst Type Burst Length

A8 A7 Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT=0 BT=1

0 0 Mode Register Set 0 0 0 Reserved 0 Sequential 0 0 0 1 Reserved
0 1 0 0 1 - 1 Interleave 0 0 1 2 Reserved
1 0 0 1 0 2 0 1 0 4 4
1 1

Vendor

Use

Only

0 1 1 3 0 1 1 8 8

Write Burst Length

A9 Length

0 Burst 1 1 0 Reserved 1 1 0 Reserved Reserved
1 Single Bit 1 1 1 Reserved

Special Mode Register Programmed with SMRS

Address A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Function X LC LM X

1 0 0 Reserved 1 0 0 Reserved Reserved
1 0 1 Reserved 1 0 1 Reserved Reserved

1 1 1 256(Full) Reserved

(Note 3)

Load Color Load Mask

A6 Function A5 Function

0 Disable 0 Disable
1 Enable 1 Enable

(Note 4)

Power Up Sequence

1. Apply power and start clock, Attempt to maintain CKE = “H”, DQM = “H” and the other pins are NOP condition at inputs.

2. Maintain stable power, stable clock and NOP input condition for a minimum of 200µs.

3. Issue precharge commands for all banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 may be changed.

The device is now ready for normal operation.
Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.

2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.

3. The full column burst (256bit) is available only at Sequential mode of burst type.

4. If LC and LM both high (1), data of mask and color register will be unknown.

PRELIMINARY (October, 2001, Version 0.1) 12 AMIC Technology, Inc.

A45L9332A Series

Burst Sequence (Burst Length = 4)

Initial address
A1 A0

0 0 0 1 2 3 0 1 2 3
0 1 1 2 3 0 1 0 3 2
1 0 2 3 0 1 2 3 0 1
1 1 3 0 1 2 3 2 1 0

Sequential Interleave

Burst Sequence (Burst Length = 8)

Initial address

Sequential Interleave

A2 A1 A0

0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6
0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5
0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4
1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3
1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2
1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1
1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0

Pixel to DQ Mapping (at BLOCK WRITE)

Column address 3 Byte 2 Byte 1 Byte 0 Byte

A2 A1 A0 I/O31 – I/O24 I/O23 – I/O16 I/O15 – I/O8 I/O7 – I/O0

0 0 0 DQ24 DQ16 DQ8 DQ0
0 0 1 DQ25 DQ17 DQ9 DQ1
0 1 0 DQ26 DQ18 DQ10 DQ2
0 1 1 DQ27 DQ19 DQ11 DQ3
1 0 0 DQ28 DQ20 DQ12 DQ4
1 0 1 DQ29 DQ21 DQ13 DQ5
1 1 0 DQ30 DQ22 DQ14 DQ6
1 1 1 DQ31 DQ23 DQ15 DQ7

PRELIMINARY (October, 2001, Version 0.1) 13 AMIC Technology, Inc.

A45L9332A Series

WE

WE

WE

Device Operations

Clock (CLK)

The clock input is used as the reference for all SGRAM
operations. All operations are synchronized to the positive
going edge of the clock. The clock transitions must be
monotonic between VIL and VIH. During operation with
CKE high all inputs are assumed to be in valid state (low or
high) for the duration of set up and hold time around
positive edge of the clock for proper functionality and ICC
specifications.

Clock Enable (CLK)

The clock enable (CKE) gates the clock onto SGRAM. If
CKE goes low synchronously with clock (set-up and hold
time same as other inputs), the internal clock is suspended
form the next clock cycle and the state of output and burst
address is frozen as long as the CKE remains low. All other
inputs are ignored from the next clock cycle after CKE goes
low. When both banks are in the idle state and CKE goes
low synchronously with clock, the SGRAM enters the power
down mode form the next clock cycle. The SGRAM remains
in the power down mode ignoring the other inputs as long
as CKE remains low. The power down exit is synchronous
as the internal clock is suspended. When CKE goes high at
least “tSS + 1 CLOCK” before the high going edge of the
clock, then the SGRAM becomes active from the same
clock edge accepting all the input commands.

Bank Select (A10)

This SGRAM is organized as two independent banks of
262,144 words X 32 bits memory arrays. The A10 inputs is

latched at the time of assertion of
the bank to be used for the operation. When A10 is

asserted low, bank A is selected. When A10 is asserted
high, bank B is selected. The bank select A10 is latched at
bank activate, read, write mode register set and precharge
operations.

Address Input (A0 ~ A9)

The 18 address bits required to decode the 262,144 word
locations are multiplexed into 10 address input pins
(A0~A9). The 10 bit row address is latched along with

and A10 during bank activate command. The 8 bit

RAS

column address is latched along with
during read or write command.

NOP and Device Deselect

When
performs no operation (NOP). NOP does not initiate any

new operation, but is needed to complete operations which
require more than single clock like bank activate, burst

RAS

,

CAS

and

and

RAS

CAS

are high, the SGRAM

to select

CAS

, WE and A10

read, auto refresh, etc. The device deselect is also a NOP
and is entered by asserting

the command decoder so that
and all the address inputs are ignored.

Power-Up

The following sequence is recommended for POWER UP

1. Power must be applied to either CKE and DQM inputs to
pull them high and other pins are NOP condition at the
inputs before or along with VDD (and VDDQ) supply.
The clock signal must also be asserted at the same time.

2. After VDD reaches the desired voltage, a minimum
pause of 200 microseconds is required with inputs in
NOP condition.

3. Both banks must be precharged now.

4. Perform a minimum of 2 Auto refresh cycles to stabilize
the internal circuitry.

5. Perform a MODE REGISTER SET cycle to program the
CAS latency, burst length and burst type as the default
value of mode register is undefined.

At the end of one clock cycle from the mode register set
cycle, the device is ready for operation.
When the above sequence is used for Power-up, all the
out-puts will be in high impedance state. The high
impedance of outputs is not guaranteed in any other
power-up sequence.
Cf.) Sequence of 4 & 5 may be charged.

Mode Register Set (MRS)

The mode register stores the data for controlling the various
operation modes of SGRAM. It programs the CAS latency,
addressing mode, burst length, test mode and various
vendor specific options to make SGRAM useful for variety
of different applications. The default value of the mode
register is not defined, therefore the mode register must be
written after power up to operate the SGRAM. The mode

register is written by asserting low on

,

CAS

mode with CKE already high prior to writing the mode
register). The state of address pins A0~A9 and A10 in the

same cycle as
is the data written in the mode register. One clock cycle is

required to complete the write in the mode register. The
mode register contents can be changed using the same
command and clock cycle requirements during operation as
long as both banks are in the idle state. The mode register
is divided into various fields depending on functionality. The
burst length field uses A0~A2, burst type uses A3,
addressing mode uses A4~A6, A7~A8 and A10 are used
for vendor specific options or test mode. And the write burst
length is programmed using A9. A7~A8 and A10 must be
set to low for normal SGRAM operation.
Refer to table for specific codes for various burst length,
addressing modes and CAS latencies.

and DSF (The SGRAM should be in active

CS,RAS

,

CS

CAS

RAS

,

high.

,

CAS

high disables

CS

and WE, DSF

CS,RAS

and DSF going low

,

PRELIMINARY (October, 2001, Version 0.1) 14 AMIC Technology, Inc.

A45L9332A Series

WE

Device Operations (continued)

Bank Activate

The bank activate command is used to select a random row
in an idle bank. By asserting low on

desired row and bank addresses, a row access is initiated.
The read or write operation can occur after a time delay of
tRCD(min) from the time of bank activation. tRCD(min) is an
internal timing parameter of SGRAM, therefore it is
dependent on operating clock frequency. The minimum
number of clock cycles required between bank activate and
read or write command should be calculated by dividing
tRCD(min) with cycle time of the clock and then rounding off
the result to the next higher integer. The SGRAM has two
internal banks on the same chip and shares part of the
internal circuitry to reduce chip area, therefore it restricts
the activation of both banks immediately. Also the noise
generated during sensing of each bank of SGRAM is high
requiring some time for power supplies recover before the
other bank can be sensed reliably. tRRD(min) specifies the
minimum time required between activating different banks.
The number of clock cycles required between different bank
activation must be calculated similar to tRCD specification.
The minimum time required for the bank to be active to
initiate sensing and restoring the complete row of dynamic
cells is determined by tRAS(min) specification before a
precharge command to that active bank can be asserted.
The maximum time any bank can be in the active state is
determined by tRAS(max). The number of cycles for both
tRAS(min) and tRAS(max) can be calculated similar to tRCD
specification.

Burst Read

The burst read command is used to access burst of data on
consecutive clock cycles from an active row in an active
bank. The burst read command is issued by asserting low

on CS and
of the clock. The bank must be active for at least tRCD(min)

before the burst read command is issued. The first output
appears CAS latency number of clock cycles after the issue
of burst read command. The burst length, burst sequence
and latency from the burst read command is determined by
the mode register which is already programmed. The burst
read can be initiated on any column address of the active
row. The address wraps around if the initial address does
not start from a boundary such that number of outputs from
each I/O are equal to the burst length programmed in the
mode register. The output goes into high-impedance at the
end of the burst, unless a new burst read was initiated to
keep the data output gapless. The burst read can be
terminated by issuing another burst read or burst write in
the same bank or the other active bank or a precharge
command to the same bank. The burst stop command is
valid only at full page burst length where the output dose
not go into high impedance at the end of burst and the
burst is wrap around.

with WE being high on the positive edge

CAS

RAS

and

CS

with

Burst Write

The burst write command is similar to burst read command,
and is used to write data into the SGRAM consecutive clock
cycles in adjacent addresses depending on burst length

and burst sequence. By asserting low on CS,

with valid column address, a write burst is initiated.
The data inputs are provided for the initial address in the
same clock cycle as the burst write command. The input
buffer is deselected at the end of the burst length, even
though the internal writing may not have been completed
yet. The writing can not complete to burst length. The burst
write can be terminated by issuing a burst read and DQM
for blocking data inputs or burst write in the same or the
other active bank. The burst stop command is valid only at
full page burst length where the writing continues at the end
of burst and the burst is wrap around. The write burst can
also be terminated by using DQM for blocking data and
precharging the bank “tRDL” after the last data input to be
written into the active row. See DQM OPERATION also.

DQM Operation

The DQM is used to mask input and output operation. It
works similar to

writing during write operation. The read latency is two
cycles from DQM and zero cycle for write, which means
DQM masking occurs two cycles later in the read cycle and
occurs in the same cycle during write cycle. DQM operation
is synchronous with the clock, therefore the masking occurs
for a complete cycle. The DQM signal is important during
burst interrupts of write with read or precharge in the
SGRAM. Due to asynchronous nature of the internal write,
the DQM operation is critical to avoid unwanted or
incomplete writes when the complete burst write is not
required. DQM is also used for device selection, byte
selection and bus control in a memory system. DQM0
controls DQ0 to DQ7, DQM1 controls DQ8 to DQ15, DQM2
controls DQ16 to DQ23, DQM3 controls DQ24 to DQ31.
DQM masks the DQ’s by a byte regardless that the
corresponding DQ’s are in a state of WPB masking or Pixel
masking. Please refer to DQM timing diagram also.

Precharge

The precharge operation is performed on an active bank by
asserting low on CS,

the bank to be precharged. The precharge command can
be asserted anytime after tRAS(min) is satisfied from the
bank activate command in the desired bank. “tRP” is defined
as the minimum time required to precharge a bank.
The minimum number of clock cycles required to complete
row precharge is calculated by dividing “tRP” with clock cycle
time and rounding up to the next higher integer. Care
should be taken to make sure that burst write is completed
or DQM is used to inhibit writing before precharge

during read operation and inhibits

OE

,WE and A9 with valid A10 of

RAS

CAS

and

PRELIMINARY (October, 2001, Version 0.1) 15 AMIC Technology, Inc.

A45L9332A Series

WE

WE

WE

Device Operations (continued)

command is asserted. The maximum time any bank can be
active is specified by tRAS(max). Therefore, each bank has
to be precharged within tRAS(max) from the bank activate
command. At the end of precharge, the bank enters the idle
state and is ready to be activated again.
Entry to Power Down, Auto refresh, Self refresh and Mode
register Set etc, is possible only when both banks are in
idle state.

Auto Precharge

The precharge operation can also be performed by using
auto precharge. The SGRAM internally generates the
timing to satisfy tRAS(min) and “tRP” for the programmed
burst length and CAS latency. The auto precharge
command is issued at the same time as burst read or burst
write by asserting high on A9. If burst read or burst write
command is issued with low on A9, the bank is left active
until a new command is asserted. Once auto precharge
command is given, no new commands are possible to that
particular bank until the bank achieves idle state.

Both Banks Precharge

Both banks can be precharged at the same time by using
Precharge all command. Asserting low on CS,

with high on A9 after both banks have satisfied
tRAS(min) requirement, performs precharge on both banks.
At the end of tRP after performing precharge all, both banks
are in idle state.

Auto Refresh

The storage cells of SGRAM need to be refreshed every
32ms to maintain data. An auto refresh cycle accomplishes
refresh of a single row of storage cells. The internal counter
increments automatically on every auto refresh cycle to
refresh all the rows. An auto refresh command is issued by

asserting low on CS,
and

with both banks being in idle state and the device is not in
power down mode (CKE is high in the previous cycle). The
time required to complete the auto refresh operation is
specified by “tRC(min)”. The minimum number of clock
cycles required can be calculated by driving “tRC” with clock
cycle time and then rounding up to the next higher integer.
The auto refresh command must be followed by NOP’s until
the auto refresh operation is completed. Both banks will be
in the idle state at the end of auto refresh operation. The
auto refresh is the preferred refresh mode when the
SGRAM is being used for normal data transactions. The
auto refresh cycle can be performed once in 15.6us or a
burst of 2048 auto refresh cycles once in 32ms.

Self Refresh

The self refresh is another refresh mode available in the
SGRAM. The self refresh is the preferred refresh mode for

. The auto refresh command can only be asserted

RAS

and

with high on CKE

CAS

RAS

and

data retention and low power operation of SGRAM. In self
refresh mode, the SGRAM disables the internal clock and
all the input buffers except CKE. The refresh addressing
and timing is internally generated to reduce power
consumption.

The self refresh mode is entered from all banks idle state
by asserting low on CS,

on WE. Once the self refresh mode is entered, only CKE
state being low matters, all the other inputs including clock
are ignored to remain in the self refresh.
The self refresh is exited by restarting the external clock
and then asserting high on CKE. This must be followed by
NOP’s for a minimum time of “tRC” before the SGRAM
reaches idle state to begin normal operation. If the system
uses burst auto refresh during normal operation, it is
recommended to used burst 2048 auto refresh cycles
immediately after exiting self refresh.

Define Special Function (DSF)

The DSF controls the graphic applications of SGRAM. If
DSF is tied to low, SGRAM function is 256K X 32 X 2 Bank
SDRAM. SDRAM can be used as an unified memory by the
appropriate DSF command. All the graphic function mode
can be entered only by setting DSF high when issuing
commands which otherwise would be normal SDRAM
commands.

SDRAM functions such as
change to SGRAM functions such as

WPB, Block Write and SWCBR respectively. See the
sessions below for the graphic functions that DSF controls.

Special Mode Register Set (SMRS)

There are two kinds of special mode registers in SGRAM.
One is color register and the other is mask register. Those
usage will be explained at “WRITE PER BIT” and ”BLOCK
WRITE” session. When A5 and DSF goes high in the same

cycle as CS,
register (LMR) process is executed and the mask registers

are filled with the masks for associated DQ’s through DQ
pins. And when A6 and DSF goes high in the same cycle

as
register (LCR) process is executed and the color register is

filled with color data for associated DQ’s through the DQ
pins. If both A5 and A6 are high at SMRS, data of mask
and color cycle is required to complete the write in the
mask register and the color register at LMR and LCR
respectively. The next clock of LMR or LCR, a new
commands can be issued. SMRS, compared with MRS, can
be issued at the active state under the condition that DQ’s
are idle. As in write operation, SMRS accepts the data
needed through DQ pins. Therefore it should be attended
not to induce bus contention. The more detailed materials
can obtained by referring corresponding timing diagram.

CS

,

RAS

RAS

,

,

CAS

CAS

and

,

RAS

RAS

and WE going low, load mask

and CKE with high

CAS

Active, Write, and WCBR

Active with

RAS

going low, load color

PRELIMINARY (October, 2001, Version 0.1) 16 AMIC Technology, Inc.

A45L9332A Series

Device Operations (continued)

Write Per Bit

Write per bit (i.e. I/O mask mode) for SGRAM is a function
that selectively masks bits of data being written to the
devices. The mask is stored in an internal register and
applied to each bit of data written when enabled. Bank
active command with DSF = High enabled write per bit
operations is stored in the mask register accessed by
SWCBR (Special Mode Register Set Command). When a
mask bit = 1, the associated data bit is written when a write
command is executed and write per bit has been enabled
for the bank being written. When a mask bit = 0, the
associated data bit is unaltered when a write command is
executed and the write per bit has been enabled for the
bank being written. No additional timing conditions are
required for write per bit operations. Write per bit writes can
be either single write, burst writes or block writes. DQM
masking is the same for write per bit and non-WPB write.

Block Write

Block write is a feature allowing the simultaneous writing of
consecutive 8 columns of data within a RAM device during
a single access cycle. During block write the data to be
written comes from an internal “color” register and DQ I/O
pins are used for independent column selection. The block
of column to be written is aligned on 8 column boundaries
and is defined by the column address with the 3 LSB’s
ignored. Write command with DSF = 1enables block write
for the associated bank. A write command with DSF = 0
enables normal write for the associated bank. The block
width is 8 column where column = “n” bits for by “n” part.
The color register is the same width as the data port of the
chip. It is written via a SWCBR where data present on the
DQ pin is to be coupled into the internal color register. The
color register provides the data masked by the DQ column
select, WPB mask (If enabled), and DQM byte mask.
Column data masking (Pixel masking) is provided on an
individual column basis for each byte of data. The column
mask is driven on the DQ pins during a block write
command. The DQ column mask function is segmented on
a per bit basis (i.e. DQ[0:7] provides the column mask for
data bits[0:7], DQ[8:15] provides the column mask for data
bits[8:15], DQ0 masks column[0] for data bits[0:7], DQ9
masks column [1] for data its [8:15], etc). Block writes are
always non-burst, independent of the burst length that has
been programmed into the mode register. Back to back
block writes are allowed provided that the specified block
write cycle time (tBWC) is satisfied. If write per bit was
enabled by the bank active command with DSF = 1, then
write per bit masking of the color register data is enabled.
If write per bit was disabled by a bank active command with
DSF = 0, the write per bit masking of the color register data
is disabled. DQM masking provides independent data byte
masking during block write exactly the same as it does
during normal write operations, except that the control is
extended to the consecutive 8 columns of the block write.

Timing Diagram to Illustrate tBWC

10 2

Clock

CKE

CS

RAS

CAS

WE

DSF

High

1 CLK BW

PRELIMINARY (October, 2001, Version 0.1) 17 AMIC Technology, Inc.

A45L9332A Series

state of

High operation frequency allows performance gain for SCROLL, FILL,

,2,4,8 and full page transfer per column

Programmable burst of 1,2,4,8 and full page transfer per column

Maximum 32 byte data transfers (e.g. for 8bpp : 32 pixels) with plane

the mask register directly controls a corresponding bit

Summary of 2M Byte SGRAM Basic Features and Benefits

Features 256K X 32 X 2 SGRAM Benefits

Better interaction between memory and system without wait­asynchronous DRAM.

Interface Synchronous

High speed vertical and horizontal drawing.

Bank 2 ea

and BitBLT.
Pseudo-infinite row length by on-chip interleaving operation.

Hidden row activation and precharge.
Page Depth / 1 Row 256 bit High speed vertical and horizontal drawing.
Total Page Depth 2048 bytes High speed vertical and horizontal drawing

Burst Length (Read) 1,2,4,8 Full Page

1,2,4,8 Full Page

Burst Length (Write)

BRSW Switch to burst length of 1 at write without MRS

Programmable burst of 1

addresses.

addresses.

Burst Type Sequential & Interleave Compatible with Intel and Motorola CPU based system.
CAS Latency 2,3 Programmable CAS latency.

High speed FILL, CLEAR, Text with color registers.
Block Write 8 Columns

Color Register 1 ea. A and B bank share.

and byte masking functions.

Mask Register 1 ea. Write-per-bit capability (bit plane masking). A and B banks share.

DQM0-3 Byte masking (pixel masking for 8bpp system) for data-out/in

Mask function

Write per bit

Pixel Mask at Block Write Byte masking (pixel masking for 8bpp system) for color by DQi

Each bit of

plane.

Basic feature And Function Descriptions

1. CLOCK Suspend

1) Click Suspended During Write (BL=4)

CLK

CMD
CKE

Internal

CLK

DQ(CL2)

DQ(CL3)

Note: CLK to CLK disable/enable=1 clock

WR

Masked by CKE

D0 D1 D2 D3

D0 D1 D2 D3

Not Written

PRELIMINARY (October, 2001, Version 0.1) 18 AMIC Technology, Inc.

2) Clock Suspended During Read (BL=4)

RD

Q0 Q1 Q3

Masked by CKE

Q2

Q0 Q2 Q3

Q1

Suspended Dout

A45L9332A Series

2. DQM Operation

CLK

CMD

DQMi

DQ(CL2)

DQ(CL3)

CLK
CMD
CKE

DQM

DQ(CL2)

DQ(CL3)

1) Write Mask (BL=4)

WR

D0 D1 D3

D0 D1 D3

DQM to Data-in Mask = 0CLK

2) Read Mask (BL=4)

RD

2) Read Mask (BL=4)

RD

Masked by CKE

Hi-Z

Q0 Q2 Q4

Hi-Z

Q1 Q3

Hi-Z

Hi-Z Hi-Z

Masked by CKE

Hi-Z

Q0 Q1 Q3

Hi-Z

Q1 Q2 Q3

DQM to Data-out Mask = 2

Hi-Z

Q6 Q7 Q8

Q5 Q6 Q7

* Note : 1. There are 4 DQMi (I=0~3).

Each DQMi masks 8 DQi’s. (1 Byte, 1 Pixel for 8bbp).

2. DQM makes data out Hi-Z after 2 clocks which should masked by CKE “L”.

PRELIMINARY (October, 2001, Version 0.1) 19 AMIC Technology, Inc.

A45L9332A Series

3. CAS Interrupt (I)

CKL
CMD
ADD

DQ(CL2)
DQ(CL3)

CKL

CMD

ADD

DQ

1) Read intreupted by Read (BL=4)

RD RD

A B

QA0 QB0 QB1 QB2 QB3

QA0 QB0 QB1 QB2 QB3

tCCD

Note2

2) Write interrupted by (Block) Write (BL =2)

WR WR

tCCD

Note2

A B

DA0 DB0 DB1 DC0

tCDL

Note3

Note 1

WR BW

tCCD

C D

Pixel

tCDL

Note3

Note2

Note4

3) Write interrupted by Read (BL =2)

WR RD

tCCD

A B

DQ(CL2)
DQ(CL3)

DA0 QB0 Pixel

DA0

tCDL

Note3

Note2

QB0 QB1

2) Block Write to Block Write

CKL

CMD

ADD

DQ

BW BW

A B

Pixel

Pixel

tBWC

Note5

Note4

Note : 1. By “Interrupt”, It is possible to stop burst read/write by external command before the end of burst.

By “

2. tCCD :

3. tCDL : Last data in to new column address delay. ( = 1CLK).

4. Pixel : Pixel mask.

5. tBWC : Block write minimum cycle time.

Interrupt”, to stop burst read/write by

CAS

CAS

to

delay. (=1CLK)

CAS

access; read, write and block write.

CAS

PRELIMINARY (October, 2001, Version 0.1) 20 AMIC Technology, Inc.

A45L9332A Series

4. CAS Interrupt (II) : Read Interrupted Write & DQM

(1) CL=2, BL=4

CLK

i) CMD

DQM

DQ

ii) CMD

DQM

DQ

iii) CMD

DQM

DQ

iv) CMD

DQM

DQ

(2) CL=3, BL=4

CLK

i) CMD

DQM

DQ

ii) CMD

RD WR

D0 D1 D2 D3

RD

RD WR

RD WR

RD

WR

Hi-Z

D0 D1 D2 D3

WRRD

Hi-Z

D0 D1 D2 D3

Hi-Z

Note 1

D0 D1 D2 D3

WR

D0 D1 D2 D3Q0

DQM

D0 D1 D2 D3

WRRD

D0 D1 D2 D3

WR

Hi-Z

D0 D1 D2 D3

WR

Hi-Z

Note 2

D0 D1 D2Q0

D3

iii) CMD

iv) CMD

v) CMD

DQ

DQM

DQ

RD WR

DQM

DQ

RD

DQM

DQ

* Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.

2. To prevent bus contention, DQM should be issued which makes a least one gap between data in and data out.

PRELIMINARY (October, 2001, Version 0.1) 21 AMIC Technology, Inc.

A45L9332A Series

5. Write Interrupted by Precharge & DQM

CLK

CMD

WR PRE

DQM

DQ

D0 D1 D2 D3

Masked by DQM

Note : 1. To inhibit invalid write, DQM should be issued.

2. This precharge command and burst write command should be of the same bank, otherwise it is not precharge
interrupt but only another bank precharge of dual banks operation.

6. Precharge

Note 2

Note 1

1) Normal Write (BL=4)
CLK

CMD

DQ

3) Read (BL=4)
CLK

CMD

DQ(CL2)

DQ(CL3)

7. Auto Precharge

1) Normal Write (BL=4)
CLK

CMD

DQ

3) Read (BL=4)
CLK

CMD

DQ(CL2)

WR PRE
D0 D1 D2 D3

t

RDL

Note 1

RD PRE

Q0 Q1 Q2 Q3

Q0 Q1 Q2 Q3

WR
D0 D1 D2 D3

Auto Precharge Starts

RD

Q0 Q1 Q2 Q3

Note 3

Note 2

1

2) Block Write
CLK

CMD

DQ

2

2) Block Write

CLK

CMD

DQ

(CL 2,3)

BW

Pixel

Auto Precharge Starts

BW

Pixel

t

BPL

t

BPL

Note 1

Note 3

PRE

t

RP

Q0 Q1 Q2 Q3DQ(CL3)

Note 3

Auto Precharge Starts

* Note : 1. tBPL : Block write data-in to PRE command delay.

2. Number of valid output data after Row Precharge : 1,2 for CAS Latency = 2,3 respectively.

3. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of other active bank can be issued from this point.

At burst read/write with auto precharge,

interrupt of the same/another bank is illegal.

CAS

PRELIMINARY (October, 2001, Version 0.1) 22 AMIC Technology, Inc.

A45L9332A Series

8. Burst Stop & Precharge Interrupt

1) Write Interrupted by Precharge (BL=4)
CLK

CMD

DQM

DQ

3) Read Interrupted by Precharge (BL=4)
CLK

CMD

DQ(CL2)

DQ(CL3)

9. MRS & SMRS

WR PRE

D0 D1 D2 D3

RDL

Note 1

Note 3
1

RD

t

PRE

Q0 Q1

Q0 Q1

2) Write Burst Stop (Full Page Only)
CLK

CMD

DQ

WR

D1

D0 D2

t

BDL

STOP

4) Read Burst Stop (Full Page Only)
CLK

CMD

DQ(CL2)

2

RD

STOP

Q0 Q1

Note 3
1

Q0 Q1DQ(CL3)

2

2) Mode Register Set
CLK

Note 4

CMD

PRE MRS

tRP

Note : 1.tRDL : 2CLK, Last Data in to Row Precharge.

2. tBDL : 1CLK, Last Data in to Burst Stop Delay.

3. Number of valid output data after Row precharge or burst stop : 1,2 for CAS latency=2,3 respectively.

4. PRE : Both banks precharge if necessary.
MRS can be issued only at all bank precharge state.

1CLK

ACT

2) Special Mode Register Set
CLK

CMD

SMRS BW

ACT SMRS

1CLK

1CLK 1CLK 1CLK

SMRS

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A45L9332A Series

10. Clock Suspend Exit & Power Down Exit

1) Clock Suspend (=Active Power Down) Exit
CLK

CKE

Internal

Note 1

CLK

CMD

11. Auto Refresh & Self Refresh

1) Auto Refresh
CLK

CKE

Internal

CLK

CMD

Note 3

Note 4

PRE AR CMD

2) Power Down (=Precharge Power Down) Exit
CLK

t

SS

CKE

Internal

Note 2

t

SS

CLK

NOP

RD

t

RP

t

RC

CMD

~

~

~

~

~

~

~

~

Note 5

ACT

PRE

Note 6

Note 4

SR

t

RP

2) Self Refresh

CLK

CMD

CKE

* Note : 1. Active power down : one or more bank active state.

2. Precharge power down : both bank precharge state.

3. The auto refresh is the same as CBR refresh of conventional DRAM.
No precharge commands are required after Auto Refresh command.
During tRC from auto refresh command, any other command can not be accepted.

4. Before executing auto/self refresh command, both banks must be idle state.

5. (S)MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.

6. During self refresh mode, refresh interval and refresh operation are performed internally.
After self refresh entry, self refresh mode is kept while CKE is LOW.
During self refresh mode, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state.
During tRC from self refresh exit command, any other command can not be accepted.
Before/After self refresh mode, burst auto refresh cycle (2K cycles ) is recommended.

~

~

~

~

~

~

CMD

~

~

~

~

t

RC

PRELIMINARY (October, 2001, Version 0.1) 24 AMIC Technology, Inc.

A45L9332A Series

At BL=4, same applications are possible. As above example, at Interleave
Decrement Counting Mode can be realized. See the BURST SEQUENCE TABLE

Using Full Page Mode and Burst Stop Command, Binary Counting Mode can be

Every cycle Read/Write Command with random column address can realize

nd of burst, new read/write stops read/write burst and starts new

12. About Burst Type Control

Basic

MODE

Pseudo-

MODE

Random

MODE

Sequential counting

Interleave counting

Pseudo-

Decrement Sequential

Counting

Pseudo-Binary Counting

Random column Access

tCCD = 1 CLK

At MRS A3=”0”. See the BURST SEQUENCE TABE.(BL=4,8)
BL=1,2,4,8 and full page wrap around.
At MRS A3=” 1”. See the BURST SEQUENCE TABE.(BL=4,8)
BL=4,8 At BL=1,2 Interleave Counting = Sequential Counting
At MRS A3 = “1”. (See to Interleave Counting Mode)
Starting Address LSB 3 bits A0-2 should be “000” or “111”.@BL=8.

--if LSB = “000” : Increment Counting.

--if LSB= “111” : Decrement Counting.
For Example, (Assume Addresses except LSB 3 bits are all 0, BL=8)

--@ write, LSB=”000”, Accessed Column in order 0-1-2-3-4-5-6-7

--@ read, LSB=”111”, Accessed Column in order 7-6-5-4-3-2-1-0
Counting mode, by confining starting address to some values, Pseudo­carefully.

At MRS A3 = “0”. (See to Sequential Counting Mode)
A0-2 = “111”. (See to Full Page Mode)

realized.

--@ Sequential Counting Accessed Column in order 3-4-5-6-7-1-2-3 (BL=8)

--@ Pseudo-Binary Counting,
Accessed Column in order 3-4-5-6-7-8-9-10 (Burst Stop command)
Note. The next column address of 256 is 0

Random Column Access.
That is similar to Extended Data Out (EDO) Operation of convention DRAM.

13. About Burst Length Control

Basic

MODE

Special

MODE

Random

MODE

Interrupt

MODE

(Interrupted by Precharge)

1
2

4 At MRS A2,1,0 = “010”
8 At MRS A2,1,0 = “011”.

Full Page

BRSW

Block Write

Burst Stop

Interrupt

RAS

Interrupt

CAS

At MRS A2,1,0 = “000”.
At auto precharge, tRAS should not be violated.
At MRS A2,1,0 = “001”.
At auto precharge, tRAS should not be violated.

At MRS A2,1,0 = “111”.
Wrap around mode (Infinite burst length) should be stopped by burst stop,

interrupt or

RAS

At MRS A9=”1”.
Read burst = 1,2,4,8, full page/write Burst =1
At auto precharge of write, tRAS should not be violated.
8 Column Block Write. LSB A0-2 are ignored. Burst length=1.
tBWC should not be violated.
At auto precharge, tRAS should not be violated.
tBDL=1, Valid DQ after burst stop is 1,2 for CL=2,3 respectively
Using burst stop command, it is possible only at full page burst length.
Before the end of burst, Row precharge command of the same bank
Stops read/write burst with Row precharge.
tRDL=2 with DQM, valid DQ after burst stop is 1,2 for CL=2,3 respectively

During read/write burst with auto precharge,
Before the e

read/write burst or block write.
During read/write burst with auto precharge,

CAS

interrupt.

interrupt cannot be issued.

RAS

interrupt can not be issued.

CAS

PRELIMINARY (October, 2001, Version 0.1) 25 AMIC Technology, Inc.

A45L9332A Series

14. Mask Functions

1) Normal Write
I/O masking : By Mask at Write per Bit Mode, the selected bit planes keep the original data.

If bit plane 0,3,7,9,15,22,24, and 31 keep the original value.

i) STEP

•• SMRS (LMR) : Load mask [31-0]=”0111,1110,1011,1111,0111,1101,0111,0110”

•• Row Active with DSF “H” : Writ Per Bit Mode Enable

•• Perform Normal Write

ii) ILLUSTRATION

I/O(=DQ) 31 24 23 16 15 8 7 0

External Data-in 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DQMi DQM3=0 DQM2=0 DQM1=0 DQM0=1

Mask Register 0 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 0 1 1 1 1 0 1 0 1 1 1 0 1 1 0

Before Write 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

After Write 0 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 0 0 0 0 1 0 1 1 1 1 1 1 1 1

Note 1

2) Block Write
Pixel masking : By Pixel Data issued through DQ pin, the selected pixels keep the original data.

See PIXEL TO DQ MAPPING TABLE.

If Pixel 0,4,9,13,18, 22, 27 and 31 keep the original white color.

Assume 8bpp,
White = “0000,0000”, Red = “1010,0011”, Green = “1110,0001”, Yellow = “0000,1111”, Blue = “1100,0011”

i) STEP

•• SMRS(LCR) : Load color (for 8bbp, through X32 DQ color 0-3 are loaded into color registers)
Load(color3, color2, color1, color0) = (Blue, Green, Yellow, Red)

= “1100,0011,1110,0001,0000,1111,1010,0011”

•• Row Active with DSF “L” : I/O Mask by Write Per Bit Mode Disable

•• Block write with DQ[31-0] = “0111,0111,1011,1011,1101,1101,1110,1110”

ii) ILLUSTRATION

I/O(=DQ) 31 24 23 16 15 8 7 0

DQMi DQM3=0 DQM2=0 DQM1=0 DQM0=1

Color Register Color3=Blue Color2=Green Color1=Yellow Color0=Red

Before

Block

Write

&

DQ

(Pixel

data)

After

Block

Write

Note 2
* Note : 1. DQM byte masking.

000 White DQ24=H White DQ16=H White DQ8=H White DQ0=L
001 White DQ25=H White DQ17=H White DQ9=L White DQ1=H
010 White DQ26=H White DQ18=L White DQ10=H White DQ2=H
011 White DQ27=L White DQ19=H White DQ11=H White DQ3=H
100 White DQ28=H White DQ20=H White DQ12=H White DQ4=L
101 White DQ29=H White DQ21=H White DQ13=L White DQ5=H
110 White DQ30=H White DQ22=L White DQ14=H White DQ6=H
111 White DQ31=L White DQ23=H White DQ15=H White DQ7=H
000 Blue Green Yellow White
001 Blue Green White White
010 Blue White Yellow White
011 White Green Yellow White
100 Blue Green Yellow White
101 Blue Green White White
110 Blue White Yellow White
111 White Green Yellow White

2. At normal write, One column is selected among columns decoded by A2-0 (000-111)
At block write, instead of ignored address A2-0, DQ0-31 control each pixel.

PRELIMINARY (October, 2001, Version 0.1) 26 AMIC Technology, Inc.

A45L9332A Series

1 1 0 0 0 0 1 1

1 1 0 0 0 0 1 1

1 0 1 0 0 0 1 1

0 0 0 0 0 0 0 0

(Continued)

Pixel and I/O masking : By Mask at Write Per Bit Mode, the selected bit planes keep the original data.

By Pixel Data issued through DQ pin, the selected pixels keep the original data.
See PIXEL TO DQ MAPPING TANLE.

Assume 8bpp,
White = “0000,0000”, Red = “1010,0011”, Green = “1110,0001”, Yellow = “0000,1111”, Blue = “1100,0011”

i) STEP

•• SMRS (LCR) : Load color (for 8bpp, through X 32 DQ color0-3 are loaded into color registers)
Load (color3, color2, color1, color0) = (Blue, Green, Yellow, Red)

= “1100,0011,1110,0001,0000,1111,1010,0011”

••SMRS (LMR) : Load mask, Mask[31-0] = “1111,1111,1101,1101,0100,0010,0111,0110”

→ Byte 3:No I/O Masking; Byte 2:I/O Masking; Byte 1:I/O and Pixel Masking; Byte 0:DQM Byte Masking

•• Row Active with DSF “H” : I/O Mask by Write Per Bit Mode Enable

•• Block Write with DQ[31-0] = “0111,0111,1111,1111,0101,0101,1110,1110” (Pixel Mask)

ii) ILLUSTRATUON

I/O(=DQ) 31 24 23 16 15 8 7 0

Color Register Blue Green Yellow Red

1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 0 1 1 1 1 1 0 1 0 0 0 1 1

DQMi DQM3=0 DQM2=0 DQM1=0 DQM0=1

Mask Register 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 0 1 0 0 0 0 1 0 0 1 1 1 0 1 1 0

Before Write Yellow

0 0 0 0 1 1 1 1

After Write Blue

Yellow

0 0 0 0 1 1 1 1

Blue

Green

1 1 1 0 0 0 0 1

Red

White

0 0 0 0 0 0 0 0

White

I/O(=DQ) 31 24 23 16 15 8 7 0

DQMi DQM3=0 DQM2=0 DQM1=0 DQM0=1

Color Register Color3=Blue Color2=Green Color1=Yellow Color0=Red

Before

Block
Write

&

DQ

(Pixel

data)

After
Block
Write

Note 2 Note 1
PIXEL MASK I/O MASK PIXEL & I/O MASK BYTE MASK
* Note : 1. DQM byte masking.

000 Yellow DQ24=H Yellow DQ16=H Green DQ8=H White DQ0=L
001 Yellow DQ25=H Yellow DQ17=H Green DQ9=L White DQ1=H
010 Yellow DQ26=H Yellow DQ18=H Green DQ10=H White DQ2=H
011 Yellow DQ27=L Yellow DQ19=H Green DQ11=H White DQ3=H
100 Yellow DQ28=H Yellow DQ20=H Green DQ12=H White DQ4=L
101 Yellow DQ29=H Yellow DQ21=H Green DQ13=L White DQ5=H
110 Yellow DQ30=H Yellow DQ22=H Green DQ14=H White DQ6=H
111 Yellow DQ31=L Yellow DQ23=H Green DQ15=L White DQ7=H
000 Blue
001 Blue
010 Blue
011 Yellow
100 Blue
101 Blue
110 Blue
111 Yellow

2. At normal write, One column is selected among columns decoded by A2-0 (000-111)
At block write, instead of ignored address A2-0, DQ0-31 control each pixel.

Blue Red
Blue
Blue Red
Blue
Blue Red
Blue
Blue Red
Blue

Green White

Green White

Green White

Green White

White

White

White

White

PRELIMINARY (October, 2001, Version 0.1) 27 AMIC Technology, Inc.

A45L9332A Series

Power On Sequence & Auto Refresh

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

A10/BA

A9/AP

WE

High level is necessary

t

RP

~

~

t

RC

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

KEY Ra

KEY

KEY

BS

Ra

~

~

DSF

DQM

DQ

PRELIMINARY (October, 2001, Version 0.1) 28 AMIC Technology, Inc.

High level is necessary

Precharge

(All Banks)

High-Z

Auto Refresh Auto Refresh Mode Regiser Set

~

~

~

~

~

~

~

~

~

~

~

~

~

~

Row Active
(Write per Bit
Enable or Disable)

: Don't care

A45L9332A Series

Single Bit Read-Write-Read Cycles (Same Page) @CAS Latency=3, Burst Length=1

t

t

CC

t

RCD

CH

t

CL

High

t

RAS

RC

t

t

SS

t

SH

t

SS

t

SS

t

SH

t

RP

t

CCD

Rb

t

SH

CLOCK

CKE

CS

RAS

CAS

ADDR

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

*Note 1

SH

t

SS

t

t

SH

Ra Ca Cb Cc

t

SS

A

A

WE

DSF

DQM

DQ

10

9

*Note 2

*Note 2,3 *Note 2,3 *Note 2,3 *Note 4 *Note 2

BS BS BS BS BS BS

*Note 3 *Note 3 *Note 3 *Note 4

Ra Rb

SH

t

t

SS

*Note 5 *Note 6

*Note 3

t

t

RAC

SH

t

SH

t

SH

t

SAC

t

SS

t

SS

Qa Db Qc

t

Row Active
(Write per Bit
Enable or
Disable)

Read

SLZ

t

OH

t

SS

SHZ

t

Block Write

Write

or

Read

Precharge

*Note 5

Row Active
(Write per Bit
Enable or
Disable

: Don't care

PRELIMINARY (October, 2001, Version 0.1) 29 AMIC Technology, Inc.

A45L9332A Series

* Note : 1. All inputs can be don’t care when

2. Bank active & read/write are controlled by A10.

A10 Active & Read/Write

0 Bank A
1 Bank B

is high at the CLK high going edge.

CS

3. Enable and disable auto precharge function are controlled by A9 in read/write command.

A9 A10 Operation

0

1

0 Disable auto precharge, leave bank A active at end of burst.
1 Disable auto precharge, leave bank B active at end of burst.
0 Enable auto precharge, precharge bank A at end of burst.
1 Enable auto precharge, precharge bank B at end of burst.

4. A9 and A10 control bank precharge when precharge command is asserted.

A9 A10 Precharge

0 0 Bank A
0 1 Bank B
1 X Both Bank

5. Enable and disable Write-per Bit function are controlled by DSF in Row Active command.

A10 DSF Operation

0

1

L Bank A row active, disable write per bit function for bank A

H Bank A row active, enable write per bit function for bank A

L Bank B row active, disable write per bit function for bank B

H Bank B row active, enable write per bit function for bank B

6. Block write/normal write is controlled by DSF

DSF Operation Minimum cycle time

L Normal write tCCD
H Block write tBWC

PRELIMINARY (October, 2001, Version 0.1) 30 AMIC Technology, Inc.

A45L9332A Series

Read & Write Cycle at Same Bank @Burst Length=4

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

A10

DQM

WE

DSF

High

*Note 1

t

RC

t

RCD

*Note 2

Ra Ca0 Rb Cb0

Ra RbA9

t

OH

DQ

(CL = 2)

DQ

(CL = 3)

Row Active

(A-Bank)

t

RAC

*Note 3

t

*Note 3

t

RAC

Read

(A-Bank)

SAC

Qa0

Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3

t

SHZ

t

OH

Qa0

Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3

t

SAC

Precharge

(A-Bank)

*Note 4

t

SHZ

*Note 4

Row Active

(A-Bank)

Write

(A-Bank)

t

t

RDL

RDL

Precharge

(A-Bank)

: Don't care

*Note : 1. Minimum row cycle times is required to complete internal DRAM operation.

2. Row precharge can interrupt burst on any cycle. [CAS latency-1] valid output data available after Row
enters precharge. Last valid output will be Hi-Z after tSHZ from the clock.

3. Access time from Row address. tCC*(tRCD + CAS latency-1) + tSAC

4. Output will be Hi-Z after the end of burst. (1,2,4 & 8)
At Full page bit burst, burst is wrap-around.

PRELIMINARY (October, 2001, Version 0.1) 31 AMIC Technology, Inc.

A45L9332A Series

Page Read & Write Cycle at Same Bank @Burst Length=4

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

A10

DSF

DQM

WE

High

t

RCD

Ra Ca0 Cb0 Cc0

RaA9

*Note 2

*Note1 *Note3

t

CDL

Cd0

*Note 2

t

RDL

DQ

(CL=2)

DQ

(CL=3)

Row Active

(A-Bank)

Read

(A-Bank)

Qa0 Qa1 Qb0 Qb1 Dc0 Dc1 Dd0 Dd1

Read

(A-Bank)

Qa0 Qa1 Qb0

Dc0 Dc1 Dd0 Dd1

Write

(A-Bank)

Write

(A-Bank)

Precharge

(A-Bank)

: Don't care

*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write

command to avoid bus contention.

2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.

3. DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.

PRELIMINARY (October, 2001, Version 0.1) 32 AMIC Technology, Inc.

A45L9332A Series

Block Write Cycle (with Auto Precharge)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

A10

DSF

*Note 2

A9

WE

RAa CAa CAb RBa

RAa

t

BWC

RBa

High

CBa

CBb

DQM

*Note 1

DQ

Row Active with

Write-per-Bit

Enable

(A-Bank)

Pixel
Mask

Masked

Block Write

(A-Bank)

Block Write with

Auto Precharge

(A-Bank)

Pixel

Mask

Masked

Row Active

(B-Bank)

Pixel

Mask

Block Write with

Auto Precharge

Block Write

(B-Bank)

Pixel
Mask

(B-Bank)

: Don't care

*Note : 1. Column Mask (DQi=L : Mask, DQi=H : Non Mask)

2. At Block Write, CA0-2 are ignored.

PRELIMINARY (October, 2001, Version 0.1) 33 AMIC Technology, Inc.

A45L9332A Series

SMRS and Block/Normal Write @ Burst Length=4

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

A0-2

A3,4,7,8

A5

A6

A9

A10

WE

High

*Note1

RAa RBa

RAa CAa RBa CBa

CAa CBaRAa

RAa CAa

RAa CAa

RBa

RBa

CBa

CBa

DSF

DQM

DQ

Color

Load Color

Register

Row Active
with WPB*

Enable

(A-Bank)

I/O

Mask

Load Color

Register

Pixel
Mask

Masked

Bolck Write

(A-Bank)

Row Active

with WPB*

(B-Bank)

I/O

Mask

Enable

Load Mask Register

Color

Load Color

Register

DBa0 DBa1 DBa2 DBa3

Masked Write

with Auto

Precharge

(B-Bank)

WPB* : Write-Per-Bit

: Don't care

* Note : 1. At the next clock of special mode set command, new command is possible.

PRELIMINARY (October, 2001, Version 0.1) 34 AMIC Technology, Inc.

A45L9332A Series

RAS

Page Read Cycle at Different Bank @Burst Length = 4

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

A10

A9

WE

DSF

DQM

*Note 1

RAa CAa

RAa RBb

High

RBb CAc CBd CAe

CBb

Low

*Note 2

DQ

(CL=2)

DQ

(CL=3)

Row Active

(A-Bank)

Read

(A-Bank)

Row Active

(B-Bank)

Read

(B-Bank)

QBb1QBb0QAa0 QAa1 QAa2 QAa3 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1

QBb1QBb0QAa0 QAa1 QAa2 QAa3 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1

Read

(A-Bank)

Read

(B-Bank)

Read

(A-Bank)

Precharge

(A-Bank)

: Don't care

* Note : 1. CS can be don’t care when

,

CAS

and WE are high at the clock high going edge.

2. To interrupt a burst read by row precharge, both the read ad the precharge banks must be the same.

PRELIMINARY (October, 2001, Version 0.1) 35 AMIC Technology, Inc.

A45L9332A Series

Page Write Cycle at Different Bank @Burst Length=4

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

A10

A9

WE

DSF

RAa CAa

Key

RAa RBb

RBb CAc CBd

t

High

CBb

CDL

DQM

DQ

Row Active with

Write-Per-Bit

Mask DAc2 DAc3 DBd2 DBd3

Load Mask

Register

enable

(A-Bank)

Row Active

(B-Bank)

Masked Write

(A-Bank)

DBb1DBb0DAa0 DAa1 DAa2 DAa3 DBb2 DBb3 DAc0 DAc1 DBd0 DBd1

Write

(B-Bank)

Masked Write

with auto

precharge

(A-Bank)

Write with auto

Precharge

(B-Bank)

: Don't care

PRELIMINARY (October, 2001, Version 0.1) 36 AMIC Technology, Inc.

A45L9332A Series

Read & Write Cycle at Different Bank @Burst Length=4

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

A10

DSF

DQM

A9

WE

RAa CAa

RAa

RBb

High

CBb CAc

RAc

RAcRBb

t

CDL

*Note 1

DQ

(CL=2)

DQ

(CL=3)

Row Active

(A-Bank)

Read

(A-Bank)

Row Active

(B-Bank)

QAa3QAa2QAa0 QAa1 DBb0 DBb1 QAc0DBb2 DBb3 QAc1 QAc2

QAa2QAa1QAa0 QAa3 DBb0

Precharge

(A-Bank)

Write

(B-Bank)

Row Active

(A-Bank)

DBb1 DBb2 DBb3

Read

(A-Bank)

QAc0 QAc1

: Don't care

* Note : 1. tCDL should be met to complete write.

PRELIMINARY (October, 2001, Version 0.1) 37 AMIC Technology, Inc.

A45L9332A Series

Read & Write Cycle with Auto Precharge I @Burst Length=4

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

RAS

CAS

ADDR

DSF

DQMi

CS

A10

WE

RAa RBbA9CAa

RAa

RBb

High

CBb

DQ

(CL=2)

DQ

(CL=3)

Row Active

(A-Bank)

Auto Precharge

Row Active

(B-Bank)

Read with

(A-Bank)

Auto Precharge

Start Point

QAa3QAa2QAa0 QAa1 DBb0 DBb1 DBb2 DBb3

QAa2QAa1QAa0 QAa3 DBb0

Write with

(A-Bank)

Auto Precharge

(B-Bank)

DBb1 DBb2 DBb3

Auto Precharge

Start Point

(B-Bank)

: Don't care

*Note : 1. tRCD should be controlled to meet minimum tRAS before internal precharge start.

(In the case of Burst Length=1 & 2, BRSW mode and Block write)

PRELIMINARY (October, 2001, Version 0.1) 38 AMIC Technology, Inc.

A45L9332A Series

Read & Write Cycle with Auto Precharge II @Burst Length=4

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

DSF

DQM

DQ

(CL=2)

A10

WE

Ra RbA9Ca

Ra

Rb

Cb

High

Ra Ca

Ra

Qb1Qb0Qa0 Qa1 Qb2 Qb3 Da0 Da1

DQ

(CL=3)

Row Active

(A-Bank)

Row Active

(B-Bank)

Read with

Auto Pre

Charge

(A-Bank)

Read without

Auto Precharge

(B-Bank)

Auto Precharge

Strart Point

(A-Bank)

*Note 1

Qb0Qa1Qa0 Qb1 Qb2

Precharge

(B-Bank)

Qb3 Da0 Da1

Row Active

(A-Bank)

Write with

Auto Precharge

(A-Bank)

: Don't care

* Note : 1. When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation.

- if read(Write) command without auto precharge is issued at B-Bank before A Bank auto precharge starts, A Bank
auto precharge will start at B Bank read command input point.

- Any command can not be issued at A Bank during tRP after A Bank auto precharge starts.

PRELIMINARY (October, 2001, Version 0.1) 39 AMIC Technology, Inc.

A45L9332A Series

Read & Write Cycle with Auto Precharge III @Burst Length=4

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

A10

DSF

DQM

DQ

(CL=2)

A9

WE

Ra

Ra

Ca

High

Rb Cb

Rb

Qa3Qa2Qa0 Qa1 Qb0 Qb1 Qb2 Qb3

DQ

(CL=3)

Row Active

(A-Bank)

Read with

Auto Preharge

(A-Bank)

* Note 1

Auto Precharge

Start Point

Row Active

Qa2Qa1Qa0 Qa3 Qb0

Read with

Auto Precharge

(A-Bank)
(B-Bank)

(B-Bank)

Qb1 Db2 Db3

Auto Precharge

Start Point

(B-Bank)

: Don't care

* Note : 1. Any command to A-bank is not allowed in this period.

tRP is determined from at auto precharge start point

PRELIMINARY (October, 2001, Version 0.1) 40 AMIC Technology, Inc.

A45L9332A Series

Read Interrupted by Precharge Command & Read Burst Stop Cycle (@Full Page Only)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

A10

DSF

DQM

DQ

(CL=2)

A9

WE

RAa

RAa

High

CAa

* Note 1 * Note 1

QAa0

CAb

1* Note 2

QAa4QAa3QAa1 QAa2 QAb0 QAb1 QAb2 QAb3

QAb4 QAb5

1

DQ

(CL=3)

Row Active

(A-Bank)

Read

(A-Bank)

QAa0

Burst Stop

2

QAa3QAa2QAa1 QAa4 QAb0

Read

(A-Bank)

QAb1 QAb2 QAb3

Precharge

(A-Bank)

QAb4 QAb5

: Don't care

2

* Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.

2. About the valid DQ’s after burst stop, it is same as the case of

RAS

interrupt.
Both cases are illustrated above timing diagram. See the label 1,2 on them.
But at burst write, burst stop and

interrupt should be compared carefully.

RAS

Refer the timing diagram of “Full page write burst stop cycle”.

PRELIMINARY (October, 2001, Version 0.1) 41 AMIC Technology, Inc.

A45L9332A Series

Write Interrupted by Precharge Command & Write Burst Stop Cycle (@ Full Page Only)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

A10

A9

WE

DSF

DQM

RAa

RAa

High

CAa

* Note 1 * Note 1

t

BDL

CAb

* Note 3

t

RDL

* Note 2

DQ

Row Active

(A-Bank)

DAa0 DAb4 DAb5

Write

(A-Bank)

DAa4DAa3DAa1 DAa2 DAb0 DAb1 DAb2 DAb3

Burst Stop

Write

(A-Bank)

Precharge

(A-Bank)

: Don't care

* Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.

2. Data-in at the cycle of burst stop command cannot be written into corresponding memory cell.
It is defined by AC parameter of tBDL(=1CLK).

3. Data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell.
It is defined by AC parameter of tRDL(2=CLK).
DQM at write interrupted by precharge command is needed to ensure tRDL of 2CLK.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.

4. Burst stop is valid only at full page burst length.

PRELIMINARY (October, 2001, Version 0.1) 42 AMIC Technology, Inc.

A45L9332A Series

Burst Read Single Bit Write Cycle @Burst Length=2, BRSW

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

RAS

CAS

ADDR

A10

DSF

DQM

(CL=2)

CS

DQ

A9

WE

RAa

RAa

CAa

DAa0

RBb CAb

RBb

High

* Note 2

CBc CAd

RAc

RAc

QAb1QAb0 DBc0 QAd0

QAd1

DQ

(CL=3)

Row Active

(A-Bank)

DAa0 QAd1

Row Active

(B-Bank)

Write

(A-Bank)

Read with

Auto Precharge

(A-Bank)

QAb1QAb0 DBc0

Row Active

(A-Bank)

Write with

Auto Precharge

(B-Bank)

Read

(A-Bank)

QAd0

Precharge

(A-Bank)

: Don't care

* Note : 1. BRSW mode is enabled by setting A9 “High” at MRS (Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to “1” regardless of programed burst length.

2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated.
Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command,

The next cycle starts the precharge.

3. WPB function is also possible at BRSW mode.

PRELIMINARY (October, 2001, Version 0.1) 43 AMIC Technology, Inc.

A45L9332A Series

Clock Suspension & DQM Operation Cycle @CAS Latency = 2, Burst Length=4

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

A10

A9

WE

DSF

DQM

DQ

Ra

Ra

Row Active

Ca

Read

Cb

* Note 1

Qa1 Qb0 Qb1 Dc0

Qa0 Dc2

Clock

Suspension

Qa2

tSHZ

Qa3

Read

tSHZ

Read DQM

Cc

Write
DQM

Write

* Note : 1. DQM needed to prevent bus contention.

Clock

Suspension

: Don't care

PRELIMINARY (October, 2001, Version 0.1) 44 AMIC Technology, Inc.

A45L9332A Series

Active/Precharge Power Down Mode @CAS Lantency=2, Burst Length=4

CLOCK

CKE

CS

RAS

CAS

ADDR

A10

WE

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

t

SS

* Note 1

A9

*Note 3

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

t

SS

* Note 2

t

SS

Ra Ca

Ra

~

~

t

SS

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

DSF

DQM

DQ Qa0 Qa1

Precharge

Power-down

Entry

* Note : 1. All banks should be in idle state prior to entering precharge power down mode.

2. CKE should be set high at least “1CLK + tSS” prior to Row active command.

3. Cannot violate minimum refresh specification. (32ms)

PRELIMINARY (October, 2001, Version 0.1) 45 AMIC Technology, Inc.

~

~

~

~

~

~

~

Precharge

Power-down

Exit

Row Active

Active

Power-down

Entry

~

~

~

~

~

~

~

~

Power-down

Qa2

Read Precharge

Active

Exit

: Don't care

A45L9332A Series

RAS

Self Refresh Entry & Exit Cycle

CLOCK

CKE

CS

RAS

CAS

ADDR

A10

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

* Note 2

* Note 1

t

SS

* Note 7 * Note 7

A9

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

* Note 3

~

~

~

~

~

~

~

~

~

~

~

~

~

~

* Note 4

t

SS

* Note 5

t

RC min.

~

~

~

~

~

~

~

~

~

~

~

~

* Note 6

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

WE

DSF

DQM

DQ

Self Refresh Entry

* Note : TO ENTER SELF REFRESH MODE

1.

2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.

3. The device remains in self refresh mode as long as CKE stays “Low”.
(cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE

4. System clock restart and be stable before returning CKE high.

5.

6. Minimum tRC is required after CKE going high to complete self refresh exit.

7. 2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit.

If the system uses burst refresh.

,

&

CS

starts from high.

CS

CAS

~

~

~

~

~

~

~

~

with CKE should be low at the same clock cycle.

Hi-ZHi-Z

Self Refresh Exit Auto Refresh

~

~

~

~

~

~

~

~

~

: Don't care

PRELIMINARY (October, 2001, Version 0.1) 46 AMIC Technology, Inc.

A45L9332A Series

RAS

RAS

Mode Register Set Cycle Auto Refresh Cycle

0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8 9 10

CLOCK

CKE

CS

RAS

CAS

ADDR

WE

DSF

High High

*Note 2

* Note 1

* Note 3

Key Ra

~

~

~

~

~

~

t

RC

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

DQM

DQ

MRS

New

Command

* Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.

MODE REGISTER SET CYCLE
* Note : 1.

,

CS

mode register.

2. Minimum 1 clock cycles should be met before new

3. Please refer to Mode Register Set table.

,

& WE activation and DSF of low at the same clock cycle with address key will set internal

CAS

Auto Refresh New Command

activation.

Hi-ZHi-Z

~

~

~

~

~

~

: Don't care

PRELIMINARY (October, 2001, Version 0.1) 47 AMIC Technology, Inc.

A45L9332A Series

RAS

WE

Function Truth Table (Table 1)

Current

State

IDLE

Row

Active

Read

CS

H X X X X X X NOP

L H H H X X X NOP
L H H L X X X ILLEGAL 2
L H L X X BA CA ILLEGAL 2
L L H H L BA RA Row Active; Latch Row Address; Non-IO Mask
L L H H H BA RA Row Active; latch Row Address; IO Mask
L L H L L BA PA NOP 4
L L H L H X X ILLEGAL
L L L H L X X Auto Refresh or Self Refresh 5
L L L H H X X ILLEGAL
L L L L L OP Code Mode Register Access 5
L L L L H OP Code Special Mode Register Access 6

H X X X X X X NOP

L H H H X X X NOP
L H H L X X X ILLEGAL 2
L H L H L BA CA,AP Begin Read; Latch CA; Determine AP
L H L H H X X ILLEGAL
L H L L L BA CA,AP Begin Write; Latch CA; Determine AP
L H L L H BA CA,AP Block Write; Latch CA; Determine AP
L L H H X BA RA ILLEGAL 2
L L H L L BA PA Precharge
L L H L H X X ILLEGAL
L L L H X X X ILLEGAL
L L L L L X X ILLEGAL
L L L L H OP Code Special Mode Register Access 6

H X X X X X X

L H H H X X X
L H H L L X X
L H H L H X X ILLEGAL
L H L H L BA CA,AP Term burst; Begin Read; Latch CA; Determine AP 3
L H L H H X X ILLEGAL
L H L L L BA CA,AP Term burst; Begin Write; Latch CA; Determine AP 3
L H L L H BA CA,AP Term burst; Block Write; Latch CA; Determine AP 3
L L H H X BA RA ILLEGAL 2
L L H L L BA PA Term Burst; Precharge timing for Reads 3
L L H L H X X ILLEGAL
L L L X X X X ILLEGAL

CAS

DSF

BA

(A10)

Address Action Note

NOP(Continue Burst to End →Row Active)
NOP(Continue Burst to End →Row Active)
Term burst →Row Active

PRELIMINARY (October, 2001, Version 0.1) 48 AMIC Technology, Inc.

A45L9332A Series

RAS

WE

Function Truth Table (Table 1, Continued)

Current

State

Write

Read with

Auto

Precharge

Write with

Auto

Precharge

Precharge

CS

H X X X X X X

L H H H X X X
L H H L L X X
L H H L H X X ILLEGAL
L H L H L BA CA,AP Term burst; Begin Read; Latch CA; Determine AP 3
L H L H H X X ILLEGAL
L H L L L BA CA,AP Term burst; Begin Write; Latch CA; Determine AP 3
L H L L H BA CA,AP Term burst; Block Write; Latch CA; Determine AP 3
L L H H X BA RA ILLEGAL 2
L L H L L BA PA Term Burst; Precharge timing for Writes 3
L L H L H X X ILLEGAL
L L L X X X X ILLEGAL

H X X X X X X

L H H H X X X
L H H L X X X ILLEGAL
L H L H X BA CA,AP ILLEGAL 2
L H L L X BA CA,AP ILLEGAL 2
L L H X X BA RA,PA ILLEGAL
L L L X X X X ILLEGAL 2

H X X X X X X

L H H H X X X
L H H L X X X ILLEGAL
L H L H X BA CA,AP ILLEGAL 2
L H L L X BA CA,AP ILLEGAL 2
L L H X X BA RA,PA ILLEGAL
L L L X X X X ILLEGAL 2

H X X X X X X

L H H H X X X
L H H L X X X ILLEGAL
L H L X X BA CA,AP ILLEGAL 2
L L H H X BA RA ILLEGAL 2
L L H L X BA PA
L L L X X X X ILLEGAL 4

CAS

DSF

BA

(A10)

Address Action Note

NOP(Continue Burst to End→Row Active)
NOP(Continue Burst to End→Row Active)
Term burst →Row Active)

NOP(Continue Burst to End→Precharge)
NOP(Continue Burst to End→Precharge)

NOP(Continue Burst to End→Precharge)
NOP(Continue Burst to End→Precharge)

NOP→Idle after tRP
NOP→Idle after tRP

NOP→Idle after tRP

2

PRELIMINARY (October, 2001, Version 0.1) 49 AMIC Technology, Inc.

A45L9332A Series

RAS

WE

Term Block Write: Precharge timing for Block

Function Truth Table (Table 1, Continued)

Current

State

Block
Write

Recovering

Row

Activating

Refreshing

Abbreviations
RA = Row Address (A0~A9) BA = Bank Address (A10) PA = Precharge All (A9)
NOP = No Operation Command CA = Column Address (A0~A7) AP = Auto Precharge (A9)

Note: 1. All entries assume that CKE was active (High) during the preceding clock cycle and the current clock cycle.

2. Illegal to bank in specified state : Function may be legal in the bank indicated by BA, depending on the state of that
bank.

3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.

4. NOP to bank precharging or in idle state. May precharge bank indicated by BA (and PA).

5. Illegal if any banks is not idle.

6. Legal only if all banks are in idle or row active state.

CS

H X X X X X X

L H H H X X X
L H H L X X X ILLEGAL
L H L X X BA CA,AP ILLEGAL 2
L L H H X BA RA ILLEGAL 2
L L H L X BA PA

L L L X X X X ILLEGAL 2

H X X X X X X

L H H H X X X
L H H L X X X ILLEGAL
L H L X X BA CA,AP ILLEGAL 2
L L H H X BA RA ILLEGAL 2
L L H L X BA PA ILLEGAL 2
L L L X X X X ILLEGAL 2

H X X X X X X

L H H X X X X
L H L X X X X ILLEGAL
L L H X X X X ILLEGAL
L L L X X X X ILLEGAL

CAS

DSF

BA

Address Action Note

(A10)

NOP→Row Active after tBWC
NOP→Row Active after tBWC

Write

NOP→Row Active after tRCD
NOP→Row Active after tRCD

NOP→Idle after tRC
NOP→Idle after tRC

2

PRELIMINARY (October, 2001, Version 0.1) 50 AMIC Technology, Inc.

A45L9332A Series

RAS

WE

Function Truth Table for CKE (Table 2)

Current

State

Self

Refresh

Both

Bank

Precharge

Power

Down

All

Banks

Idle

Any State

Other than

Listed

Above

Abbreviations : ABI = All Banks Idle

Note: 7. After CKE’s low to high transition to exit self refresh mode. And a time of tRC(min) has to be elapse after CKE’s low

to high transition to issue a new command.

8. CKE low to high transition is asynchronous as if restarts internal clock.

A minimum setup time “tSS + one clock” must be satisfied before any command other than exit.

9. Power-down and self refresh can be entered only from the all banks idle state.

10. Must be a legal command.

CKE

CKE

n-1

H X X X X X X X INVALID

L H H X X X X X
L H L H H H X X
L H L H H L X X ILLEGAL
L H L H L X X X ILLEGAL
L H L L X X X X ILLEGAL
L L X X X X X X NOP(Maintain Self Refresh)

H X X X X X X X INVALID

L H H X X X X X
L H L H H H X X
L H L H H L X X ILLEGAL
L H L H L X X X ILLEGAL
L H L L X X X X ILLEGAL

L L X X X X X X NOP(Maintain Power Down Mode)
H H X X X X X X Refer to Table 1
H L H X X X X X Enter Power Down 9
H L L H H H X X Enter Power Down 9
H L L H H L X X ILLEGAL
H L L H L X X X ILLEGAL
H L L L H X X X ILLEGAL
H L L L L H L X Enter Self Refresh 9
H L L L L L X X ILLEGAL

L L X X X X X X NOP
H H X X X X X X Refer to Operations in Table 1
H L X X X X X X Begin Clock Suspend next cycle 10

L H X X X X X X Exit Clock Suspend next cycle 10

L L X X X X X X Maintain clock Suspend

n

CS

CAS

DSF Address Action Note

Exit Self Refresh→ABI after tRC
Exit Self Refresh→ABI after tRC

Exit Power Down→ABI
Exit Power Down→ABI

7
7

8
8

PRELIMINARY (October, 2001, Version 0.1) 51 AMIC Technology, Inc.

A45L9332A Series

Ordering Information

Part No. Cycle Time (ns) Clock Frequency (MHz) Access Time Package

A45L9332AF-6 6 166 5.5 ns @ CL = 3 100 QFP

A45L9332AE-6 6 166 5.5 ns @ CL = 3 100 LQFP

A45L9332AF-7 7 143 6.0 ns @ CL = 3 100 QFP

A45L9332AE-7 7 143 6.0 ns @ CL = 3 100 LQFP

A45L9332AF-8 8 125 6.5 ns @ CL = 3 100 QFP

A45L9332AE-8 8 125 6.5 ns @ CL = 3 100 LQFP

* QFP (Height = 3.0mm Max)

LQFP (Height = 1.4mm Max)

PRELIMINARY (October, 2001, Version 0.1) 52 AMIC Technology, Inc.

A45L9332A Series

Package Information

QFP 100L Outline Dimensions unit: inches/mm

HE

80

81

D

HD

100

1 30

θ

E

e

51

50

31

b

Symbol

A1 0.004 - - 0.100 - ­A2 0.107 0.112 0.117 2.723 2.85 2.977

b 0.010 - 0.014 0.26 - 0.36
c 0.0057 0.006 0.0063 0.142 0.150 0.158

HE 0.905 0.913 0.921 22.950 23.200 23.450

E 0.783 0.787 0.791 19.900 20.000 20.100

HD 0.669 0.677 0.685 16.950 17.200 17.450

D 0.547 0.551 0.555 13.900 14.000 14.100

e 0.020 0.026 0.032 0.500 0.650 0.800
L 0.025 0.031 0.037 0.650 0.800 0.950

L1 0.057 0.063 0.069 1.450 1.600 1.750

y - - 0.004 - - 0.100
θ 0°

Dimensions in inches Dimensions in mm

Min. Nom. Max. Min. Nom. Max.

-

8° 0°

A1A2

y

D

L1

L

c

-

8°

Notes:

1. Dimensions D and E do not include mold protrusion.

2. Dimensions b does not include dambar protrusion.
Total in excess of the b dimension at maximum material condition.
Dambar cannot be located on the lower radius of the foot.

PRELIMINARY (October, 2001, Version 0.1) 53 AMIC Technology, Inc.

A45L9332A Series

Package Information
LQFP 100L Outline Dimensions unit: inches/mm

HE

80

81

D

HD

100

1 30

θ

E

e

51

50

31

b

Symbol

A1 0.002 - - 0.05 - ­A2 0.053 0.055 0.057 1.35 1.40 1.45

b 0.011 0.013 0.015 0.27 0.32 0.37
c 0.005 - 0.008 0.12 - 0.20

HE 0.860 0.866 0.872 21.85 22.00 22.15

E 0.783 0.787 0.791 19.90 20.00 20.10

HD 0.624 0.630 0.636 15.85 16.00 16.15

D 0.547 0.551 0.555 13.90 14.00 14.10

e 0.026 BSC 0.65 BSC
L 0.018 0.024 0.030 0.45 0.60 0.75

L1 0.039 REF 1.00 REF

y - - 0.004 - - 0.1
θ 0° 3.5° 7° 0° 3.5° 7°

Dimensions in inches Dimensions in mm
Min. Nom. Max. Min. Nom. Max.

A1A2

y

D

L1

L

c

Notes:

1. Dimensions D and E do not include mold protrusion.

2. Dimensions b does not include dambar protrusion.
Total in excess of the b dimension at maximum material condition.
Dambar cannot be located on the lower radius of the foot.

PRELIMINARY (October, 2001, Version 0.1) 54 AMIC Technology, Inc.