Datasheet A43P26161 Datasheet (AMIC)

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A43P26161

Preliminary 1M X 16 Bit X 4 Banks Low Power Synchronous DRAM

Document Title
1M X 16 Bit X 4 Banks Low Power Synchronous DRAM

Revision History

Rev. No.

History Issue Date Remark

0.0 Initial issue September 13, 2004 Preliminary

1.0 Modify to 133MHz & 105MHz June 10, 2005
Modify all DC specification for new product

1.1 Modify t

SS from 3ns to 2ns July 11, 2005

PRELIMINARY (July, 2005, Version 1.1) AMIC Technology, Corp.

A43P26161

(

A

A8 A7A6A0A1A

A4A3A

Preliminary 1M X 16 Bit X 4 Banks Low Power Synchronous DRAM

Features

 Low power supply

- VDD: 2.5V VDDQ : 2.5V

 LVCMOS compatible with multiplexed address
 Four banks / Pulse

 MRS cycle with address key programs

- CAS Latency (2 & 3)

- Burst Length (1,2, 4,8 & full page)

- Burst Type (Sequential & Interleave)

 All inputs are sampled at the positive going edge of the

system clock

 Deep Power Down Mode
 DQM for masking
 Auto & self refresh
 Clock Frequency (max) : 105MHz @ CL=3 (-95)

133MHz @ CL=3 (-75)

RAS

General Description

The A43P26161 is 67,108,864 bits Low Power
synchronous high data rate Dynamic RAM organized as 4
X 1,048,576 words by 16 bits, fabricated with AMIC’s high
performance CMOS technology. Synchronous design
allows precise cycle control with the use of system clock.

 64ms refresh period (4K cycle)
 Self refresh with programmable refresh period through

EMRS cycle

 Programmable Power Reduction Feature by partial

array activation during Self-refresh through EMRS
cycle

 Industrial operating temperature range: -40ºC to +85ºC

for -U series.

 Available in 54 Balls CSP (8mm X 8mm) and 54-pin

TSOP(II) packages.

 Package is available to lead free (-F series)

I/O transactions are possible on every clock cycle. Range
of operating frequencies, programmable latencies allows
the same device to be useful for a variety of high
bandwidth, high performance memory system
applications.

Pin Configuration

 54 Balls CSP (8 mm x 8 mm)

Top View

1 2 3 7 8 9

VSS DQ15 VSSQ VDDQ DQ0 VDD
B DQ14 DQ13 VDDQ VSSQ DQ2 DQ1
C DQ12 DQ11 VSSQ VDDQ DQ4 DQ3
D DQ10 DQ9 VDDQ VSSQ DQ6 DQ5
E DQ8 NC VSS VDD LDQM DQ7
F UDQM CLK CKE

G NC A11 A9 BA0 BA1
H

J VSS A5

54 Ball

6X9) CSP

CAS

RAS

WE

CS

10

2 VDD

PRELIMINARY (July, 2005, Version 1.1) 1 AMIC Technology, Corp.

A43P26161

Pin Configuration (continued)

 54 TSOP (II)

Block Diagram

VSS

15

DQ

14

VSSQ

DQ

DQ13

12

DQ

VDDQ

DQ11

10

DQ

VSSQ

DQ9

8

VDDQ

DQ

VSS

NC

UDQM

CLK

A11

CKE

NC

A9A8A7A6A5A4VSS

54 53 52 51 50 49 48 47 46 45 4344 42 41 40 39 38 37 36 35 34 33 32 31 30

A43P26161V

12345678 910 1211 13 14 15 16 17 18 19 20 21 22 23 24 25

1

VDD

0

DQ

DQ

VDDQ

3

DQ2

DQ

VSSQ

DQ4

5

DQ

VDDQ

7

DQ

DQ6

VSSQ

WE

VDD

LDQM

CAS

RAS

CS

BS0

BS1

A0A1A2

A10/AP

I/O Control Output Buffer

LWE

2829

26 27

A3

VDD

CLK

ADD

LRAS

Bank Select

Refresh Counter

Address Register

LRAS

LRAS LCBR LWE

Row Buffer

LCBR

Row Decoder Column Buffer

LCAS

Timing Register

Data Input Register

1M X 16

Sense AMP
1M X 16
1M X 16
1M X 16

Column Decoder

Latency & Burst Length

Programming Register

LWCBR

DQM

DQi

DQM

CLK CKE

RAS CAS WE

CS

DQM

PRELIMINARY (July, 2005, Version 1.1) 2 AMIC Technology, Corp.

A43P26161

Pin Descriptions

Symbol Name Description

CLK System Clock Active on the positive going edge to sample all inputs.

CS

CKE Clock Enable

A0~A11 Address

BS0, BS1 Bank Select Address

RAS

CAS

WE

L(U)DQM

Chip Select

Row Address Strobe

Column Address
Strobe

Write Enable Enables write operation and Row precharge.

Data Input/Output
Mask

Disables or Enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM

Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one clock + tss prior to new command.
Disable input buffers for power down in standby.
Row / Column addresses are multiplexed on the same pins.
Row address : RA0~RA11, Column address: CA0~CA7
Selects bank to be activated during row address latch time.
Selects band for read/write during column address latch time.

Latches row addresses on the positive going edge of the CLK with
Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with
Enables column access.

Makes data output Hi-Z, t SHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.

RAS low.

CAS low.

DQ0-15 Data Input/Output Data inputs/outputs are multiplexed on the same pins.

VDD/VSS

VDDQ/VSSQ

NC/RFU No Connection

Power
Supply/Ground

Data Output
Power/Ground

Power Supply: +2.3V ~ 2.7V/Ground

Provide isolated Power/Ground to DQs for improved noise immunity.

PRELIMINARY (July, 2005, Version 1.1) 3 AMIC Technology, Corp.

A43P26161

Absolute Maximum Ratings*

Voltage on any pin relative to VSS (Vin, Vout ) . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +3.0V

Voltage on VDD supply relative to VSS (VDD, VDDQ )

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to + 3.0V

Storage Temperature (T
Soldering Temperature X Time (T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

Power Dissipation (P

Short Circuit Current (Ios) . . . . . . . . . . . . . . . . . . . . 50mA

STG) . . . . . . . . . . -55°C to +150°C

SLODER) . . . . . . . . . . . . . .

°C X 10sec

D) . . . . . . . . . . . . . . . . . . . . . . . . 0.8W

*Comments

Permanent device damage may occur if “Absolute
Maximum Ratings” are exceeded.
Functional operation should be restricted to recommended
operating condition.
Exposure to higher than recommended voltage for
extended periods of time could affect device reliability.

Capacitance (TA=25°C, f=1MHz)

Parameter Symbol Condition Min Max Unit

Input Capacitance CI1 A0 to A11, BS0, BS1 2.0 4.0 pF

,

CI2
Data Input/Output Capacitance CI/O DQ0 to DQ15 3.5 6.0 pF

CLK, CKE,

CS, RAS,CAS

WE

, DQM

2.0 4.0 pF

DC Electrical Characteristics

Recommend operating conditions
(Voltage referenced to VSS=0V, T

A = 0ºC to +70ºC for commercial or TA =-40ºC to +85ºC for extended)

Parameter Symbol Min Typ Max Unit Note

Supply Voltage VDD 2.3 2.5 2.7 V
DQ Supply Voltage VDDQ 2.3 2.5 2.7 V
Input High Voltage VIH 0.8*VDDQ - VDDQ+0.3 V
Input Low Voltage VIL -0.3 - 0.3 V Note 1
Output High Voltage VOH VDDQ - 0.2 - - V IOH = -0.1mA
Output Low Voltage VOL - - 0.2 V IOL = 0.1mA
Input Leakage Current IIL -1 - 1
Output Leakage Current IOL -1.5 - 1.5
Output Loading Condition See Fig. 1 (Page 6)

Note: 1. VIL (min) = -1.5V AC (pulse width ≤ 5ns).

2. Any input 0V

3. Dout is disabled, 0V

≤ VIN ≤ VDD + 0.3V, all other pins are not under test = 0V

≤ Vout ≤ VDD

µA
µA

Note 2
Note 3

PRELIMINARY (July, 2005, Version 1.1) 4 AMIC Technology, Corp.

A43P26161

Decoupling Capacitance Guide Line

Recommended decoupling capacitance added to power line at board.

Parameter Symbol Value Unit

Decoupling Capacitance between VDD and VSS CDC1 0.1 + 0.01

Decoupling Capacitance between VDDQ and VSSQ CDC2 0.1 + 0.01

µF

µF

Note: 1. VDD and VDDQ pins are separated each other.

All VDD pins are connected in chip. All VDDQ pins are connected in chip.

2. VSS and VSSQ pins are separated each other
All VSS pins are connected in chip. All VSSQ pins are connected in chip.

DC Electrical Characteristics

(Recommended operating condition unless otherwise noted, TA = 0ºC to +70ºC for commercial or TA = -40ºC to +85ºC for extended)

Symbol Parameter Test Conditions

Icc1

Icc2 P

Icc2 PS

ICC2N

ICC2NS

Operating Current
(One Bank Active)

Precharge Standby Current
in power-down mode

Precharge Standby Current
in non power-down mode

Burst Length = 1
t

RC ≥ tRC(min), tCC ≥ tCC(min), IOL = 0mA

CKE

≤ VIL(max), tCC = 15ns

CKE

≤ VIL(max), tCC = ∞

≥ VIH(min), CS ≥ VIH(min), tCC = 15ns

CKE
Input signals are changed one time during 30ns

CKE

≥ VIH(min), CLK ≤ VIL(max), tCC = ∞

Input signals are stable.

Speed

-75 -95

40

0.3

0.5

5.5

2

Units Note

mA 1

mA

mA

ICC3P

Active Standby current in

CKE

≤ VIL(max), tCC = 15ns

non power-down mode

≥ VIH(min), CS ≥ VIH(min), tCC = 15ns

ICC3N

ICC4

(One Bank Active)

Operating Current
(Burst Mode)

ICC5 Refresh Current

ICC6 Self Refresh Current

ICC7 Deep Power Down Current

CKE
Input signals are changed one time during 30ns

I

OL = 0mA, Page Burst

All bank Activated, t

t

RC ≥ tRC (min)

CKE

≤ 0.2V

CKE

≤ 0.2V

CCD = tCCD (min)

TCSR Range

4 Banks 400 450 500
2 Banks 250 260 300

1 Banks 150 180 180
1/2 Bank 100 120 120
1/4 Bank 80 90 100

Note: 1. Measured with outputs open. Addresses are changed only one time during tCC(min).

2. Refresh period is 64ms. Addresses are changed only one time during t

CC(min).

1.5

12

50

90

<45°C <70°C <85°C

10

mA

mA 1

mA 2

uA

uA

PRELIMINARY (July, 2005, Version 1.1) 5 AMIC Technology, Corp.

A43P26161

AC Operating Test Conditions

(VDD = 2.3V~2.7V, T

Parameter Value Unit

AC input levels 0.9 x VDDQ/0.2 V
Input timing measurement reference level 0.5 x VDDQ V
Input rise and all time (See note3) tr/tf = 1/1 ns
Output timing measurement reference level 0.5 x VDDQ V
Output load condition See Fig.2

Output

A = 0ºC to +70ºC for commercial or TA =-40ºC to +85ºC for extended)

VDDQ

V

500Ω

500Ω

OH(DC) = VDDQ-0.2V, IOH = -0.1mA
OL(DC) = 0.2V, IOL = 0.1mA

V

30pF

OUTPUT

ZO=50Ω

TT =0.5V x VDDQ

V
50Ω

30pF

(Fig. 1) DC Output Load Circuit

(Fig. 2) AC Output Load Circuit

AC Characteristics

(AC operating conditions unless otherwise noted)

Symbol Parameter

tCC CLK cycle time

tSAC

tOH Output data hold time 2.5 - 2.5 - ns 2

tCH CLK high pulse width

tCL CLK low pulse width

tSS Input setup time

tSH Input hold time 1.5 - 1.5 - ns 3

tSLZ CLK to output in Low-Z 1 - 1 - ns 2

tSHZ CLK to output in Hi-Z

CL=CAS Latency. *All AC parameters are measured from half to half.

CLK to valid
Output delay

-75 -95
Unit Note

Min Max Min Max

CL=3 7.5 9.5
CL=2 12
CL=3 - 6 - 7
CL=2 - 9 - 8

CL=3 3 - 3.5 ­CL=2 3 - 3.5 ­CL=3 3 - 3.5 ­CL=2 3 - 3.5 ­CL=3 2 - 2 -

1000

15

1000

ns

ns 1,2

ns 3

ns 3

ns 3

1

CL=2 2 - 2 -

CL=3 - 6 - 7
CL=2 - 8 - 8

ns

Note : 1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e.,

[(tr + tf)/2-1]ns should be added to the parameter.

PRELIMINARY (July, 2005, Version 1.1) 6 AMIC Technology, Corp.

A43P26161

Operating AC Parameter

(AC operating conditions unless otherwise noted)

Version

Symbol Parameter

-75 -95

tRRD(min) Row active to row active delay 2 2 CLK 1

Unit Note

tRCD(min)

tRP(min) Row precharge time 19 24 ns 1
tRAS(min) 45 60 ns 1
tRAS(max)

tRC(min) Row cycle time 64 84 ns 1

tCDL(min) Last data in new col. Address delay 7.5 9.5 ns 2
tRDL(min) Last data in row precharge 2 2 CLK 1, 2
tBDL(min) Last data in to burst stop 7.5 9.5 ns 2
tCCD(min) Col. Address to col. Address delay 7.5 9.5 ns

Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and

2. Minimum delay is required to complete write.

RAS to

Row active time

then rounding off to the next higher integer.

CAS

delay

19 24 ns 1

100 100

µs

PRELIMINARY (July, 2005, Version 1.1) 7 AMIC Technology, Corp.

A43P26161

Simplified Truth Table

Command CKEn-1 CKEn

Register

Extended Mode Register Set H X L L L L L OP CODE 1,2
Refresh

Bank Active & Row Addr. H X L L H H X V Row Addr. 4

Column Addr.

Column Addr.
Burst Stop H X L H H L X X

Precharge

Clock Suspend or
Active Power Down

Precharge Power Down Mode

DQM H X V X 6
No Operation Command H X
Deep Power Down Entry H L L H H L X X

Deep Power Down Exit L H X X X X X X 7

Note : 1. OP Code: Operand Code

2. MRS can be issued only when all banks are at precharge state.

3. Auto refresh functions is same as CBR refresh of DRAM.

4. BS0, BS1 : Bank select address.

5. During burst read or write with auto precharge, new read/write command cannot be issued.

6. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0)
but masks the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)

7. After Deep Power Down mode exit, a full new initialization of the memory device is mandatory.

Mode Register Set

Auto Refresh H
Self
Refresh

Auto Precharge Disable L 4 Read &
Auto Precharge Enable
Auto Precharge Disable L 4 Write &
Auto Precharge Enable

Bank Selection V L
Both Banks

(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)

A0~A11, BS0, BS1: Program keys. (@MRS, EMRS)
A new command can be issued after 2 clock cycle of MRS, EMRS.
The automatical precharge without Row precharge command is meant by “Auto”.

Auto/Self refresh can be issued only when all banks are at precharge state.
If both BS1 and BS0 are “Low” at read, write, row active and precharge, bank A is selected.

If both BS1 is “Low” and BS0 is “High” at read, write, row active and precharge, bank B is selected.
If both BS1 is “High” and BS0 is “Low” at read, write, row active and precharge, bank C is selected.
If both BS1 and BS0 are “High” at read, write, row active and precharge, bank D is selected.
If A10/AP is “High” at row precharge, BS1 and BS0 is ignored and all banks are selected.

Another bank read/write command can be issued at every burst length.

Entry

Exit L H

Entry

Exit L H X X X X X

Entry H L

Exit L H

H X L L L L X OP CODE

H

H X L H L H X V

H X L H L L X V

H X L L H L X

H L

CS RAS

L L L H X X

L

L H H H 3

H X X X

L H H H

H X X X

L H H H

H X X X

L V V V

H X X X

L H H H

H X X X

CAS

WE

DQM BS0

X X

X

X

X

X X

A10

BS1

/AP

H

H

X H

A9~A0,

A11

Column

Addr.

Column

Addr.

X

X

X

Notes

1,2

3
3

3

4,5

4,5

PRELIMINARY (July, 2005, Version 1.1) 8 AMIC Technology, Corp.

A43P26161

Mode Register Filed Table to Program Modes

Register Programmed with MRS

Address BS1 BS0 A11,A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Function 0 0 RFU W.B.L TM CAS Latency BT Burst Length

(Note 3) (Note 1) (Note 2)

Test Mode CAS Latency Burst Type Burst Length

A8 A7 Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT=0 BT=1

0 0 Mode Register Set 0 0 0 Reserved 0 Sequential 0 0 0 1 1
0 1 0 0 1 - 1 Interleave 0 0 1 2 2
1 0 0 1 0 2 0 1 0 4 4

1 1

Vendor

Use

Only

0 1 1 3 0 1 1 8 8

Write Burst Length

A9 Length

0 Burst 1 1 0 Reserved 1 1 0 Reserved Reserved
1 Single Bit 1 1 1 Reserved

Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.

2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.

3. BS0, BS1 must be 0,0 to select the Mode Register (vs. the Extended Mode Register).

1 0 0 Reserved 1 0 0 Reserved Reserved
1 0 1 Reserved 1 0 1 Reserved Reserved

1 1 1 256(Full) Reserved

Extended Mode Register Table

BS1 BS0 A11, A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus (Ax)

↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓

1 0 All have to be set to “0” DS TCSR PASR

(Note)

Driver Strength

Temperature-Compensated Self-Refresh:

Driver Strength A4 A3 Max. Case Temp.

A6 A5 Driver Strength

0 0 Full 0 1
0 1 1/2 1 0
1 0 1/4 1 1

Note: BS1 and BS0 must be 1, 0 to select the Extended Mode Register (vs. the Mode Register)

0 0

70
45
15
85

°C
°C
°C
°C

A2 A1 A0 Banks to be Self-Refreshed

0 0 0 All banks
0 0 1 Bank A, Bank B
0 1 0 Bank A
0 1 1 Reserved
1 0 0 Reserved
1 0 1 1/2 of Bank A
1 1 0 1/4 of Bank A
1 1 1 Reserved

Partial-Array Self Refresh:

PRELIMINARY (July, 2005, Version 1.1) 9 AMIC Technology, Corp.

A43P26161

Power Up Sequence

1. Apply power and start clock, Attempt to maintain CKE = “H”, DQM = “H” and the other pins are NOP condition at inputs.

2. Maintain stable power, stable clock and NOP input condition for a minimum of 200

3. Issue precharge commands for all banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register. The device is now ready for normal operation.

6. Issue a extended mode register set command to define DS or PASR operating type of the device after normal MRS.
cf.) Sequence of 4 & 5 may be changed.

EMRS cycle is not mandatory and the EMRS command needs to be issued only when DS or PASR is used.
The default state without EMRS command issued is the half driver strength and full array refreshed.
The device is now ready for the operation selected by EMRS.
For operating with DS or PASR, set DS or PASR mode in EMRS setting stage.
In order to adjust another mode in the state of DS or PASR mode, additional EMRS set is required but power up sequence is not
needed again at this time. In that case, all banks have to be in idle state prior to adjusting EMRS set.

Burst Sequence (Burst Length = 4)

µs.

Initial address

A1 A0

0 0 0 1 2 3 0 1 2 3
0 1 1 2 3 0 1 0 3 2
1 0 2 3 0 1 2 3 0 1
1 1 3 0 1 2 3 2 1 0

Sequential Interleave

Burst Sequence (Burst Length = 8)

Initial address

Sequential Interleave

A2 A1 A0

0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6
0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5
0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4
1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3
1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2
1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1
1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0

PRELIMINARY (July, 2005, Version 1.1) 10 AMIC Technology, Corp.

,

CAS

and

CS

RAS

CAS

are high, the SDRAM

WE

high.

RAS

,

high disables the

CS

and

CAS

WE

and

,

WE

, and all

CAS

, BS0

The clock signal must also be asserted at the same time.

2. After VDD reaches the desired voltage, a minimum pause
of 200 microseconds is required with inputs in NOP
condition.

3. All banks must be precharged now.

4. Perform a minimum of 2 Auto refresh cycles to stabilize
the internal circuitry.

5. Perform a MODE REGISTER SET cycle to program the
CAS latency, burst length and burst type as the default
value of mode register is undefined.

At the end of one clock cycle from the mode register set
cycle, the device is ready for operation.
When the above sequence is used for Power-up, all the
out-puts will be in high impedance state. The high
impedance of outputs is not guaranteed in any other
power-up sequence.
cf.) Sequence of 4 & 5 may be changed.

Mode Register Set (MRS)

The mode register stores the data for controlling the various
operation modes of SDRAM. It programs the CAS latency,
addressing mode, burst length, test mode and various
vendor specific options to make SDRAM useful for variety of
different applications. The default value of the mode register
is not defined, therefore the mode register must be written
after power up to operate the SDRAM. The mode register is

written by asserting low on
SDRAM should be in active mode with CKE already high

prior to writing the mode register). The state of address pins
A0~A11, BS0 and BS1 in the same cycle as

,

CS

RAS
mode register. One clock cycle is required to complete the
write in the mode register. The mode register contents can
be changed using the same command and clock cycle
requirements during operation as long as all banks are in the
idle state. The mode register is divided into various fields
depending on functionality. The burst length field uses
A0~A2, burst type uses A3, addressing mode uses A4~A6,
A7~A8, A9, BS0 and BS1 are used for vendor specific
options or test mode. And the write burst length is
programmed using A9. A7~A8, A10~A11, BS0 and BS1
must be set to low for normal SDRAM operation.
Refer to table for specific codes for various burst length,
addressing modes and CAS latencies. BS0 and BS1 have to
be set to “0” to enter the Mode Register.

Extended Mode Register (EMRS)

The Extended Mode Register controls functions beyond
those controlled by the Mode Register. These additional
functions are unique to AMIC’s Low Power SDRAM and
includes a Refresh Period field (TCSR) for temperature
compensated self-refresh and a Partial-Array Self Refresh
field (PASR). The PASR field is used to specify whether only
bank A and bank B,or bank A,or 1/2 of bank A,or 1/4 of bank
A be refreshed. Disable banks will not be refreshed in Self­Refresh mode and written data will be lost. When only bank
A is selected it is possible to partial select only half or one
quarter of bank A. The TCR field has four entries to set
Refresh Period during self-refresh depending on the case
temperature of the Low Power devices.
The Extended Mode Register is programmed via the Mode
Register Set command (with BS0=0 and BS1=1) and retains

,

CAS

,

going low is the data written in the

WE

CS

,

RAS

,

CAS

,

WE

(The

A43P26161

Device Operations

Clock (CLK)

The clock input is used as the reference for all SDRAM
operations. All operations are synchronized to the positive
going edge of the clock. The clock transitions must be
monotonic between VIL and VIH. During operation with CKE
high all inputs are assumed to be in valid state (low or high)
for the duration of set up and hold time around positive edge
of the clock for proper functionality and ICC specifications.

Clock Enable (CKE)

The clock enable (CKE) gates the clock onto SDRAM. If
CKE goes low synchronously with clock (set-up and hold
time same as other inputs), the internal clock is suspended
from the next clock cycle and the state of output and burst
address is frozen as long as the CKE remains low. All other
inputs are ignored from the next clock cycle after CKE goes
low. When all banks are in the idle state and CKE goes low
synchronously with clock, the SDRAM enters the power
down mode from the next clock cycle. The SDRAM remains
in the power down mode ignoring the other inputs as long as
CKE remains low. The power down exit is synchronous as
the internal clock is suspended. When CKE goes high at

SS + 1 CLOCK” before the high going edge of the

least “t
clock, then the SDRAM becomes active from the same clock
edge accepting all the input commands.

Bank Select (BS0, BS1)

This SDRAM is organized as 4 independent banks of
1,048,576 words X 16 bits memory arrays. The BS0, BS1

inputs is latched at the time of assertion of

to select the bank to be used for the operation. The bank
select BS0, BS1 is latched at bank activate, read, write
mode register set and precharge operations.

Address Input (A0 ~ A11)

The 20 address bits required to decode the 1,048,576 word
locations are multiplexed into 12 address input pins
(A0~A11). The 12 bit row address is latched along with

, BS0 and BS1 during bank activate command. The 8

RAS

bit column address is latched along with
and BS1during read or write command.

NOP and Device Deselect

When
performs no operation (NOP). NOP does not initiate any new

operation, but is needed to complete operations which
require more than single clock like bank activate, burst read,
auto refresh, etc. The device deselect is also a NOP and is

entered by asserting
command decoder so that

the address inputs are ignored.

Power-Up

The following sequence is recommended for POWER UP

1. Power must be applied to either CKE and DQM inputs to

RAS

pull them high and other pins are NOP condition at the
inputs before or along with VDD (and VDDQ) supply.

PRELIMINARY (July, 2005, Version 1.1) 11

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A43P26161

S

the stored information until it is programmed again or the
device loses power. The Extended Mode Register must be
loaded when all banks are idle, and the controller must wait
the specified time before initiating any subsequent operation.
Violating either these requirements result in unspecified
operation. Unused bit A7 to A11 have to be set to “0”.

Bank Activate

The bank activate command is used to select a random row
in an idle bank. By asserting low on

RAS

and

CS

with

desired row and bank addresses, a row access is initiated.
The read or write operation can occur after a time delay of
t

RCD(min) from the time of bank activation. tRCD(min) is an

internal timing parameter of SDRAM, therefore it is
dependent on operating clock frequency. The minimum
number of clock cycles required between bank activate and
read or write command should be calculated by dividing
t

RCD(min) with cycle time of the clock and then rounding off

the result to the next higher integer. The SDRAM has 4
internal banks on the same chip and shares part of the
internal circuitry to reduce chip area, therefore it restricts the
activation of all banks simultaneously. Also the noise
generated during sensing of each bank of SDRAM is high
requiring some time for power supplies to recover before the
other bank can be sensed reliably. t

RRD(min) specifies the

minimum time required between activating different banks.
The number of clock cycles required between different bank
activation must be calculated similar to t

RCD specification.

The minimum time required for the bank to be active to
initiate sensing and restoring the complete row of dynamic
cells is determined by t

RAS(min) specification before a

precharge command to that active bank can be asserted.
The maximum time any bank can be in the active state is
determined by t
t

RAS(min) and tRAS(max) can be calculated similar to tRCD

RAS(max). The number of cycles for both

specification.

Burst Read

The burst read command is used to access burst of data on
consecutive clock cycles from an active row in an active
bank. The burst read command is issued by asserting low on

and

C

the clock. The bank must be active for at least t

CAS

with

being high on the positive edge of

WE

RCD(min)

before the burst read command is issued. The first output
appears CAS latency number of clock cycles after the issue
of burst read command. The burst length, burst sequence
and latency from the burst read command is determined by
the mode register which is already programmed. The burst
read can be initiated on any column address of the active
row. The address wraps around if the initial address does not
start from a boundary such that number of outputs from each
I/O are equal to the burst length programmed in the mode
register. The output goes into high-impedance at the end of
the burst, unless a new burst read was initiated to keep the
data output gapless. The burst read can be terminated by
issuing another burst read or burst write in the same bank or
the other active bank or a precharge command to the same
bank. The burst stop command is valid at every page burst
length.

Burst Write

The burst write command is similar to burst read command,
and is used to write data into the SDRAM consecutive clock

cycles in adjacent addresses depending on burst length and

,

burst sequence. By asserting low on

CS

CAS

and

WE

with valid column address, a write burst is initiated. The data
inputs are provided for the initial address in the same clock
cycle as the burst write command. The input buffer is
deselected at the end of the burst length, even though t he
internal writing may not have been completed yet. The burst
write can be terminated by issuing a burst read and DQM for
blocking data inputs or burst write in the same or the other
active bank. The burst stop command is valid only at full
page burst length where the writing continues at the end of
burst and the burst is wrap around. The write burst can also
be terminated by using DQM for blocking data and
precharging the bank “t

RDL” after the last data input to be

written into the active row. See DQM OPERATION also.

DQM Operation

The DQM is used to mask input and output operation. It
works similar to

during read operation and inhibits

OE

writing during write operation. The read latency is two cycles
from DQM and zero cycle for write, which means DQM
masking occurs two cycles later in the read cycle and occurs
in the same cycle during write cycle. DQM operation is
synchronous with the clock, therefore the masking occurs for
a complete cycle. The DQM signal is important during burst
interrupts of write with read or precharge in the SDRAM. Due
to asynchronous nature of the internal write, the DQM
operation is critical to avoid unwanted or incomplete writes
when the complete burst write is not required.

Precharge

The precharge operation is performed on an active bank by

,

,

asserting low on

CS

RAS

and A10/AP with valid BA

WE

of the bank to be precharged. The precharge command can
be asserted anytime after t
activate command in the desired bank. “t

RAS(min) is satisfied from the bank

RP” is defined as the

minimum time required to precharge a bank.
The minimum number of clock cycles required to complete
row precharge is calculated by dividing “t

RP” with clock cycle

time and rounding up to the next higher integer. Care should
be taken to make sure that burst write is completed or DQM
is used to inhibit writing before precharge command is
asserted. The maximum time any bank can be active is
specified by t
precharged within t

RAS(max). Therefore, each bank has to be

RAS(max) from the bank activate

command. At the end of precharge, the bank enters the idle
state and is ready to be activated again.
Entry to Power Down, Auto refresh, Self refresh and Mode
register Set etc, is possible only when all banks are in idle
state.

Auto Precharge

The precharge operation can also be performed by using
auto precharge. The SDRAM internally generates the timing
to satisfy t
and CAS latency. The auto precharge command is issued at
the same time as burst read or burst write by asserting high
on A10/AP. If burst read or burst write command is issued
with low on A10/AP, the bank is left active until a new
command is asserted. Once auto precharge command is
given, no new commands are possible to that particular bank
until the bank achieves idle state.

RAS(min) and “tRP” for the programmed burst length

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All Banks Precharge

All banks can be precharged at the same time by using
Precharge all command. Asserting low on

with high on A10/AP after both banks have satisfied

WE

t

RAS(min) requirement, performs precharge on all banks. At

the end of tRP after performing precharge all, all banks are
in idle state.

Auto Refresh

The storage cells of SDRAM need to be refreshed every
64ms to maintain data. An auto refresh cycle accomplishes
refresh of a single row of storage cells. The internal counter
increments automatically on every auto refresh cycle to
refresh all the rows. An auto refresh command is issued by

asserting low on
and

. The auto refresh command can only be asserted

WE

CS

,

RAS

and

with high on CKE

CAS

with all banks being in idle state and the device is not in
power down mode (CKE is high in the previous cycle). The
time required to complete the auto refresh operation is
specified by “t
required can be calculated by dividing “t

RC(min)”. The minimum number of clock cycles

RC” with clock cycle

time and then rounding up to the next higher integer. The
auto refresh command must be followed by NOP’s until the
auto refresh operation is completed. All banks will be in the
idle state at the end of auto refresh operation. The auto
refresh is the preferred refresh mode when the SDRAM is
being used for normal data transactions. The auto refresh
cycle can be performed once in 15.6us or a burst of 4096
auto refresh cycles once in 64ms.

CS

,

RAS

and

Self Refresh

The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode for
data retention and low power operation of SDRAM. In self
refresh mode, the SDRAM disables the internal clock and all
the input buffers except CKE. The refresh addressing and
timing is internally generated to reduce power consumption.
The self refresh mode is entered from all banks idle state by

asserting low on

. Once the self refresh mode is entered, only CKE state

WE

CS

,

RAS

,

and CKE with high on

CAS

being low matters, all the other inputs including clock are
ignored to remain in the self refresh.
The self refresh is exited by restarting the external clock and
then asserting high on CKE. This must be followed by NOP’s
for a minimum time of “t

RC” before the SDRAM reaches idle

state to begin normal operation. If the system uses burst
auto refresh during normal operation, it is recommended to
used burst 4096 auto refresh cycles immediately after exiting
self refresh.

Deep Power Down Mode

The Deep Power Down Mode is an unique function on Low
Power SDRAMs with very low standby currents. All internal
voltage generators inside the Low Power SDRAMs are
stopped and all memory data will be lost in this mode. To
enter the Deep Power Down Mode all banks must be
precharged and the necessary Precharged Delay t

RP must

occur.

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Basic feature And Function Descriptions

1. CLOCK Suspend

1) Click Suspended During Write (BL=4)

CLK

CMD
CKE

Internal

CLK

DQ(CL2)

DQ(CL3)

Note: CLK to CLK disable/enable=1 clock

WR

D0 D1 D2 D3

D0 D1 D2 D3

2. DQM Operation

1) Write Mask (BL=4)

CLK

CMD

DQM

DQ(CL2)

DQ(CL3)

WR

D0 D1 D3

D0 D1 D3

DQM to Data-in Mask = 0CLK

Masked by CKE

Not Written

Masked by CKE

2) Clock Suspended During Read (BL=4)

RD

2) Read Mask (BL=4)

RD

Masked by CKE

Q0 Q1 Q3

Q0 Q2 Q3

Masked by CKE

Hi-Z

Q0 Q2 Q3

Hi-Z

Q1 Q2 Q3

DQM to Data-out Mask = 2

Q2

Q1

Suspended Dout

2) Read Mask (BL=4)

CLK

RD

CMD
CKE

DQM

DQ(CL2)

DQ(CL3)

* Note :

Q0 Q2 Q4

Hi-Z

Hi-Z

Q1 Q3

1. DQM makes data out Hi-Z after 2 clocks which should masked by CKE “L”.

Hi-Z

Hi-Z Hi-Z

2. DQM masks both data-in and data-out.

PRELIMINARY (July, 2005, Version 1.1) 14

Hi-Z

Q6 Q7 Q8

Q5 Q6 Q7

AMIC Technology, Corp.

A43P26161

3. CAS Interrupt (I)

CLK

CMD

ADD

DQ(CL2)
DQ(CL3)

CLK

CMD

ADD

DQ

1) Read interrupted by Read (BL=4)

RD RD

AB

QA0 QB0 QB1 QB2 QB3

QA0 QB0 QB1 QB2 QB3

t

CCD

Note2

2) Write interrupted by Write (BL =2)

WR WR

t

CCD

Note2

AB

DA0 DB0 DB1

t

CDL

Note3

Note 1

3) Write interrupted by Read (BL =2)

WR RD

t

CCD

AB

DQ(CL2)
DQ(CL3)

DA0 QB0 QB1

DA0

t

CDL

Note3

Note2

QB0 QB1

Note : 1. By “Interrupt”, It is possible to stop burst read/write by external command before the end of burst.

By “

CCD :

2. t

3. t

CDL : Last data in to new column address delay. (= 1CLK).

Interrupt”, to stop burst read/write by

CAS

CAS

to

delay. (=1CLK)

CAS

access; read, write and block write.

CAS

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4. CAS Interrupt (II) : Read Interrupted Write & DQM

(1) CL=2, BL=4

CLK

i) CMD

DQM

DQ

ii) CMD

DQM

DQ

iii) CMD

DQM

DQ

iv) CMD

DQM

DQ

(2) CL=3, BL=4

CLK

i) CMD

DQM

DQ

ii) CMD

RD WR

D0 D1 D2 D3

RD

RD WR

RD WR

RD

WR

Hi-Z

D0 D1 D2 D3

WRRD

Hi-Z

D0 D1 D2 D3

Hi-Z

Note 1

D0 D1 D2 D3

WR

D0 D1 D2 D3Q0

DQM

iii) CMD

iv) CMD

v) CMD

DQ

DQM

DQ

RD WR

DQM

DQ

RD

DQM

DQ

D0 D1 D2 D3

WRRD

D0 D1 D2 D3

WR

Hi-Z

D0 D1 D2 D3

WR

Hi-Z

Note 2

D0 D1 D2Q0

D3

* Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.

2. To prevent bus contention, DQM should be issued which makes a least one gap between data in and data out.

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5. Write Interrupted by Precharge & DQM

CLK

CMD

DQM
DQ

WR PRE

D0 D1 D2 D3

Masked by DQM

Note 2

Note 1

Note : 1. To inhibit invalid write, DQM should be issued.

2. This precharge command and burst write command should be of the same bank, otherwise it is not precharge
interrupt but only another bank precharge of dual banks operation.

6. Precharge

1) Normal Write (BL=4)
CLK

CMD

DQ

2) Read (BL=4)
CLK

CMD

DQ(CL2)

WR PRE
D0 D1 D2 D3

t

RDL

RD PRE

Q0 Q1 Q2 Q3

Q0 Q1 Q2 Q3DQ(CL3)

7. Auto Precharge

1) Normal Write (BL=4)
CLK

CMD

DQ

2) Read (BL=4)
CLK

CMD

DQ(CL2)

* Note : 1. The row active command of the precharge bank can be issued after tRP from this point.

The new read/write command of other active bank can be issued from this point.
At burst read/write with auto precharge,

WR

D0 D1 D2 D3

RD

Q0 Q1 Q2 Q3

Q0 Q1 Q2 Q3DQ(CL3)

Auto Precharge Starts

Auto Precharge Starts

CAS

Note 1

Note 1

interrupt of the same/another bank is illegal.

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8. Burst Stop & Interrupted by Precharge

1) Normal Write (BL=4)
CLK

CMD

WR

DQM
DQ

D0 D1 D2 D3

1) Read Interrupted by Precharge (BL=4)
CLK

CMD

RD

DQ(CL2)

DQ(CL3)

9. MRS

t

RDL

PRE

Q0 Q1

PRE

Note 1

Note 3

1

Q0 Q1

2) Write Burst Stop (BL=8)
CLK

CMD

WR

STOP

DQM
DQ

D0 D1 D2 D3

t

BDL

Note 2

D4 D5

4) Read Burst Stop (BL=4)
CLK

CMD

DQ(CL2)

2

DQ(CL3)

RD

STOP

Q0 Q1

1

Q0 Q1

2

Mode Register Set

CLK

Note 1

Note : 1. t

2. t

CMD

RDL: 1CLK

BDL: 1CLK; Last data in to burst stop delay.

PRE MRS

t

RP

ACT

2CLK

Read or write burst stop command is valid at every burst length.

3. Number of valid output data after row precharge or burst stop: 1,2 for CAS latency = 2, 3 respectively.

4. PRE: All banks precharge if necessary.
MRS can be issued only when all banks are in precharged state.

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10. Clock Suspend Exit & Power Down Exit

1) Clock Suspend (=Active Power Down) Exit
CLK

CKE

Internal

CLK

Note 1

CMD

11. Auto Refresh & Self Refresh

1) Auto Refresh
CLK

CKE

Internal

CLK

CMD

2) Self Refresh

Note 3

Note 4

PRE AR CMD

Note 6

2) Power Down (=Precharge Power Down) Exit
CLK

~

~

CKE

Internal

CLK

CMD

Note 2

Note 5

NOP

t

SS

ACT

~

~

~

~

~

t

SS

RD

~

t

RP

t

RC

CLK

Note 4

CMD

CKE

PRE

t

RP

SR

* Note : 1. Active power down : one or more bank active state.

2. Precharge power down : both bank precharge state.

3. The auto refresh is the same as CBR refresh of conventional DRAM.
No precharge commands are required after Auto Refresh command.
During t

4. Before executing auto/self refresh command, both banks must be idle state.

5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.

6. During self refresh mode, refresh interval and refresh operation are performed internally.
After self refresh entry, self refresh mode is kept while CKE is LOW.
During self refresh mode, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state.
During t
Before/After self refresh mode, burst auto refresh cycle (4K cycles ) is recommended.

RC from auto refresh command, other command can not be accepted.

RC from self refresh exit command, any other command can not be accepted.

~

~

~

~

~

~

CMD

~

~

~

~

t

RC

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12. About Burst Type Control

Basic

MODE

Random

MODE

Sequential counting

Interleave counting

Random column Access

t

CCD = 1 CLK

13. About Burst Length Control

MODE

Special

MODE

Interrupt

MODE

Basic

(Interrupted by Precharge)

1
2

4 At MRS A2,1,0 = “010”
8 At MRS A2,1,0 = “011”.

BRSW

Interrupt

RAS

Interrupt

CAS

At MRS A3=”0”. See the BURST SEQUENCE TABE.(BL=4,8)
BL=1,2,4,8 and full page wrap around.
At MRS A3=” 1”. See the BURST SEQUENCE TABE.(BL=4,8)
BL=4,8 At BL=1,2 Interleave Counting = Sequential Counting
Every cycle Read/Write Command with random column address can realize
Random Column Access.
That is similar to Extended Data Out (EDO) Operation of convention DRAM.

At MRS A2,1,0 = “000”.
At auto precharge, tRAS should not be violated.
At MRS A2,1,0 = “001”.
At auto precharge, tRAS should not be violated.

At MRS A9=”1”.
Read burst = 1,2,4,8, full page/write Burst =1
At auto precharge of write, tRAS should not be violated.
Before the end of burst, Row precharge command of the same bank
Stops read/write burst with Row precharge.
t

RDL= 2 with DQM, valid DQ after burst stop is 1,2 for CL=2,3 respectively

During read/write burst with auto precharge,
Before the end of burst, new read/write stops read/write burst and starts new

read/write burst or block write.
During read/write burst with auto precharge,

interrupt cannot be issued.

RAS

interrupt can not be issued.

CAS

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Power On Sequence for Low Power SDRAM

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

BS0

BS1

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

KEY KEY

Ra

A10/AP

WE

DQM

DQ

High level is necessary

High-Z

t

PR

Precharge

(All Banks)

~

~

~

~

~

~

~

~

~

~

~

~

t

RC

Auto Refresh Auto Refresh

~

~

~

~

~

~

~

~

~

~

~

~

t

RC

Normal

MRS

Extended

MRS

Ra

Row Active
(A-Bank)

: Don't care

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A43P26161

Single Bit Read-Write-Read Cycles (Same Page) @CAS Latency=3, Burst Length=1

t

t

t

CC

RCD

CH

t

CL

High

t

RAS

t

RC

t

SS

t

SH

t

SS

t

SS

*Note 2,3 *Note 2,3 *Note 2,3 *Note 4 *Note 2

t

SH

t

RP

t

CCD

t

SH

Rb

CLOCK

CKE

CS

RAS

CAS

ADDR

BS0, BS1

0 12345678910111213141516171819

*Note 1

t

SH

t

SS

t

SH

Ra Ca Cb Cc

t

SS

*Note 2

BS BS BS BS BS BS

A10/AP

WE

DQM

DQ

*Note 3 *Note 3 *Note 3 *Note 4

Ra Rb

t

SH

t

SS

t

Row Active

t

RA

C

Read

t

SS

t

SA

C

Qa Db Qc

t

SLZ

t

OH

t

SHZ

t

SS

Write

SH

t

SH

Read

Precharge

Row Active

: Don't care

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A43P26161

* Note : 1. All inputs can be don’t care when

2. Bank active & read/write are controlled by BS0, BS1.

BS1 BS0 Active & Read/Write

0 0 Bank A
0 1 Bank B
1 0 Bank C
1 1 Bank D

is high at the CLK high going edge.

CS

3. Enable and disable auto precharge function are controlled by A10/AP in read/write command.

A10/AP BS1 BS0 Operation

0 0 Disable auto precharge, leave bank A active at end of burst.

0

1

0 1 Disable auto precharge, leave bank B active at end of burst.
1 0 Disable auto precharge, leave bank C active at end of burst.
1 1 Disable auto precharge, leave bank D active at end of burst.
0 0 Enable auto precharge, precharge bank A at end of burst.
0 1 Enable auto precharge, precharge bank B at end of burst.
1 0 Enable auto precharge, precharge bank C at end of burst.
1 1 Enable auto precharge, precharge bank D at end of burst.

4. A10/AP and BS0, BS1 control bank precharge when precharge command is asserted.

A10/AP BS1 BS0 Precharge

0 0 0 Bank A
0 0 1 Bank B
0 1 0 Bank C
0 1 1 Bank D
1 X X All Banks

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Read & Write Cycle at Same Bank @Burst Length=4

0 12345678910111213141516171819

CLOCK

CKE

CS

RAS

CAS

ADDR

BS0

BS1

DQM

WE

High

*Note 1

t

RC

t

RCD

*Note 2

Ra Ca0 Rb Cb0

Ra RbA10/AP

t

OH

DQ

(CL = 2)

DQ

(CL = 3)

Row Active

(A-Bank)

t

RAC

*Note 3

*Note 3

t

t

RAC

Read

(A-Bank)

SAC

t

SAC

Qa0

Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3

t

SHZ

*Note 4

*Note 4

t

SHZ

t

OH

Qa0

Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3

Precharge

(A-Bank)

*Note : 1. Minimum row cycle times is required to complete internal DRAM operation.

2. Row precharge can interrupt burst on any cycle. [CAS latency-1] valid output data available after Row
enters precharge. Last valid output will be Hi-Z after t

3. Access time from Row address. t

CC*(tRCD + CAS latency-1) + tSAC

SHZ from the clock.

4. Output will be Hi-Z after the end of burst. (1,2,4 & 8)

Row Active

(A-Bank)

Write

(A-Bank)

t

t

RDL

RDL

Precharge

(A-Bank)

: Don't care

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Page Read & Write Cycle at Same Bank @Burst Length=4

0 12345678910111213141516171819

CLOCK

CKE

CS

RAS

CAS

ADDR

BS0

BS1

DQM

WE

High

t

RCD

Ra Ca Cb Cc

RaA10/AP

*Note1 *Note3

t

CDL

Cd

*Note 2

t

RDL

DQ

(CL=2)

DQ

(CL=3)

Row Active

(A-Bank)

Read

(A-Bank)

Qa0 Qa1 Qb0 Qb1 Dc0 Dc1 Dd0 Dd1

Qa0 Qa1 Qb0

Read

(A-Bank)

Qb2

Qb1

Dc0 Dc1 Dd0 Dd1

Write

(A-Bank)

*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write

command to avoid bus contention.

2. Row precharge will interrupt writing. Last data input, t

RDL before Row precharge, will be written.

3. DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.

Write

(A-Bank)

Precharge

(A-Bank)

: Don't care

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Page Read Cycle at Different Bank @Burst Length = 4

0 12345678910111213141516171819

CLOCK

CKE

CS

RAS

CAS

ADDR

BS1

BS0

A10/AP

WE

DQM

DQ

(CL=2)

*Note 1

RAa RBb

RAa

RBb

CAa

High

CBb

RCc CCcRDd CDd

RCc RDd

QBb2QBb1QAa0 QAa1 QAa2 QBb0 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2

*Note 2

DQ

(CL=3)

Row Active

(A-Bank)

Row Active

(B-Bank)

Read

(A-Bank)

Row Active

(C-Bank)

Read

(B-Bank)

Row Active

Precharge

(A-Bank)

(D-Bank)

Read

(C-Bank)

QBb2QBb1QAa0 QAa1 QAa2 QBb0 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2

Precharge

(B-Bank)

Read

(D-Bank)

Precharge

(C-Bank)

Precharge

(D-Bank)

* Note : 1.

can be don’t care when

CS

RAS

,

CAS

and

are high at the clock high going edge.

WE

2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.

: Don't care

PRELIMINARY (July, 2005, Version 1.1) 26 AMIC Technology, Corp.

A43P26161

Page Write Cycle at Different Bank @Burst Length=4

0 12345678910111213141516171819

CLOCK

CKE

CS

RAS

CAS

ADDR

BS1

BS0

A10/AP

DQ

DQM

WE

High

RAa RBb CBbCAa RCc RDd

RAa

RBb RCc RDd

DBb1DBb0DAa0 DAa1 DAa2 DAa3 DBb2 DBb3 DCc0 DCc1

t

CDL

CCc CDd

DDd0 DDd1

CDd2

*Note 1

t

*Note 2

RDL

Row Active

(A-Bank)

Row Active

(B-Bank)

Write

(A-Bank)

Write

(B-Bank)

Row Active

(C-Bank)

Row Active

(D-Bank)

Write

(C-Bank)

Write

(D-Bank)

* Note:

1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.

2. To interrupt burst write by Row precharge, both the write and precharge banks must be the same.

Precharge

(All Banks)

: Don't care

PRELIMINARY (July, 2005, Version 1.1) 27 AMIC Technology, Corp.

A43P26161

Read & Write Cycle at Different Bank @Burst Length=4

0 12345678910111213141516171819

CLOCK

CKE

CS

RAS

CAS

ADDR

BS1

BS0

A10/AP

DQM

DQ

(CL=2)

WE

RAa CAa

RAa

RDb

High

CDb CBc

RBc

RBCRDb

t

CDL

*Note 1

QAa3QAa2QAa0 QAa1 DDb0 DDb1 QBc0DDb2 DDb3 QBc1 QBc2

DQ

(CL=3)

Row Active

(A-Bank)

* Note : t

Read

(A-Bank)

CDL should be met to complete write.

Row Active

(D-Bank)

Precharge

(A-Bank)

QAa2QAa1QAa0 QAa3 DDb0

Write

(D-Bank)

DDb1 DDb2 DDb3

Row Active

(B-Bank)

Read

(B-Bank)

QBc0 QBc1

: Don't care

PRELIMINARY (July, 2005, Version 1.1) 28 AMIC Technology, Corp.

A43P26161

Read & Write Cycle with Auto Precharge @Burst Length=4

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

BS1

BS0

A10/AP

DQM

WE

RAa RBb

RAa

RBb

CAa

High

CBb

DQ

(CL=2)

DQ

(CL=3)

Row Active

(A-Bank)

Auto Precharge

Row Active

(D-Bank)

Read with

(A-Bank)

Auto Precharge

Start Point

(A-Bank/CL=2)

(In the case of Burst Length=1 & 2, BRSW mode)

*Note : tRCD should be controlled to meet minimum tRAS before internal precharge start.

QAa3QAa2QAa0 QAa1 DDb0 DDb1 DDb2 DDb3

QAa2QAa1QAa0 QAa3 DDb0

Auto Precharge

Start Point

(A-Bank/CL=3)

Auto Precharge

DDb1 DDb2 DDb3

Write with

(D-Bank)

Auto Precharge

Start Point

(D-Bank)

: Don't care

PRELIMINARY (July, 2005, Version 1.1) 29 AMIC Technology, Corp.

A43P26161

Clock Suspension & DQM Operation Cycle @CAS Latency = 2, Burst Length=4

0 12345678910111213141516171819

CLOCK

CKE

CS

RAS

CAS

ADDR

BS1

BS0

A10/AP

DQM

DQ

WE

Ra

Ra

Row Active

Ca

Read

Bank 0

Cb

* Note 1

Qa1 Qb0 Qb1 Dc0

Qa0 Dc2

Clock

Suspension

Qa2

Qa3

t

SHZ

Read

Bank 0

t

SHZ

Read DQM

Cc

Write

Bank 0

Write
DQM

Suspension

Clock

: Don't care

* Note : DQM needed to prevent bus contention.

PRELIMINARY (July, 2005, Version 1.1) 30 AMIC Technology, Corp.

A43P26161

Read Interrupted by Precharge Command & Read Burst Stop Cycle @Burst Length=Full Page

0 12345678910111213141516171819

CLOCK

CKE

CS

RAS

CAS

ADDR

BS1

BS0

A10/AP

DQM

DQ

(CL=2)

WE

RAa

RAa

CAa

QAa0

High

CAb

1

QAa4QAa3QAa1 QAa2 QAb0 QAb1 QAb2 QAb3

QAb4 QAb5

1

DQ

(CL=3)

Row Active

(A-Bank)

Read

(A-Bank)

QAa0

QAa3QAa2QAa1 QAa4 QAb0

Burst Stop

2

Read

(A-Bank)

QAb1 QAb2 QAb3

* Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.

2. About the valid DQ’s after burst stop, it is same as the case of

RAS

interrupt.
Both cases are illustrated above timing diagram. See the label 1,2 on them.
But at burst write, burst stop and

interrupt should be compared carefully.

RAS

Refer the timing diagram of “Full page write burst stop cycle”.

3. Burst stop is valid at every burst length.

Precharge

(A-Bank)

QAb4 QAb5

: Don't care

2

PRELIMINARY (July, 2005, Version 1.1) 31 AMIC Technology, Corp.

A43P26161

Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length = Full Page

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

RAS

CAS

ADDR

BS1

BS0

A10/AP

DQM

CS

WE

DQ

RAa

RAa

High

CAa

t

BDL

DAa0 DAb4 DAb5

DAa4DAa3DAa1 DAa2 DAb0 DAb1 DAb2 DAb3

CAb

* Note 2

t

RDL

Row Active

(A-Bank)

Write

(A-Bank)

Burst Stop

Write

(A-Bank)

Precharge

(A-Bank)

: Don't care

* Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.

2. Data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell.
It is defined by AC parameter of t
DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.

3. Burst stop is valid at every burst length.

RDL(=2CLK).

PRELIMINARY (July, 2005, Version 1.1) 32 AMIC Technology, Corp.

A43P26161

Active/Precharge Power Down Mode @CAS Lantency=2, Burst Length=4

CLOCK

CKE

CS

RAS

CAS

ADDR

BS1

BS0

0 12345678910111213141516171819

t

SS

* Note 1

*Note 3

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

t

SS

* Note 2

t

SS

Ra Ca

~

~

t

SS

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

Exit

Ra

Row

Active

Power-down

Active

Entry

SS” prior to Row active command.

A10/AP

WE

DQM

DQ

Precharge

Power-down

Entry

* Note : 1. All banks should be in idle state prior to entering precharge power down mode.

2. CKE should be set high at least “1CLK + t

3. Cannot violate minimum refresh specification. (64ms)

~

~

~

~

~

~

~

~

~

~

~

~

Precharge

Power-down

~

~

~

~

~

~

~

~

~

~

~

~

~

~

Power-down

Qa0 Qa1

Read Precharge

Active

Exit

Qa2

t

SHZ

: Don't care

PRELIMINARY (July, 2005, Version 1.1) 33 AMIC Technology, Corp.

A43P26161

Self Refresh Entry & Exit Cycle

CLOCK

CKE

CS

RAS

CAS

ADDR

BS0, BS1

A10/AP

0 12345678910111213141516171819

* Note 2

* Note 1

t

SS

* Note 7 * Note 7

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

* Note 3

~

~

~

~

~

~

~

* Note 4

t

SS

* Note 5

t

RC

min.

~

~

~

~

~

~

~

~

~

~

~

~

* Note 6

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

WE

DQM

DQ

Self Refresh Entry

* Note : TO ENTER SELF REFRESH MODE

1.

2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.

3. The device remains in self refresh mode as long as CKE stays “Low”.
(cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE

4. System clock restart and be stable before returning CKE high.

5.

6. Minimum tRC is required after CKE going high to complete self refresh exit.

7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit.

If the system uses burst refresh.

CS, RAS

CS

&

CAS

starts from high.

~

~

~

~

~

~

~

~

and CKE should be low at the same clock cycle.

Hi-ZHi-Z

Self Refresh Exit Auto Refresh

~

~

~

~

~

~

~

~

~

: Don't care

PRELIMINARY (July, 2005, Version 1.1) 34 AMIC Technology, Corp.

A43P26161

Mode Register Set Cycle Auto Refresh Cycle

0 123456 012345678910

CLOCK

CKE

High High

~

~

~

~

*Note 2

CS

t

RC

RAS

CAS

ADDR

WE

DQM

DQ

* All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.

MODE REGISTER SET CYCLE
* Note : 1.

* Note 1

* Note 3

Key

MRS

CS, RAS

mode register.

2. Minimum 2 clock cycles is required before new

Ra

New

Command

,

CAS

&

activation at the same clock cycle with address key will set internal

WE

Hi-ZHi-Z

Auto Refresh New Command

activation.

RAS

3. Please refer to Mode Register Set table.

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

: Don't care

PRELIMINARY (July, 2005, Version 1.1) 35 AMIC Technology, Corp.

A43P26161

Deep Power D own Mode Entry

CLK
CKE

CS

WE

CAS

RAS

ADDR

DQM

DQ

input

DQ

output

t

RP

Precharge Command Deep Power Down Entry

Normal Mode Deep Power Down Mode

High-Z

PRELIMINARY (July, 2005, Version 1.1) 36 AMIC Technology, Corp.

A43P26161

Deep Power Down Mode Exit

CLK

CKE

CS

RAS

CAS

WE

Deep Power

Down Exit

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

200 us t

All Banks

Precharge

RP

Auto

Refresh

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

Auto

Refresh

t

RC

Mode
Register
Set

Extended
Mode
Register Set

New
Command
Accepted
Here

The deep power down mode is exited by asserting CKE high. After the exit, the following sequence is needed to enter a new
command:

1. Maintain NOP input conditions for a minimum of 200

µs

2. Issue precharge commands for all banks of the device

3. Issue eight or more auto-refresh commands

4. Issue a mode register set command to initialize the mode register

5. Issue an extended mode register set command to initialize the extended mode register

PRELIMINARY (July, 2005, Version 1.1) 37 AMIC Technology, Corp.

A43P26161

S

Function Truth Table (Table 1)

Current

State

IDLE

Row

Active

Read

Write

Read with

Auto

Precharge

CS RA

H X X X X X NOP

L H H H X X NOP
L H H L X X ILLEGAL 2
L H L X BS CA, A10/AP ILLEGAL 2
L L H H BS RA Row Active; Latch Row Address
L L H L BS A10/AP NOP 4
L L L H X X Auto Refresh or Self Refresh 5
L L L L OP Code Mode Register Access 5

H X X X X X NOP

L H H H X X NOP
L H H L X X ILLEGAL 2
L H L H BS CA,A10/AP Begin Read; Latch CA; Determine AP
L H L L BS CA,A10/AP Begin Write; Latch CA; Det ermine AP
L L H H BS RA ILLEGAL 2
L L H L BS PA Precharge
L L L X X X ILLEGAL

H X X X X X

L H H H X X
L H H L X X
L H L H BS CA,A10/AP Term burst; Begin Read; Latch CA; Determine AP 3
L H L L BS CA,A10/AP Term burst; Begin Writ e; Latch CA; Determine AP 3
L L H H BS RA ILLEGAL 2
L L H L BS A10/AP Term Burst; Precharge timing for Reads 3
L L L X X X ILLEGAL

H X X X X X

L H H H X X
L H H L X X
L H L H BS CA,A10/AP Term burst; Begin Read; Latch CA; Determine AP 3
L H L L BS CA,A10/AP Term burst; Begin Write; Latch CA; Determine AP 3
L L H H BS RA ILLEGAL 2
L L H L BS A10/AP Term Burst; Precharge timing for Writes 3
L L L X X X ILLEGAL

H X X X X X

L H H H X X
L H H L X X ILLEGAL
L H L H BS CA,A10/AP ILLEGAL 2
L H L L BS CA,A10/AP ILLEGAL 2
L L H X BS RA, PA ILLEGAL
L L L X X X ILLEGAL 2

CAS

BS Address Action Note

WE

NOP(Continue Burst to End
NOP(Continue Burst to End
Term burst

NOP(Continue Burst to End
NOP(Continue Burst to End
Term burst

NOP(Continue Burst to End
NOP(Continue Burst to End

→Row Active

→Row Active

→Row Active)
→Row Active)

→Row Active)
→Row Active)

→Precharge)
→Precharge)

PRELIMINARY (July, 2005, Version 1.1) 38 AMIC Technology, Corp.

A43P26161

Function Truth Table (Table 1, Continued)

Current

State

Write with

Auto

Precharge

Precharge

Row

Activating

Refreshing

Mode

Register

Accessing

Abbreviations
RA = Row Address BS = Bank Address AP = Auto Precharge
NOP = No Operation Command CA = Column Address PA = Precharge All

Note: 1. All entries assume that CKE was active (High) during the preceding clock cycle and the current clock cycle.

2. Illegal to bank in specified state: Function may be legal in the bank indicated by BA, depending on the state of that bank.

3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.

4. NOP to bank precharging or in idle state. May precharge bank indicated by BS (and PA).

5. Illegal if any banks is not idle.

CS

RAS

H X X X X X

L H H H X X
L H H L X X ILLEGAL
L H L H BS CA,A10/AP ILLEGAL 2
L H L L BS CA,A10/AP ILLEGAL 2
L L H X BS RA, PA ILLEGAL
L L L X X X ILLEGAL 2

H X X X X X

L H H H X X
L H H L X X ILLEGAL
L H L X BS CA,A10/AP ILLEGAL 2
L L H H BS RA ILLEGAL 2
L L H L BS A10/AP
L L L X X X ILLEGAL 4

H X X X X X

L H H H X X
L H H L X X ILLEGAL
L H L X BS CA,A10/AP ILLEGAL 2
L L H H BS RA ILLEGAL 2
L L H L BS A10/AP ILLEGAL 2
L L L X X X ILLEGAL 2

H X X X X X

L H H X X X
L H L X X X ILLEGAL
L L H X X X ILLEGAL
L L L X X X ILLEGAL

H X X X X X

L H H H H X
L H H L X X ILLEGAL
L H L X X X ILLEGAL
L L X X X X ILLEGAL

CAS

BS Address Action Note

WE

NOP(Continue Burst to End
NOP(Continue Burst to End

→Idle after tRP

NOP

→Idle after tRP

NOP

→Idle after tRP

NOP

→Row Active after tRCD

NOP

→Row Active after tRCD

NOP

→Idle after tRC

NOP

→Idle after tRC

NOP

→Idle after 2 clocks

NOP

→Idle after 2 clocks

NOP

→Precharge)
→Precharge)

2

PRELIMINARY (July, 2005, Version 1.1) 39 AMIC Technology, Corp.

A43P26161

S

Function Truth Table for CKE (Table 2)

Current

State

Self

Refresh

Both

Bank

Precharge

Power

Down

All

Banks

Idle

Any State

Other than

Listed

Above

Abbreviations : ABI = All Banks Idle

Note: 6. After CKE’s low to high transition to exit self refresh mode, a minimum of t

new command.

7. CKE low to high transition is asynchronous as if it restarts internal clock.
A minimum setup time “tSS + one clock” must be satisfied before any command can be issued other than exit.

8. Power-down and self refresh can be entered only when all the banks are in idle state.

9. Must be a legal command.

CKE

CKE

n-1

H X X X X X X INVALID

L H H X X X X
L H L H H H X
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L L X X X ILLEGAL
L L X X X X X NOP(Maintain Self Refresh)

H X X X X X X INVALID

L H H X X X X
L H L H H H X
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L L X X X ILLEGAL

L L X X X X X NOP(Maintain Power Down Mode)
H H X X X X X Refer to Table 1
H L H X X X X Enter Power Down 8
H L L H H H X Enter Power Down 8
H L L H H L X ILLEGAL
H L L H L X X ILLEGAL
H L L L H H RA Row (& Bank ) Active
H L L L L H X Enter Self Refresh 8
H L L L L L OPCODE MRS

L L X X X X X NOP
H H X X X X X Refer to Operations in Table 1
H L X X X X X Begin Clock Suspend next cycle 9

L H X X X X X Exit Clock Suspend next cycle 9

L L X X X X X Maintain clock Suspend

n

CS RA

CAS

Address Action Note

WE

Exit Self Refresh
Exit Self Refresh

Exit Power Down
Exit Power Down

→ABI after tRC
→ABI after tRC

→ABI
→ABI

RC(min) has to be elapse before issuing a

6
6

7
7

PRELIMINARY (July, 2005, Version 1.1) 40 AMIC Technology, Corp.

A43P26161

Ordering Information

Part No. Min. Cycle Time

(ns)

A43P26161G-75 7.5 133 6 ns 54B CSP

A43P26161G-75F 7.5 133 6 ns 54B Pb-Free CSP

A43P26161G-75U 7.5 133 6 ns 54B CSP

A43P26161G-75UF 7.5 133 6 ns 54B Pb-Free CSP

A43P26161V-75 7.5 133 6 ns 54 TSOP (II)

A43P26161V-75F 7.5 133 6 ns 54 Pb-Free TSOP (II)

A43P26161V-75U 7.5 133 6 ns 54 TSOP (II)

A43P26161V-75UF 7. 5 133 6 ns 54 Pb-Free TSOP (II)

A43P26161G-95 9.5 105 7 ns 54B CSP

A43P26161G-95F 9.5 105 7 ns 54B Pb-Free CSP

A43P26161G-95U 9.5 105 7 ns 54B CSP

A43P26161G-95UF 9.5 105 7 ns 54B Pb-Free CSP

Max. Clock Frequency

(MHz)

Access Time Package

A43P26161V-95 9.5 105 7 ns 54 TSOP (II)

A43P26161V-95F 9.5 105 7 ns 54 Pb-Free TSOP (II)

A43P26161V-95U 9.5 105 7 ns 54 TSOP (II)

A43P26161V-95UF 9. 5 105 7 ns 54 Pb-Free TSOP (II)

Note: -U is for industrial operating temperature range -40ºC to +85ºC.

PRELIMINARY (July, 2005, Version 1.1) 41 AMIC Technology, Corp.

A43P26161

Package Information
54 Ball (8 x 8 mm) Outline Dimensions

Max. 0.20

unit: mm

E1

123456789

D1

A
B
C
D
E
F
G
H
J

E

E/2

Encapsulant

e

D

D/2

A

A1

z

b

Symbol

Dimensions in mm

MIN. NOM. MAX.

A - - 1.00

A1 0.20 0.25 0.30

E 7.95 8.00 8.05

E1 6.40 BSC

D 7.95 8.00 8.05

D1 6.40 BSC

e 0.80 BSC
b 0.30 0.35 0.40
z - - 0.10

PRELIMINARY (July, 2005, Version 1.1) 42 AMIC Technology, Corp.

A43P26161

Package Information

TSOP 54L (Type II) Outline Dimensions unit: inches/mm

Detail "A"

54

28

R1

0.21 REF

0.665 REF

c

-C-

1

S

Seating Plane

R2

E

E1

θ

L

L

1

D

e

b

0.1

D

27

Detail "A"

A2

A

A1

Symbol

A - - 0.047 - - 1.20
A1 0.002 0.004 0.006 0.05 - 0.15
A2 0.037 0.039 0.041 0.95 1.00 1.05

b 0.012 - 0.018 0.30 - 0.45

c 0.005 - 0.008 0.12 - 0.21

D 0.875 BSC 22.22 BSC

S 0.028 REF 0.71 REF

E 0.463 BSC 11.76 BSC
E1 0.400 BSC 10.16 BSC

e 0.031 BSC 0.80 BSC

L 0.016 0.020 0.024 0.40 0.50 0.60
L1 0.031 REF 0.80 REF
R1 0.005 - - 0.12 - ­R2 0.005 - 0.010 0.12 - 0.25

θ

Dimensions in inches Dimensions in mm

Min Nom Max Min Nom Max

0° - 8° 0° - 8°

Notes:

1. The maximum value of dimension D includes end flash.

2. Dimension E does not include resin fins.

3. Dimension S includes end flash.

PRELIMINARY (July, 2005, Version 1.1) 43 AMIC Technology, Corp.