Datasheet A43L0616AV-7, A43L0616AV-5.5 Datasheet (AMIC)

A43L0616A

512K X 16 Bit X 2 Banks Synchronous DRAM

Document Title
512K X 16 Bit X 2 Banks Synchronous DRAM

Revision History

Rev. No. History Issue Date Remark

0.0 Initial issue December 4, 2000 Preliminary

0.1 Add input/output capacitance specification February 13, 2001
Add Cl2 spec for (-5, -5.5, -6)
Modify MRS Set Cycle Waveform error

0.2 Add -U for industrial operating temperature range April 11, 2001

1.0 Final spec. release May 29, 2001 Final
Some AC parameter unit update

(May, 2001, Version 1.0) AMIC Technology, Inc.

A43L0616A

512K X 16 Bit X 2 Banks Synchronous DRAM

Features

n JEDEC standard 3.3V power supply
n LVTTL compatible with multiplexed address

n Dual banks / Pulse RAS
n MRS cycle with address key programs

- CAS Latency (2,3)

- Burst Length (1,2,4,8 & full page)

- Burst Type (Sequential & Interleave)

n All inputs are sampled at the positive going edge of the

system clock

General Description

The A43L0616A is 16,777,216 bits synchronous high data
rate Dynamic RAM organized as 2 X 524,288 words by 16
bits, fabricated with AMIC’s high performance CMOS
technology. Synchronous design allows precise cycle
control with the use of system clock. I/O transactions are

n Industrial operating temperature range: -40ºC to +85ºC

for -U

n Burst Read Single-bit Write operation
n DQM for masking
n Auto & self refresh
n 32ms refresh period (2K cycle)
n 50 Pin TSOP (II)

possible on every clock cycle. Range of operating
frequencies, programmable latencies allows the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.

Pin Configuration

nn TSOP (II)

DQ15

DQ14

VSS

50 49 48 47 46 45 44 43 42 41 3940 38 37 36 35 34 33 32 31 30 29 28 27 26

VSSQ

VDDQ

DQ13

DQ12

VSSQ

DQ9

DQ8

NC/RFU

UDQM

CLK

DQ11

DQ10

VDDQ

CKENCA9A8A7A6A5A4VSS

A43L0616AV

1 2 3 4 5 6 7 8 9 10 1211 13 14 15 16 17 18 19 20 21 22 23 24 25

VDD

DQ0

DQ1

DQ2

DQ3

DQ4

VSSQ

VDDQ

DQ5

VSSQ

DQ7

DQ6

VDDQ

LDQM

WE

CAS

RAS

CS

A10/AP

A0A1A2

BA

A3

VDD

(May, 2001, Version 1.0) 1 AMIC Technology, Inc.

A43L0616A

Block Diagram

CLK

ADD

Address Register

LRAS

Bank Select

Refresh Counter

Row Buffer

LCBR

LRAS

Row Decoder Column Buffer

Data Input Register

512K X 16

512K X 16

Column Decoder

Latency & Burst Length

Sense AMP

I/O Control Output Buffer

LWE

LDQM

DQi

Programming Register

LDQM

LWCBR

L(U)DQM

LRAS LCBR LWE

CLK CKE

LCAS

Timing Register

CS RAS CAS WE

(May, 2001, Version 1.0) 2 AMIC Technology, Inc.

A43L0616A

WE

Pin Descriptions

Symbol Name Description

CLK System Clock Active on the positive going edge to sample all inputs.

CS

CKE Clock Enable

A0~A10/AP Address

BA Bank Select Address

RAS

CAS

L(U)DQM

Chip Select

Row Address Strobe

Column Address
Strobe

Write Enable Enables write operation and Row precharge.

Data Input/Output
Mask

Disables or Enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM

Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one clock + tss prior to new command.
Disable input buffers for power down in standby.
Row / Column addresses are multiplexed on the same pins.
Row address : RA0~RA10, Column address: CA0~CA7
Selects bank to be activated during row address latch time.
Selects band for read/write during column address latch time.

Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with
Enables column access.

Makes data output Hi-Z, t SHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.

CAS

low.

DQ0-15 Data Input/Output Data inputs/outputs are multiplexed on the same pins.

VDD/VSS

VDDQ/VSSQ

NC/RFU No Connection

(May, 2001, Version 1.0) 3 AMIC Technology, Inc.

Power
Supply/Ground

Data Output
Power/Ground

Power Supply: +3.3V±0.3V/Ground

Provide isolated Power/Ground to DQs for improved noise immunity.

A43L0616A

WE

Absolute Maximum Ratings*

Voltage on any pin relative to VSS (Vin, Vout ) . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +4.6V

Voltage on VDD supply relative to VSS (VDD, VDDQ )

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to +4.6V

Storage Temperature (TSTG) . . . . . . . . . . -55°C to +150°C

Soldering Temperature X Time (TSLODER) . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C X 10sec

Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . .1W

Short Circuit Current (Ios) . . . . . . . . . . . . . . . . . . . . 50mA

*Comments

Permanent device damage may occur if “Absolute
Maximum Ratings” are exceeded.
Functional operation should be restricted to recommended
operating condition.
Exposure to higher than recommended voltage for
extended periods of time could affect device reliability.

Capacitance (TA=25°°C, f=1MHz)

Parameter Symbol Condition Min Typ Max Unit

Input Capacitance CI1 A0 to A10, BA 2 4 pF
CI2

Data Input/Output Capacitance CI/O DQ0 to DQ15 2 6 pF

CLK, CKE, CS,
UDQM, LDQM

RAS,CAS

,

2 4 pF

,

DC Electrical Characteristics

Recommend operating conditions (Voltage referenced to VSS = 0V, TA = 0ºC to +70ºC or -40ºC to +85ºC)

Parameter Symbol Min Typ Max Unit Note

Supply Voltage VDD,VDDQ 3.0 3.3 3.6 V
Input High Voltage VIH 2.0 3.0 VDD+0.3 V
Input Low Voltage VIL -0.3 0 0.8 V Note 1
Output High Voltage VOH 2.4 - - V IOH = -2mA
Output Low Voltage VOL - - 0.4 V IOL = 2mA
Input Leakage Current IIL -5 - 5
Output Leakage Current IOL -5 - 5
Output Loading Condition See Figure 1

Note: 1. VIL (min) = -1.5V AC (pulse width ≤ 5ns).

2. Any input 0V ≤ VIN ≤ VDD + 0.3V, all other pins are not under test = 0V

3. Dout is disabled, 0V ≤ Vout ≤ VDD

µA
µA

Note 2
Note 3

(May, 2001, Version 1.0) 4 AMIC Technology, Inc.

A43L0616A

Decoupling Capacitance Guide Line

Recommended decoupling capacitance added to power line at board.

Parameter Symbol Value Unit

Decoupling Capacitance between VDD and VSS CDC1 0.1 + 0.01

Decoupling Capacitance between VDDQ and VSSQ CDC2 0.1 + 0.01

Note: 1. VDD and VDDQ pins are separated each other.

All VDD pins are connected in chip. All VDDQ pins are connected in chip.

2. VSS and VSSQ pins are separated each other
All VSS pins are connected in chip. All VSSQ pins are connected in chip.

DC Electrical Characteristics

(Recommended operating condition unless otherwise noted, TA = 0 to 70°C or -40ºC to +85ºC)

Symbol Parameter Test Conditions

Icc1

Icc2 P

Operating Current
(One Bank Active)

Precharge Standby

Burst Length = 1
tRC ≥ tRC(min), tCC ≥ tCC(min), IOL = 0mA

CKE ≤ VIL(max), tCC = 15ns

Current in power-

Icc2 PS

ICC2N

ICC2NS

ICC3 P

down mode

Precharge Standby
Current in non
power-down mode

Active Standby

CKL ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns

Input signals are changed one time during 30ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞

Input signals are stable.
CKE ≤ VIL(max), tCC = 15ns

Current in power-

ICC3 PS

down mode CKE ≤ VIL(max) tCC = ∞

CAS

Latency

Speed

-5.5

-5

230 210 190 160

-6 -7

1
1

15

4

2
1

µF

µF

Unit Notes

mA 1

mA

mA

mA

ICC3N

Active Standby
current in non
power-down mode

ICC3NS

ICC4

(One Bank Active)

Operating Current
(Burst Mode)

ICC5 Refresh Current
ICC6

Self Refresh
Current

CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable.

IOL = 0mA, Page Burst
All bank Activated, tCCD = tCCD (min)

3 250 230 210 180

2 - - - 180

tRC ≥ tRC (min)
CKE ≤ 0.2V

25

15

250 230 210 180

1 mA

mA

mA 1

mA 2

Note: 1. Measured with outputs open. Addresses are changed only one time during tCC(min).

2. Refresh period is 32ms. Addresses are changed only one time during tCC(min).

(May, 2001, Version 1.0) 5 AMIC Technology, Inc.

A43L0616A

AC Operating Test Conditions

(VDD = 3.3V ±0.3V, TA = 0°C to +70°C or -40ºC to +85ºC)

Parameter Value

AC input levels VIH/VIL = 2.4V/0.4V
Input timing measurement reference level 1.4V
Input rise and all time (See note3) tr/tf = 1ns/1ns
Output timing measurement reference level 1.4V
Output load condition See Fig.2

3.3V

Output

870

VOH(DC) = 2.4V, IOH = -2mA

1200

Ω

VOL(DC) = 0.4V, IOL = 2mA

ZO=50

OUTPUT

Ω

30pF

Ω

VTT =1.4V

50

Ω

30pF

(Fig. 1) DC Output Load Circuit

(Fig. 2) AC Output Load Circuit

AC Characteristics

(AC operating conditions unless otherwise noted)

Symbol Parameter CAS

Latency

3 5 5.5 6 7

tCC CLK cycle time

2 7

CLK to valid

3 - 4.5 - 5 - 5.5 - 6

tSAC

Output delay

2 - 5 - 5.5 - 6 - 7

tOH Output data hold time 2 2 2.5 2.5 ns 2

3 2 2 2.5 2.5

tCH CLK high pulse width

2 2

-5 -5.5 -6 -7

Min Max Min Max Min Max Min Max

1000

-

7

2

1000

-

8

2.5

1000

-

1000 ns 1

8

- ns 3

3

Unit Note

ns 1,2

(May, 2001, Version 1.0) 6 AMIC Technology, Inc.

A43L0616A

AC Characteristics (continued)

(AC operating conditions unless otherwise noted)

Symbol Parameter CAS

Latency

3 2 2 2.5 2.5

tCL CLK low pulse width

2 2

3 2 2 2 2

tSS Input setup time

2 2

3

tSH Input hold time

2

3

tSLZ CLK to output in Low-Z

2

tSHZ

CLK to output

In Hi-Z

3 - 5.5 - 5.5 - 5.5 - 6

2 - 5.5 - 5.5 - 6 - 7

-5 -5.5 -6 -7

Min Max Min Max Min Max Min Max

­2

­2

1 - 1 - 1 - 1 - ns 3

1 - 1 - 1 - 1 - ns 2

-

2.5

-

2.5

*All AC parameters are measured from half to half.

­3

-

2.5

Unit Note

- ns 3

- ns 3

ns

Note : 1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.

(May, 2001, Version 1.0) 7 AMIC Technology, Inc.

A43L0616A

Operating AC Parameter

(AC operating conditions unless otherwise noted)

CAS

Symbol Parameter

tRRD(min) Row active to row active delay 10 11 12 14 ns 1
tRCD(min)

tRP(min) Row precharge time 15 17 18 20 ns 1

tRAS(min) 40 42 42 42 ns 1

tRAS(max)

tRC(min) Row cycle time 55 60.5 60 63 ns 1

tCDL(min) Last data in new col. Address delay 1 CLK 2
tRDL(min) Last data in row precharge 2 2 2 2 CLK 2
tBDL(min) Last data in to burst stop 1 CLK 2
tCCD(min) Col. Address to col. Address delay 1 CLK

Number of valid output data

RAS to

Row active time

CAS

delay

Latency

-5 -5.5 -6 -7

15 17 18 20 ns 1

3 2 CLK 4
2 1 CLK

Version

100

Unit Note

µs

Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

(May, 2001, Version 1.0) 8 AMIC Technology, Inc.

A43L0616A

RAS

WE

Simplified Truth Table

Command CKEn-1 CKEn

Register

Refresh

Bank Active & Row Addr. H X L L H H X V Row Addr. 4

Column Addr.

Column Addr.
Burst Stop H X L H H L X X 6

Precharge

Clock Suspend or
Active Power Down

Precharge Power Down Mode

DQM H X V X 7
No Operation Command H X

Mode Register Set
Auto Refresh H

Self
Refresh

Auto Precharge Disable L 4 Read &
Auto Precharge Enable
Auto Precharge Disable L 4 Write &
Auto Precharge Enable

Bank Selection V L
Both Banks

Entry

Exit L H

Entry

Exit L H X X X X X

Entry H L

Exit L H

H X L L L L X OP CODE

H

H X L H L H X V

H X L H L L X V

H X L L H L X

H L

L

CS

L L L H X X
L H H H 3

H X X X

L H H H

H X X X

L H H H

H X X X

L V V V

H X X X

L H H H

H X X X

CAS

DQM BA A10

/AP

X X

H

H

X H

X

X

X

X X

A9~A0 Notes

Column

Addr.

Column

Addr.

X

X

X

1,2

3
3

3

4,5

4,5

(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)

Note : 1. OP Code : Operand Code

A0~A10/AP,BA : Program keys. (@MRS)

2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 clock cycle of MRS.

3. Auto refresh functions as same as CBR refresh of DRAM.
The automatical precharge without Row precharge command is meant by “Auto”.
Auto/Self refresh can be issued only at both precharge state.

4. BA : Bank select address.

If “Low” at read, write, Row active and precharge, bank A is selected.
If “High” at read, write, Row active and precharge, bank B is selected.
If A10/AP is “High” at Row precharge, BA is ignored and both banks are selected.

5. During burst read or write with auto precharge, new read write command cannot be issued.

Another bank read write command can be issued at every burst length.

6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0),

but makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)

(May, 2001, Version 1.0) 9 AMIC Technology, Inc.

A43L0616A

Mode Register Filed Table to Program Modes

Register Programmed with MRS

Address BA A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Function RFU RFU W.B.L TM CAS Latency BT Burst Length

(Note 1) (Note 2)

Test Mode CAS Latency Burst Type Burst Length

A8 A7 Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT=0 BT=1

0 0 Mode Register Set 0 0 0 Reserved 0 Sequential 0 0 0 1 Reserved
0 1 0 0 1 - 1 Interleave 0 0 1 2 Reserved
1 0 0 1 0 2 0 1 0 4 4
1 1

Write Burst Length

A9 Length

0 Burst 1 1 0 Reserved 1 1 0 Reserved Reserved
1 Single Bit 1 1 1 Reserved

Vendor

Use

Only

0 1 1 3 0 1 1 8 8
1 0 0 Reserved 1 0 0 Reserved Reserved
1 0 1 Reserved 1 0 1 Reserved Reserved

1 1 1 256(Full) Reserved

(Note 3)

Power Up Sequence

1. Apply power and start clock, Attempt to maintain CKE = “H”, DQM = “H” and the other pins are NOP condition at inputs.

2. Maintain stable power, stable clock and NOP input condition for a minimum of 200µs.

3. Issue precharge commands for all banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 may be changed.

The device is now ready for normal operation.
Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.

2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.

3. The full column burst (256bit) is available only at Sequential mode of burst type.

(May, 2001, Version 1.0) 10 AMIC Technology, Inc.

A43L0616A

Burst Sequence (Burst Length = 4)

Initial address
A1 A0

0 0 0 1 2 3 0 1 2 3
0 1 1 2 3 0 1 0 3 2
1 0 2 3 0 1 2 3 0 1
1 1 3 0 1 2 3 2 1 0

Sequential Interleave

Burst Sequence (Burst Length = 8)

Initial address

Sequential Interleave

A2 A1 A0

0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6
0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5
0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4
1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3
1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2
1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1
1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0

(May, 2001, Version 1.0) 11 AMIC Technology, Inc.

A43L0616A

WE

WE

Device Operations

Clock (CLK)

The clock input is used as the reference for all SDRAM
operations. All operations are synchronized to the positive
going edge of the clock. The clock transitions must be
monotonic between VIL and VIH. During operation with
CKE high all inputs are assumed to be in valid state (low or
high) for the duration of set up and hold time around
positive edge of the clock for proper functionality and ICC
specifications.

Clock Enable (CLK)

The clock enable (CKE) gates the clock onto SDRAM. If
CKE goes low synchronously with clock (set-up and hold
time same as other inputs), the internal clock is suspended
form the next clock cycle and the state of output and burst
address is frozen as long as the CKE remains low. All
other inputs are ignored from the next clock cycle after
CKE goes low. When both banks are in the idle state and
CKE goes low synchronously with clock, the SDRAM
enters the power down mode form the next clock cycle.
The SDRAM remains in the power down mode ignoring the
other inputs as long as CKE remains low. The power down
exit is synchronous as the internal clock is suspended.
When CKE goes high at least “tSS + 1 CLOCK” before the
high going edge of the clock, then the SDRAM becomes
active from the same clock edge accepting all the input
commands.

Bank Select (BA)

This SDRAM is organized as two independent banks of
524,288 words X 16 bits memory arrays. The BA inputs is

latched at the time of assertion of
the bank to be used for the operation. When BA is asserted
low, bank A is selected. When BA is asserted high, bank B
is selected. The bank select BA is latched at bank activate,
read, write mode register set and precharge operations.

Address Input (A0 ~ A10/AP)

The 19 address bits required to decode the 524,288 word
locations are multiplexed into 11 address input pins
(A0~A10/AP). The 11 bit row address is latched along with

and BA during bank activate command. The 8 bit

RAS

column address is latched along with
during read or write command.

NOP and Device Deselect

When
performs no operation (NOP). NOP does not initiate any
new operation, but is needed to complete operations which
require more than single clock like bank activate, burst
read, auto refresh, etc. The device deselect is also a NOP

RAS

,

CAS

and

and

RAS

CAS

are high, the SDRAM

to select

CAS

, WE and BA

and is entered by asserting
the command decoder so that

all the address inputs are ignored.

Power-Up

The following sequence is recommended for POWER UP

1. Power must be applied to either CKE and DQM inputs to
pull them high and other pins are NOP condition at the
inputs before or along with VDD (and VDDQ) supply.
The clock signal must also be asserted at the same time.

2. After VDD reaches the desired voltage, a minimum
pause of 200 microseconds is required with inputs in
NOP condition.

3. Both banks must be precharged now.

4. Perform a minimum of 2 Auto refresh cycles to stabilize
the internal circuitry.

5. Perform a MODE REGISTER SET cycle to program the
CAS latency, burst length and burst type as the default
value of mode register is undefined.

At the end of one clock cycle from the mode register set
cycle, the device is ready for operation.
When the above sequence is used for Power-up, all the
out-puts will be in high impedance state. The high
impedance of outputs is not guaranteed in any other
power-up sequence.
cf.) Sequence of 4 & 5 may be changed.

Mode Register Set (MRS)

The mode register stores the data for controlling the
various operation modes of SDRAM. It programs the CAS
latency, addressing mode, burst length, test mode and
various vendor specific options to make SDRAM useful for
variety of different applications. The default value of the
mode register is not defined, therefore the mode register
must be written after power up to operate the SDRAM. The

mode register is written by asserting low on

,

CAS

CKE already high prior to writing the mode register). The
state of address pins A0~A10/AP and BA in the same cycle

as

CS
the mode register. One clock cycle is required to complete
the write in the mode register. The mode register contents
can be changed using the same command and clock cycle
requirements during operation as long as both banks are in
the idle state. The mode register is divided into various
fields depending on functionality. The burst length field
uses A0~A2, burst type uses A3, addressing mode uses
A4~A6, A7~A8, A10/AP and BA are used for vendor
specific options or test mode. And the write burst length is
programmed using A9. A7~A8, A10/AP and BA must be
set to low for normal SDRAM operation.
Refer to table for specific codes for various burst length,
addressing modes and CAS latencies.

(The SDRAM should be in active mode with

,

,

,WE going low is the data written in

CAS

RAS

CS

RAS

high.

,

high disables

CS

and WE, and

CAS

CS

,

RAS

,

(May, 2001, Version 1.0) 12 AMIC Technology, Inc.

A43L0616A

WE

Device Operations (continued)

Bank Activate

The bank activate command is used to select a random row
in an idle bank. By asserting low on

desired row and bank addresses, a row access is initiated.
The read or write operation can occur after a time delay of
tRCD(min) from the time of bank activation. tRCD(min) is an
internal timing parameter of SDRAM, therefore it is
dependent on operating clock frequency. The minimum
number of clock cycles required between bank activate and
read or write command should be calculated by dividing
tRCD(min) with cycle time of the clock and then rounding off
the result to the next higher integer. The SDRAM has two
internal banks on the same chip and shares part of the
internal circuitry to reduce chip area, therefore it restricts the
activation of both banks immediately. Also the noise
generated during sensing of each bank of SDRAM is high
requiring some time for power supplies recover before the
other bank can be sensed reliably. tRRD(min) specifies the
minimum time required between activating different banks.
The number of clock cycles required between different bank
activation must be calculated similar to tRCD specification.
The minimum time required for the bank to be active to
initiate sensing and restoring the complete row of dynamic
cells is determined by tRAS(min) specification before a
precharge command to that active bank can be asserted.
The maximum time any bank can be in the active state is
determined by tRAS(max). The number of cycles for both
tRAS(min) and tRAS(max) can be calculated similar to tRCD
specification.

Burst Read

The burst read command is used to access burst of data on
consecutive clock cycles from an active row in an active
bank. The burst read command is issued by asserting low

on CS and
of the clock. The bank must be active for at least tRCD(min)
before the burst read command is issued. The first output
appears CAS latency number of clock cycles after the issue
of burst read command. The burst length, burst sequence
and latency from the burst read command is determined by
the mode register which is already programmed. The burst
read can be initiated on any column address of the active
row. The address wraps around if the initial address does
not start from a boundary such that number of outputs from
each I/O are equal to the burst length programmed in the
mode register. The output goes into high-impedance at the
end of the burst, unless a new burst read was initiated to
keep the data output gapless. The burst read can be
terminated by issuing another burst read or burst write in
the same bank or the other active bank or a precharge
command to the same bank. The burst stop command is
valid at every page burst length.

with WE being high on the positive edge

CAS

RAS

and

CS

with

Burst Write

The burst write command is similar to burst read command,
and is used to write data into the SDRAM consecutive clock
cycles in adjacent addresses depending on burst length and

burst sequence. By asserting low on CS,
with valid column address, a write burst is initiated. The
data inputs are provided for the initial address in the same
clock cycle as the burst write command. The input buffer is
deselected at the end of the burst length, even though the
internal writing may not have been completed yet. The
writing can not complete to burst length. The burst write can
be terminated by issuing a burst read and DQM for blocking
data inputs or burst write in the same or the other active
bank. The burst stop command is valid only at full page
burst length where the writing continues at the end of burst
and the burst is wrap around. The write burst can also be
terminated by using DQM for blocking data and precharging
the bank “tRDL” after the last data input to be written into the
active row. See DQM OPERATION also.

DQM Operation

The DQM is used to mask input and output operation. It
works similar to OEduring read operation and inhibits

writing during write operation. The read latency is two cycles
from DQM and zero cycle for write, which means DQM
masking occurs two cycles later in the read cycle and
occurs in the same cycle during write cycle. DQM operation
is synchronous with the clock, therefore the masking occurs
for a complete cycle. The DQM signal is important during
burst interrupts of write with read or precharge in the
SDRAM. Due to asynchronous nature of the internal write,
the DQM operation is critical to avoid unwanted or
incomplete writes when the complete burst write is not
required.

Precharge

The precharge operation is performed on an active bank by
asserting low on CS,

BA of the bank to be precharged. The precharge command
can be asserted anytime after tRAS(min) is satisfied from the
bank activate command in the desired bank. “tRP” is defined
as the minimum time required to precharge a bank.
The minimum number of clock cycles required to complete
row precharge is calculated by dividing “tRP” with clock cycle
time and rounding up to the next higher integer. Care should
be taken to make sure that burst write is completed or DQM
is used to inhibit writing before precharge command is
asserted. The maximum time any bank can be active is
specified by tRAS(max). Therefore, each bank has to be
precharged within tRAS(max) from the bank activate
command. At the end of precharge, the bank enters the idle
state and is ready to be activated again.
Entry to Power Down, Auto refresh, Self refresh and Mode
register Set etc, is possible only when both banks are in idle
state.

RAS

,

and A10/AP with valid

CAS

and WE

(May, 2001, Version 1.0) 13 AMIC Technology, Inc.

A43L0616A

WE

WE

WE

Device Operations (continued)

Auto Precharge

The precharge operation can also be performed by using
auto precharge. The SDRAM internally generates the timing
to satisfy tRAS(min) and “tRP” for the programmed burst
length and CAS latency. The auto precharge command is
issued at the same time as burst read or burst write by
asserting high on A10/AP. If burst read or burst write
command is issued with low on A10/AP, the bank is left
active until a new command is asserted. Once auto
precharge command is given, no new commands are
possible to that particular bank until the bank achieves idle
state.

Both Banks Precharge

Both banks can be precharged at the same time by using
Precharge all command. Asserting low on CS,

with high on A10/AP after both banks have satisfied
tRAS(min) requirement, performs precharge on both banks.
At the end of tRP after performing precharge all, both banks
are in idle state.

Auto Refresh

The storage cells of SDRAM need to be refreshed every
32ms to maintain data. An auto refresh cycle accomplishes
refresh of a single row of storage cells. The internal counter
increments automatically on every auto refresh cycle to
refresh all the rows. An auto refresh command is issued by

asserting low on CS,
and

with both banks being in idle state and the device is not in
power down mode (CKE is high in the previous cycle). The
time required to complete the auto refresh

. The auto refresh command can only be asserted

RAS

and

with high on CKE

CAS

RAS

and

operation is specified by “tRC(min)”. The minimum number
of clock cycles required can be calculated by driving “tRC”
with clock cycle time and then rounding up to the next
higher integer. The auto refresh command must be followed
by NOP’s until the auto refresh operation is completed. Both
banks will be in the idle state at the end of auto refresh
operation. The auto refresh is the preferred refresh mode
when the SDRAM is being used for normal data
transactions. The auto refresh cycle can be performed once
in 15.6us or a burst of 2048 auto refresh cycles once in
32ms.

Self Refresh

The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode for
data retention and low power operation of SDRAM. In self
refresh mode, the SDRAM disables the internal clock and all
the input buffers except CKE. The refresh addressing and
timing is internally generated to reduce power consumption.
The self refresh mode is entered from all banks idle state by

asserting low on CS,

. Once the self refresh mode is entered, only CKE state
being low matters, all the other inputs including clock are
ignored to remain in the self refresh.
The self refresh is exited by restarting the external clock and
then asserting high on CKE. This must be followed by
NOP’s for a minimum time of “tRC” before the SDRAM
reaches idle state to begin normal operation. If the system
uses burst auto refresh during normal operation, it is
recommended to used burst 2048 auto refresh cycles
immediately after exiting self refresh.

RAS

,

and CKE with high on

CAS

(May, 2001, Version 1.0) 14 AMIC Technology, Inc.

A43L0616A

Basic feature And Function Descriptions

1. CLOCK Suspend

1) Click Suspended During Write (BL=4)

CLK

CMD

CKE

Internal

CLK

DQ(CL2)

DQ(CL3)

Note: CLK to CLK disable/enable=1 clock

WR

D0 D1 D2 D3

D0 D1 D2 D3

2. DQM Operation

1) Write Mask (BL=4)

CLK

CMD

DQM

DQ(CL2)

DQ(CL3)

WR

D0 D1 D3

D0 D1 D3

DQM to Data-in Mask = 0CLK

Masked by CKE

Not Written

Masked by CKE

2) Clock Suspended During Read (BL=4)

RD

2) Read Mask (BL=4)

RD

Masked by CKE

Q0 Q1 Q3

Q0 Q2 Q3

Masked by CKE

Hi-Z

Q0 Q1 Q3

Hi-Z

Q1 Q2 Q3

DQM to Data-out Mask = 2

Q2

Q1

Suspended Dout

2) Read Mask (BL=4)

CLK

RD

CMD
CKE

DQM

DQ(CL2)

DQ(CL3)

Hi-Z

Q0 Q2 Q4

Hi-Z

Q1 Q3

Hi-Z

Hi-Z Hi-Z

Hi-Z

Q6 Q7 Q8

Q5 Q6 Q7

* Note : 1. DQM makes data out Hi-Z after 2 clocks which should masked by CKE “L”.

2. DQM masks both data-in and data-out.

(May, 2001, Version 1.0) 15 AMIC Technology, Inc.

A43L0616A

3. CAS Interrupt (I)

CLK
CMD
ADD

DQ(CL2)
DQ(CL3)

CLK

CMD

ADD

DQ

1) Read interrupted by Read (BL=4)

RD RD

A B

QA0 QB0 QB1 QB2 QB3

QA0 QB0 QB1 QB2 QB3

tCCD

Note2

2) Write interrupted by Write (BL =2)

WR WR

tCCD

Note2

A B

DA0 DB0 DB1

tCDL

Note3

Note 1

3) Write interrupted by Read (BL =2)

WR RD

tCCD

A B

DQ(CL2)
DQ(CL3)

DA0 QB0 QB1

DA0

tCDL

Note3

Note2

QB0 QB1

Note : 1. By “Interrupt”, It is possible to stop burst read/write by external command before the end of burst.

By “

2. tCCD :

Interrupt”, to stop burst read/write by

CAS

CAS

to

delay. (=1CLK)

CAS

access; read, write and block write.

CAS

3. tCDL : Last data in to new column address delay. (= 1CLK).

(May, 2001, Version 1.0) 16 AMIC Technology, Inc.

A43L0616A

4. CAS Interrupt (II) : Read Interrupted Write & DQM

(1) CL=2, BL=4

CLK

i) CMD

DQM

DQ

ii) CMD

DQM

DQ

iii) CMD

DQM

DQ

iv) CMD

DQM

DQ

(2) CL=3, BL=4

CLK

i) CMD

DQM

DQ

ii) CMD

RD WR

D0 D1 D2 D3

RD

RD WR

RD WR

RD

WR

Hi-Z

D0 D1 D2 D3

WRRD

Hi-Z

D0 D1 D2 D3

Hi-Z

Note 1

D0 D1 D2 D3

WR

D0 D1 D2 D3Q0

DQM

D0 D1 D2 D3

WRRD

D0 D1 D2 D3

WR

Hi-Z

D0 D1 D2 D3

WR

Hi-Z

Note 2

D0 D1 D2Q0

D3

iii) CMD

iv) CMD

v) CMD

DQ

DQM

DQ

RD WR

DQM

DQ

RD

DQM

DQ

* Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.

2. To prevent bus contention, DQM should be issued which makes a least one gap between data in and data out.

(May, 2001, Version 1.0) 17 AMIC Technology, Inc.

A43L0616A

5. Write Interrupted by Precharge & DQM

CLK

CMD

DQM

DQ

WR PRE

D0 D1 D2 D3

Masked by DQM

Note : 1. To inhibit invalid write, DQM should be issued.

2. This precharge command and burst write command should be of the same bank, otherwise it is not precharge

interrupt but only another bank precharge of dual banks operation.

6. Precharge

1) Normal Write (BL=4)
CLK

CMD

DQ

2) Read (BL=4)

CLK

CMD

DQ(CL2)

WR PRE
D0 D1 D2 D3

RD PRE

Q0 Q1 Q2 Q3

Note 2

Note 1

t

RDL

Q0 Q1 Q2 Q3DQ(CL3)

7. Auto Precharge

1) Normal Write (BL=4)
CLK

CMD

DQ

2) Read (BL=4)

CLK

CMD

DQ(CL2)

* Note : 1. The row active command of the precharge bank can be issued after tRP from this point.

The new read/write command of other active bank can be issued from this point.
At burst read/write with auto precharge,

WR
D0 D1 D2 D3

RD

Q0 Q1 Q2 Q3

Q0 Q1 Q2 Q3DQ(CL3)

Auto Precharge Starts

Auto Precharge Starts

CAS

Note 1

Note 1

interrupt of the same/another bank is illegal.

(May, 2001, Version 1.0) 18 AMIC Technology, Inc.

A43L0616A

8. Burst Stop & Precharge Interrupt

9. MRS

1) Write Interrupted by Precharge (BL=4)

CLK

CMD

DQM

DQ

3) Read Interrupted by Precharge (BL=4)

CLK

CMD

DQ(CL2)

DQ(CL3)

WR PRE

D0 D1 D2 D3

tRDL

RD

PRE

Q0 Q1

Note 1

Note 3
1

Q0 Q1

2) Write Burst Stop (BL=8)
CLK

CMD

DQ

4) Read Burst Stop (BL=4)
CLK

CMD

DQ(CL2)

2

WR

D1

D0 D2

RD

STOP

Q0 Q1

STOP

tBDL (note 2)

Q0 Q1DQ(CL3)

Note 3
1

2

Mode Register Set

CLK

Note 4

CMD

PRE MRS

tRP

Note : 1. tRDL : 2CLK, Last Data in to Row Precharge.

2. tBDL : 1CLK, Last Data in to Burst Stop Delay.

3. Number of valid output data after Row precharge or burst stop : 1,2 for CAS latency=2,3 respectively.

4. PRE : Both banks precharge if necessary.
MRS can be issued only at all bank precharge state.

ACT

1CLK

(May, 2001, Version 1.0) 19 AMIC Technology, Inc.

A43L0616A

10. Clock Suspend Exit & Power Down Exit

1) Clock Suspend (=Active Power Down) Exit
CLK

CKE

Internal

Note 1

CLK

CMD

11. Auto Refresh & Self Refresh

1) Auto Refresh
CLK

CKE

Internal

CLK

CMD

2) Self Refresh

Note 3

Note 4

PRE AR CMD

t

Note 6

2) Power Down (=Precharge Power Down) Exit
CLK

tSS

CKE

Internal

tSS

Note 2

CLK

NOP

RD

~

RP

t

RC

CMD

~

~

Note 5

~

~

~

~

~

ACT

CLK

Note 4

CMD

CKE

PRE

t

RP

SR

* Note : 1. Active power down : one or more bank active state.

2. Precharge power down : both bank precharge state.

3. The auto refresh is the same as CBR refresh of conventional DRAM.
No precharge commands are required after Auto Refresh command.
During tRC from auto refresh command, any other command can not be accepted.

4. Before executing auto/self refresh command, both banks must be idle state.

5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.

6. During self refresh mode, refresh interval and refresh operation are performed internally.
After self refresh entry, self refresh mode is kept while CKE is LOW.
During self refresh mode, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state.
During tRC from self refresh exit command, any other command can not be accepted.
Before/After self refresh mode, burst auto refresh cycle (2K cycles ) is recommended.

~

~

~

~

~

~

CMD

~

~

~

~

t

RC

(May, 2001, Version 1.0) 20 AMIC Technology, Inc.

A43L0616A

At BL=4, same applications are possible. As above example, at Interleave
Decrement Counting Mode can be realized. See the BURST SEQUENCE

Using Full Page Mode and Burst Stop Command, Binary Counting Mode can be

Every cycle Read/Write Command with random column address can realize

Before the end of burst, new read/write stops read/write burst and starts new

12. About Burst Type Control

Basic

MODE

Pseudo-

MODE

Random

MODE

Sequential counting

Interleave counting

Pseudo-

Decrement Sequential

Counting

Pseudo-Binary Counting

Random column Access

tCCD = 1 CLK

At MRS A3=”0”. See the BURST SEQUENCE TABE.(BL=4,8)
BL=1,2,4,8 and full page wrap around.
At MRS A3=” 1”. See the BURST SEQUENCE TABE.(BL=4,8)
BL=4,8 At BL=1,2 Interleave Counting = Sequential Counting
At MRS A3 = “1”. (See to Interleave Counting Mode)
Starting Address LSB 3 bits A0-2 should be “000” or “111”.@BL=8.

--if LSB = “000” : Increment Counting.

--if LSB= “111” : Decrement Counting.
For Example, (Assume Addresses except LSB 3 bits are all 0, BL=8)

--@ write, LSB=”000”, Accessed Column in order 0-1-2-3-4-5-6-7

--@ read, LSB=”111”, Accessed Column in order 7-6-5-4-3-2-1-0
Counting mode, by confining starting address to some values, Pseudo­TABLE carefully.

At MRS A3 = “0”. (See to Sequential Counting Mode)
A0-2 = “111”. (See to Full Page Mode)

realized.

--@ Sequential Counting Accessed Column in order 3-4-5-6-7-1-2-3 (BL=8)

--@ Pseudo-Binary Counting,
Accessed Column in order 3-4-5-6-7-8-9-10 (Burst Stop command)
Note. The next column address of 256 is 0

Random Column Access.
That is similar to Extended Data Out (EDO) Operation of convention DRAM.

13. About Burst Length Control

Basic

MODE

Special

MODE

Random

MODE

Interrupt

MODE

(Interrupted by Precharge)

1
2

4 At MRS A2,1,0 = “010”
8 At MRS A2,1,0 = “011”.

Full Page

BRSW

Burst Stop

Interrupt

RAS

Interrupt

CAS

At MRS A2,1,0 = “000”.
At auto precharge, tRAS should not be violated.
At MRS A2,1,0 = “001”.
At auto precharge, tRAS should not be violated.

At MRS A2,1,0 = “111”.
Wrap around mode (Infinite burst length) should be stopped by burst stop,

interrupt or

RAS

At MRS A9=”1”.
Read burst = 1,2,4,8, full page/write Burst =1
At auto precharge of write, tRAS should not be violated.
tBDL=1, Valid DQ after burst stop is 1,2 for CL=2,3 respectively
Using burst stop command, it is possible only at full page burst length.
Before the end of burst, Row precharge command of the same bank
Stops read/write burst with Row precharge.
tRDL=1 with DQM, valid DQ after burst stop is 1,2 for CL=2,3 respectively

During read/write burst with auto precharge,

read/write burst or block write.
During read/write burst with auto precharge,

CAS

interrupt.

interrupt cannot be issued.

RAS

interrupt can not be issued.

CAS

(May, 2001, Version 1.0) 21 AMIC Technology, Inc.

A43L0616A

Power On Sequence & Auto Refresh

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

BA

A10/AP

WE

High level is necessary

t

RP

~

~

t

RC

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

KEY Ra

KEY

KEY

BS

Ra

~

DQM

DQ

(May, 2001, Version 1.0) 22 AMIC Technology, Inc.

High level is necessary

Precharge

(All Banks)

High-Z

Auto Refresh Auto Refresh Mode Regiser Set

~

~

~

~

~

~

~

Row Active
(A-Bank)

: Don't care

A43L0616A

Single Bit Read-Write-Read Cycles (Same Page) @CAS Latency=3, Burst Length=1

tCC

tRCD

tSS

tCH

t

CL

High

tRAS

tRC

tSH

t

SS

t

CCD

t

SH

t

RP

CLOCK

CKE

CS

RAS

CAS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

*Note 1

t

SH

t

SS

ADDR

BA

A10/AP

WE

DQM

DQ

tSH

tSS

Ra Ca Cb Cc

tSS

*Note 2

*Note 2,3 *Note 2,3 *Note 2,3 *Note 4 *Note 2

tSH

BS BS BS BS BS BS

*Note 3 *Note 3 *Note 3 *Note 4

Ra Rb

tSH

t

SS

tSHtSS

Row Active

tRAC

Read

tSAC

tSLZ

Qa Db Qc

tOH

tSS

tSHZ

Write

t

SH

Read

Precharge

Rb

Row Active

: Don't care

(May, 2001, Version 1.0) 23 AMIC Technology, Inc.

A43L0616A

* Note : 1. All inputs can be don’t care when

2. Bank active & read/write are controlled by BA.

BA Active & Read/Write

0 Bank A
1 Bank B

3. Enable and disable auto precharge function are controlled by A10/AP in read/write command.

A10/AP BA Operation

is high at the CLK high going edge.

CS

0

1

0 Disable auto precharge, leave bank A active at end of burst.
1 Disable auto precharge, leave bank B active at end of burst.
0 Enable auto precharge, precharge bank A at end of burst.
1 Enable auto precharge, precharge bank B at end of burst.

4. A10/AP and BA control bank precharge when precharge command is asserted.

A10/AP BA Precharge

0 0 Bank A
0 1 Bank B
1 X Both Bank

(May, 2001, Version 1.0) 24 AMIC Technology, Inc.

A43L0616A

Read & Write Cycle at Same Bank @Burst Length=4

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

RAS

CAS

ADDR

DQM

DQ

(CL = 2)

CS

BA

WE

High

*Note 1

t

RC

t

RCD

*Note 2

Ra Ca0 Rb Cb0

Ra RbA10/AP

t

OH

Qa0

t

RAC

*Note 3

t

SAC

Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3

t

SHZ

*Note 4

t

RDL

t

OH

DQ

(CL = 3)

Row Active

(A-Bank)

*Note 3

t

RAC

Read

(A-Bank)

t

SAC

Qa0

Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3

*Note 4

Row Active

(A-Bank)

Write

(A-Bank)

Precharge

(A-Bank)

t

SHZ

t

RDL

Precharge

(A-Bank)

: Don't care

*Note : 1. Minimum row cycle times is required to complete internal DRAM operation.

2. Row precharge can interrupt burst on any cycle. [CAS latency-1] valid output data available after Row
enters precharge. Last valid output will be Hi-Z after tSHZ from the clock.

3. Access time from Row address. tCC*(tRCD + CAS latency-1) + tSAC

4. Output will be Hi-Z after the end of burst. (1,2,4 & 8)
At Full page bit burst, burst is wrap-around.

(May, 2001, Version 1.0) 25 AMIC Technology, Inc.

A43L0616A

Page Read & Write Cycle at Same Bank @Burst Length=4

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

DQM

DQ

(CL=2)

BA

WE

High

t

RCD

Ra Ca0 Cb0 Cc0

RaA10/AP

*Note 2

*Note1 *Note3

Qa0 Qa1 Qb0 Qb1 Dc0 Dc1 Dd0 Dd1

*Note 2

Cd0

t

t

CDL

RDL

DQ

(CL=3)

Row Active

(A-Bank)

Read

(A-Bank)

Read

(A-Bank)

Qa0 Qa1 Qb0

Dc0 Dc1 Dd0 Dd1

Write

(A-Bank)

Write

(A-Bank)

Precharge

(A-Bank)

: Don't care

*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write

command to avoid bus contention.

2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.

3. DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.

(May, 2001, Version 1.0) 26 AMIC Technology, Inc.

A43L0616A

RAS

WE

Page Read Cycle at Different Bank @Burst Length = 4

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

BA

A10/AP

WE

DQM

DQ

(CL=2)

*Note 1

RAa CAa

RAa RBb

High

RBb CAc CBd CAe

CBb

QBb1QBb0QAa0 QAa1 QAa2 QAa3 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1

*Note 2

DQ

(CL=3)

Row Active

(A-Bank)

Read

(A-Bank)

Row Active

(B-Bank)

Read

(B-Bank)

QBb1QBb0QAa0 QAa1 QAa2 QAa3 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1

Read

(A-Bank)

Read

(B-Bank)

Read

(A-Bank)

Precharge

(A-Bank)

: Don't care

* Note : 1. CS can be don’t care when

,

CAS

and

are high at the clock high going edge.

2. To interrupt a burst read by row precharge, both the read ad the precharge banks must be the same.

(May, 2001, Version 1.0) 27 AMIC Technology, Inc.

A43L0616A

Page Write Cycle at Different Bank @Burst Length=4

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

A10/AP

DQ

DQM

BA

WE

RAa CAa

RAa RBb

RBb CAc

High

*Note 2

CBb

DBb1DBb0DAa0 DAa1 DAa2 DAa3 DBb2 DBb3 DAc0 DAc1

t

CDL

CBd

DBd0 DBd1

*Note 1

t

RDL

Write

(B-Bank)

Write

(A-Bank)

Write

(B-Bank)

Precharge

(Both Banks)

: Don't care

Row Active with

(A-Bank)

Write

(A-Bank)

Row Active

(B-Bank)

* Note:

1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.

2. To interrupt burst write by Row precharge, both the write and precharge banks must be the same.

(May, 2001, Version 1.0) 28 AMIC Technology, Inc.

A43L0616A

Read & Write Cycle at Different Bank @Burst Length=4

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

A10/AP

WE

DQM

DQ

(CL=2)

BA

RAa CAa

RAa

RBb

High

CBb CAc

RAc

RAcRBb

tCDL

*Note 1

QAa3QAa2QAa0 QAa1 DBb0 DBb1 QAc0DBb2 DBb3 QAc1 QAc2

DQ

(CL=3)

Row Active

(A-Bank)

Read

(A-Bank)

Row Active

(B-Bank)

Precharge

(A-Bank)

QAa2QAa1QAa0 QAa3 DBb0

Write

(B-Bank)

DBb1 DBb2 DBb3

Row Active

(A-Bank)

QAc0 QAc1

Read

(A-Bank)

: Don't care

* Note : tCDL should be met to complete write.

(May, 2001, Version 1.0) 29 AMIC Technology, Inc.

A43L0616A

Read & Write Cycle with Auto Precharge I @Burst Length=4

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

BA

A10/AP

WE

DQM

DQ

(CL=2)

RAa RBb

RAa

RBb

CAa

High

CBb

QAa3QAa2QAa0 QAa1 DBb0 DBb1 DBb2 DBb3

DQ

(CL=3)

Row Active

(A-Bank)

Auto Precharge

Row Active

(B-Bank)

Read with

(A-Bank)

Auto Precharge

Start Point

QAa2QAa1QAa0 QAa3 DBb0

(A-Bank)

DBb1 DBb2 DBb3

Write with

Auto Precharge

(B-Bank)

Auto Precharge

Start Point

(B-Bank)

: Don't care

*Note : tRCD should be controlled to meet minimum tRAS before internal precharge start.

(In the case of Burst Length=1 & 2, BRSW mode)

(May, 2001, Version 1.0) 30 AMIC Technology, Inc.

A43L0616A

Read & Write Cycle with Auto Precharge II @Burst Length=4

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

A10/AP

WE

DQM

DQ

(CL=2)

BA

Ra Rb

Ra

Rb

Ca

Cb

High

Ra Ca

Ra

Qb1Qb0Qa0 Qa1 Qb2 Qb3 Da0 Da1

DQ

(CL=3)

Row Active

(A-Bank)

Row Active

(B-Bank)

Read with

Auto Pre

Charge

(A-Bank)

Read without

Auto Precharge

(B-Bank)

Auto Precharge

Strart Point

(A-Bank) *Note 1

Qb0Qa1Qa0 Qb1 Qb2

Precharge

Qb3 Da0 Da1

Row Active

(B-Bank)

(A-Bank)

Write with

Auto Precharge

(A-Bank)

: Don't care

* Note : When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation.

- if read(Write) command without auto precharge is issued at B-Bank before A Bank auto precharge starts, A Bank
auto precharge will start at B Bank read command input point.

- Any command can not be issued at A Bank during tRP after A Bank auto precharge starts.

(May, 2001, Version 1.0) 31 AMIC Technology, Inc.

A43L0616A

Read & Write Cycle with Auto Precharge III @Burst Length=4

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

BA

A10/AP

WE

DQM

DQ

(CL=2)

Ra

Ra

Ca

High

Rb Cb

Rb

Qa3Qa2Qa0 Qa1 Qb0 Qb1 Qb2 Qb3

DQ

(CL=3)

Row Active

(A-Bank)

Read with

Auto Preharge

(A-Bank)

* Note 1

Auto Precharge

Start Point

(A-Bank)

Row Active

(B-Bank)

Qa2Qa1Qa0 Qa3 Qb0

Read with

Auto Precharge

(B-Bank)

Qb1 Db2 Db3

Auto Precharge

Start Point

(B-Bank)

: Don't care

* Note : Any command to A-bank is not allowed in this period.

tRP is determined from at auto precharge start point

(May, 2001, Version 1.0) 32 AMIC Technology, Inc.

A43L0616A

Read Interrupted by Precharge Command & Read Burst Stop Cycle (@Burst Length = Full Page)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

BA

A10/AP

WE

DQM

DQ

(CL=2)

RAa

RAa

High

CAa

* Note 1 * Note 1

QAa0 QAb4 QAb5

CAb

1* Note 2

QAa4QAa3QAa1 QAa2 QAb0 QAb1 QAb2 QAb3

1

DQ

(CL=3)

Row Active

(A-Bank)

Read

(A-Bank)

QAa0

2

QAa3QAa2QAa1 QAa4 QAb0

Burst Stop

Read

(A-Bank)

QAb1 QAb2 QAb3

Precharge

(A-Bank)

QAb4 QAb5

: Don't care

2

* Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.

2. About the valid DQ’s after burst stop, it is same as the case of

RAS

interrupt.
Both cases are illustrated above timing diagram. See the label 1,2 on them.
But at burst write, burst stop and

interrupt should be compared carefully.

RAS

Refer the timing diagram of “Full page write burst stop cycle”.

3. Burst stop is valid at every burst length.

(May, 2001, Version 1.0) 33 AMIC Technology, Inc.

A43L0616A

Write Interrupted by Precharge Command & Write Burst Stop Cycle (@ Burst Length = Full Page)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

BA

A10/AP

DQM

DQ

WE

RAa

RAa

High

CAa

* Note 1 * Note 1

t

BDL

* Note 2

DAa0 DAb4 DAb5

DAa4DAa3DAa1 DAa2 DAb0 DAb1 DAb2 DAb3

CAb

* Note 3

t

RDL

Row Active

(A-Bank)

Write

(A-Bank)

Burst Stop

Write

(A-Bank)

Precharge

(A-Bank)

: Don't care

* Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.

2. Data-in at the cycle of burst stop command cannot be written into corresponding memory cell.
It is defined by AC parameter of tBDL(=1CLK).

3. Data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell.
It is defined by AC parameter of tRDL(=2CLK).
DQM at write interrupted by precharge command is needed to ensure tRDL of 2CLK.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.

4. Burst stop is valid only at every burst length.

(May, 2001, Version 1.0) 34 AMIC Technology, Inc.

A43L0616A

Burst Read Single Bit Write Cycle @Burst Length=2, BRSW

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

RAS

CAS

ADDR

A10/AP

(CL=2)

(CL=3)

CS

BA

WE

DQM

DQ

DQ

RAa

RAa

High

* Note 2

CAa

RBb CAb

RBb

DAa0

DAa0 QAd1

QAb1QAb0 DBc0 QAd0

RAc

CBc CAd

RAc

QAb1QAb0 DBc0

QAd1

QAd0

Row Active

(A-Bank)

Row Active

(B-Bank)

Row Active

(A-Bank)

Read

(A-Bank)

Precharge

(A-Bank)

Write

(A-Bank)

Read with

Auto Precharge

(A-Bank)

Write with

Auto Precharge

(B-Bank)

: Don't care

* Note : 1. BRSW mode is enabled by setting A9 “High” at MRS (Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to “1” regardless of programed burst length.

2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated.
Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command,

The next cycle starts the precharge.

(May, 2001, Version 1.0) 35 AMIC Technology, Inc.

A43L0616A

Clock Suspension & DQM Operation Cycle @CAS Latency = 2, Burst Length=4

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

BA

A10/AP

WE

DQM

DQ

Ra

Ra

Row Active

Ca

Read

Cb

* Note 1

Qa1 Qb0 Qb1 Dc0

Qa0 Dc2

Clock

Suspension

Qa2

t

SHZ

Qa3

Read

t

SHZ

Read DQM

Cc

Write
DQM

Write

* Note : DQM needed to prevent bus contention.

Clock

Suspension

: Don't care

(May, 2001, Version 1.0) 36 AMIC Technology, Inc.

A43L0616A

Active/Precharge Power Down Mode @CAS Lantency=2, Burst Length=4

CLOCK

CKE

CS

RAS

CAS

ADDR

BA

A10/AP

WE

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

t

SS

* Note 1

*Note 3

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

t

SS

* Note 2

t

SS

Ra Ca

Ra

~

~

t

SS

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

DQM

DQ Qa0 Qa1

Precharge

Power-down

Entry

* Note : 1. All banks should be in idle state prior to entering precharge power down mode.

2. CKE should be set high at least “1CLK + tSS” prior to Row active command.

3. Cannot violate minimum refresh specification. (32ms)

~

~

~

~

Precharge

Power-down

Exit

Row Active

Active

Power-down

Entry

~

~

~

~

~

Power-down

Read Precharge

Active

Exit

Qa2

: Don't care

(May, 2001, Version 1.0) 37 AMIC Technology, Inc.

A43L0616A

RAS

Self Refresh Entry & Exit Cycle

CLOCK

CKE

CS

RAS

CAS

ADDR

A10/AP

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

* Note 2

* Note 1

t

SS

* Note 7 * Note 7

BA

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

* Note 3

~

~

~

~

~

~

~

~

~

~

~

~

~

~

* Note 4

t

* Note 5

~

~

t

RC min.

SS

* Note 6

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

WE

DQM

DQ

Self Refresh Entry

* Note : TO ENTER SELF REFRESH MODE

1.

2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.

3. The device remains in self refresh mode as long as CKE stays “Low”.
(cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE

4. System clock restart and be stable before returning CKE high.

5.

6. Minimum tRC is required after CKE going high to complete self refresh exit.

7. 2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit.

If the system uses burst refresh.

,

CS

CS

&

CAS

starts from high.

~

~

~

~

~

~

~

~

with CKE should be low at the same clock cycle.

Hi-ZHi-Z

Self Refresh Exit Auto Refresh

~

~

~

~

~

~

~

~

~

: Don't care

(May, 2001, Version 1.0) 38 AMIC Technology, Inc.

A43L0616A

RAS

RAS

Mode Register Set Cycle Auto Refresh Cycle

0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8 9 10

CLOCK

CKE

High High

~

~

~

~

*Note 2

CS

t

RC

RAS

CAS

ADDR

WE

DQM

DQ

* Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.

MODE REGISTER SET CYCLE
* Note : 1.

* Note 1

* Note 3

Key

MRS

,

CS

mode register.

2. Minimum 2 clock cycles should be met before new

Ra

New

Command

,

CAS

& WE activation at the same clock cycle with address key will set internal

Hi-ZHi-Z

Auto Refresh New Command

activation.

3. Please refer to Mode Register Set table.

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

: Don't care

(May, 2001, Version 1.0) 39 AMIC Technology, Inc.

A43L0616A

RAS

WE

Function Truth Table (Table 1)

Current

State

IDLE

Row

Active

Read

Write

Read with

Auto

Precharge

CS

H X X X X X NOP
L H H H X X NOP
L H H L X X ILLEGAL 2
L H L X BA CA, A10/AP ILLEGAL 2
L L H H BA RA Row Active; Latch Row Address
L L H L BA PA NOP 4
L L L H X X Auto Refresh or Self Refresh 5
L L L L OP Code Mode Register Access 5
H X X X X X NOP
L H H H X X NOP
L H H L X X ILLEGAL 2
L H L H BA CA,A10/AP Begin Read; Latch CA; Determine AP
L H L L BA CA,A10/AP Begin Write; Latch CA; Determine AP
L L H H BA RA ILLEGAL 2
L L H L BA PA Precharge
L L L X X X ILLEGAL
H X X X X X
L H H H X X
L H H L X X
L H L H BA CA,A10/AP Term burst; Begin Read; Latch CA; Determine AP 3
L H L L BA CA,AP Term burst; Begin Write; Latch CA; Determine AP 3
L L H H BA RA ILLEGAL 2
L L H L BA PA Term Burst; Precharge timing for Reads 3
L L L X X X ILLEGAL
H X X X X X
L H H H X X
L H H L X X ILLEGAL
L H L H BA CA,A10/AP Term burst; Begin Read; Latch CA; Determine AP 3
L H L L BA CA,A10/AP Term burst; Begin Read; Latch CA; Determine AP 3
L L H H BA RA ILLEGAL 2
L L H L BA A10/AP Term Burst; Precharge timing for Writes 3
L L L X X X ILLEGAL
H X X X X X
L H H H X X
L H H L X X ILLEGAL
L H L H BA CA,A10/AP ILLEGAL 2
L H L L BA CA,A10/AP ILLEGAL 2
L L H X BA RA, PA ILLEGAL
L L L X X X ILLEGAL 2

CAS

BA Address Action Note

NOP(Continue Burst to End →Row Active)
NOP(Continue Burst to End →Row Active)
Term burst →Row Active

NOP(Continue Burst to End→Row Active)
NOP(Continue Burst to End→Row Active)

NOP(Continue Burst to End→Precharge)
NOP(Continue Burst to End→Precharge)

(May, 2001, Version 1.0) 40 AMIC Technology, Inc.

A43L0616A

RAS

WE

Function Truth Table (Table 1, Continued)

Current

State

Write with

Auto

Precharge

Precharge

Row

Activating

Refreshing

Abbreviations
RA = Row Address BA = Bank Address AP = Auto Precharge
NOP = No Operation Command CA = Column Address PA = Precharge All

Note: 1. All entries assume that CKE was active (High) during the preceding clock cycle and the current clock cycle.

2. Illegal to bank in specified state : Function may be legal in the bank indicated by BA, depending on the state of
that bank.

3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.

4. NOP to bank precharging or in idle state. May precharge bank indicated by BA (and PA).

5. Illegal if any banks is not idle.

CS

H X X X X X
L H H H X X
L H H L X X ILLEGAL
L H L H BA CA,A10/AP ILLEGAL 2
L H L L BA CA,A10/AP ILLEGAL 2
L L H X BA RA, PA ILLEGAL
L L L X X X ILLEGAL 2
H X X X X X
L H H H X X
L H H L X X ILLEGAL
L H L X BA CA,A10/AP ILLEGAL 2
L L H H BA RA ILLEGAL 2
L L H L BA PA
L L L X X X ILLEGAL 4
H X X X X X
L H H H X X
L H H L X X ILLEGAL
L H L X BA CA,A10/AP ILLEGAL 2
L L H H BA RA ILLEGAL 2
L L H L BA PA ILLEGAL 2
L L L X X X ILLEGAL 2
H X X X X X
L H H X X X
L H L X X X ILLEGAL
L L H X X X ILLEGAL
L L L X X X ILLEGAL

CAS

BA Address Action Note

NOP(Continue Burst to End→Precharge)
NOP(Continue Burst to End→Precharge)

NOP→Idle after tRP
NOP→Idle after tRP

NOP→Idle after tRP

NOP→Row Active after tRCD
NOP→Row Active after tRCD

NOP→Idle after tRC
NOP→Idle after tRC

2

(May, 2001, Version 1.0) 41 AMIC Technology, Inc.

A43L0616A

RAS

WE

Function Truth Table for CKE (Table 2)

Current

State

Self

Refresh

Both

Bank

Precharge

Power

Down

All

Banks

Idle

Any State

Other than

Listed

Above

Abbreviations : ABI = All Banks Idle

Note: 6. After CKE’s low to high transition to exit self refresh mode. And a time of tRC(min) has to be elapse after CKE’s low

to high transition to issue a new command.

7. CKE low to high transition is asynchronous as if restarts internal clock.

A minimum setup time “tSS + one clock” must be satisfied before any command other than exit.

8. Power-down and self refresh can be entered only from the all banks idle state.

9. Must be a legal command.

CKE

CKE

n-1

n

H X X X X X X INVALID

L H H X X X X
L H L H H H X
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L L X X X ILLEGAL
L L X X X X X NOP(Maintain Self Refresh)

H X X X X X X INVALID

L H H X X X X
L H L H H H X
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L L X X X ILLEGAL

L L X X X X X NOP(Maintain Power Down Mode)
H H X X X X X Refer to Table 1
H L H X X X X Enter Power Down 8
H L L H H H X Enter Power Down 8
H L L H H L X ILLEGAL
H L L H L X X ILLEGAL
H L L L H X X ILLEGAL
H L L L L H X Enter Self Refresh 8
H L L L L L X ILLEGAL

L L X X X X X NOP
H H X X X X X Refer to Operations in Table 1
H L X X X X X Begin Clock Suspend next cycle 9

L H X X X X X Exit Clock Suspend next cycle 9

L L X X X X X Maintain clock Suspend

CS

CAS

Address

Action Note

Exit Self Refresh→ABI after tRC
Exit Self Refresh→ABI after tRC

Exit Power Down→ABI
Exit Power Down→ABI

6
6

7
7

(May, 2001, Version 1.0) 42 AMIC Technology, Inc.

A43L0616A

Ordering Information

Part No. Cycle Time (ns) Clock Frequency (MHz) Access Time Package

200 @ CL = 3 4.5 ns @ CL = 3

A43L0616AV-5 5

143 @ CL = 2 5.0 ns @ CL = 2

183 @ CL = 3 5.0 ns @ CL = 3

A43L0616AV-5.5 5.5

143 @ CL = 2 5.5 ns @ CL = 2

166 @ CL = 3 5.5 ns @ CL = 3

A43L0616AV-6 6

125 @ CL = 2 6.0 ns @ CL = 2

143 @ CL = 3 6.0 ns @ CL = 3

A43L0616AV-7 7

125 @ CL = 2 7.0 ns @ CL = 2

143 @ CL = 3 6.0 ns @ CL = 3

A43L0616AV-7U 7

125 @ CL = 2 7.0 ns @ CL = 2

Note: -U is for industrial operating temperature range

50 TSOP (II)

50 TSOP (II)

50 TSOP (II)

50 TSOP (II)

50 TSOP (II)

(May, 2001, Version 1.0) 43 AMIC Technology, Inc.

A43L0616A

Package Information
TSOP 50L (Type II) Outline Dimensions unit: inches/mm

Detail "A"

50

1

D

26

E

E1

25

A2

A

R0.15 REF.

R0.15 REF.

0.25

θ

L

L 1

Detail "A"

c

b

Seating Plane

e

0.1

D

A1

Symbol

A - - 0.047 - - 1.20
A1 0.002 - - 0.05 - ­A2 0.037 0.040 0.041 0.95 1.016 1.05

b 0.012 - 0.018 0.30 - 0.45

c 0.005 - 0.008 0.12 - 0.21

D 0.821 0.825 0.829 20.855 20.955 21.055
E 0.455 0.463 0.471 11.56 11.76 11.96

E1 0.396 0.400 0.404 10.06 10.16 10.26

e - 0.031 - - 0.800 -

L 0.016 0.020 0.024 0.40 0.50 0.60

θ

Dimensions in inches Dimensions in mm

Min Nom Max Min Nom Max

0° - 5° 0° - 5°

Notes:

1. The maximum value of dimension D includes end flash.

2. Dimension E does not include resin fins.

3. Dimension S includes end flash.

(May, 2001, Version 1.0) 44 AMIC Technology, Inc.