Page 1
A42U0616 Series
Preliminary 1M X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Document Title
1M X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Revision History
Rev. No. History Issue Date Remark
0.0 Initial issue June 13, 2001 Preliminary
Preliminary (June, 2001, Version 0.0) AMIC Technology, Inc.
Page 2
A42U0616 Series
Preliminary 1M X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Features
n Organization: 1,048,576 words X 16 bits
n Part Identification
- A42U0616 (1K Ref.)
n Single 2.5V power supply/built -in VBB generator
n Low power consumption
- Operating: 120mA (-50 max)
- Standby: 1mA (TTL), 0.2mA (CMOS),
250µA (Self -refresh current)
n High speed
- 50/60/80 ns RAS access time
- 25/30/40 ns column address access time
General Description
The A42U0616 is a new generation randomly accessed
memory for graphics, organized in a 1,048,576 -word by
16-bit configuration. This product can execute Write and
Read operation via
CAS
pin.
The A42U0616 offers an accelerated Fast Page Mode
cycle with a feature called Extended Data Out (EDO).
Pin Configuration
- 13/15/20 ns CAS access time
- 20/25/35 ns EDO Page Mode Cycle Time
n Separate
CAS
(
UCAS,LCAS
) for byte selection
n Fast Page Mode with Extended Data Out
n Read-modify-write, RAS -only, CAS -before- RAS ,
Hidden refresh capability
n TTL-compatible, three-state I/O
n JEDEC standard packages
- 400mil, 42-pin SOJ
- 400mil, 50/44 TSOP type II package
This allow random access of up to 1024(1K Ref.) words
within a row at a 50/40/28 MHz EDO cycle, making the
A42U0616 ideally suited for graphics, digital signal
processing and high performance computing systems.
nn SOJ nn TSOP
Pin Descriptions
VCC
1
42 VCC
2
3
4
5
6
7
A42U0616S
8
9
10
11
12
13
14
15
16
17
18
19
20
21 22 VSSVCC
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
I/O
0
I/O
1
I/O
2
I/O
3
VCC
I/O
4
I/O
5
I/O
6
I/O
7
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3 A4
VSS
I/O
I/O
I/O
I/O
VSS
I/O
I/O
I/O
I/O
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
15
14
13
12
11
10
9
8
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
WE
RAS
VCC
NC
NC
NC
NC
A0
A1
A2
A3
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
A42U0616V
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22 23
VSS
44
15
43
I/O
I/O
14
42
I/O
13
41
40
I/O
12
VSS
39
I/O
11
38
37
I/O
10
I/O
9
36
I/O
8
35
NC
34NC
33
NC
32
LCAS
31
UCAS
30
OE
29
A9
A8
28
A7
27
A6
26
A5
25
A4
24
VSS
Symbol Description
A0 - A9 Address Inputs (1K product)
I/O0 - I/O15 Data Input/Output
RAS
LCAS
Row Address Strobe
Column Address Strobe for Lower Byte
(I/O0 – I/O7)
Column Address Strobe for Upper Byte
UCAS
(I/O8 – I/O15)
WE
OE
Write Enable
Output Enable
VCC 2.5V Power Supply
VSS Ground
NC No Connection
PRELIMINARY (June, 2001, Version 0.0) 1 AMIC Technology, Inc.
Page 3
A42U0616 Series
Selection Guide
Symbol Description -50 -60 -80 Unit
tRAC
tAA Maximum Column Address Access Time 25 30 40 ns
tCAC
tOEA
tRC Minimum Read or Write Cycle Time 84 104 134 ns
tPC Minimum EDO Cycle Time 20 25 35 ns
Maximum RAS Access Time
Maximum CAS Access Time
Maximum Output Enable (OE) Access Time
50 60 80 ns
13 15 20 ns
13 15 20 ns
Functional Description
The A42U0616 reads and writes data by multiplexing an
20-bit address into a 10-bit row and 10-bit column
address.
address and the column address, respectively.
The A42U0616 has two
I/O7, and
function in an identical manner to
generate an internal
timing are determined by the first
) to transition low and by the last to transition high.
LCAS
Byte Read and Byte Write are controlled by using
and
UCAS
A Read cycle is performed by holding the WE signal high
during RAS/
holding the WE signal low during RAS/
the input data is latched by the falling edge of WE or
, whichever occurs later. The data inputs and outputs
CAS
are routed through 16 common I/O pins, with RAS,
WE and OE controlling the in direction.
EDO Page Mode operation all 1024(1K) columns within a
selected row to be randomly accessed at a high data rate.
A EDO Page Mode cycle is initiated with a row address
latched by RAS followed by a column address latched by
. While holding RAS low,
CAS
strobe changing column addresses, thus achieving
shorter cycle times.
The A42U0616 offers an accelerated Fast Page Mode
cycle through a feature called Extended Data Out, which
keeps the output drivers on during the
time (tcp). Since data can be output after
and
RAS
controls I/O8 - I/O15,
UCAS
separately.
operation. A Write cycle is executed by
CAS
are used to strobe the row
CAS
CAS
signal. The
CAS
inputs:
CAS
CAS
controls I/O0-
LCAS
and
UCAS
in that either will
function and
CAS
(
CAS
CAS
can be toggled to
CAS
CAS
LCAS
UCAS
or
LCAS
operation;
CAS
precharge
goes high,
the user is not required to wait for valid data to appear
before starting the next access cycle. Data-out will remain
valid as long as RAS and OE are low, and WE is high;
this is the only characteristic which differentiates Extended
Data Out operation from a standard Read or Fast Page
Read.
A memory cycle is terminated by returning both RAS and
high. Memory cell data will retain its correct state by
CAS
maintaining power and accessing all 1024(1K)
combinations of the 10-bit row addresses, regardless of
sequence, at least once every 16ms through any RAS
cycle (Read, Write) or RAS Refresh cycle (RAS -only,
CBR, or Hidden). The CBR Refresh cycle automatically
controls the row addresses by invoking the refresh
counter and controller.
Power-On
The initial application of the VCC supply requires a 200 µs
wait followed by a minimum of any eight initialization
,
cycles containing a RAS clock. During Power-On, the
VCC current is dependent on the input levels of RAS and
. It is recommended that RAS and
CAS
VCC or be held at a valid VIH during Power-On to avoid
current surges.
CAS
track with
PRELIMINARY (June, 2001, Version 0.0) 2 AMIC Technology, Inc.
Page 4
A42U0616 Series
Block Diagram
RAS
UCAS
LCAS
WE
Control
Clocks
Refresh Timer
Refresh control
VBB Generator
Row Decoder
Vcc
Vss
Lower
Data in
Buffer
Lower
Data out
Buffer
I/O0
to
I/O7
Memory Array
1,048,576 x 16
Cells
Column Decoder
Upper
Data in
Buffer
Sense Amps & I/O
Upper
Data out
Buffer
A0~A9
A0~A9
Refresh Counter
Row Address Buffer
Col. Address Buffer
Recommended Operating Conditions (Ta = 0°C to +70°C)
Symbol Description Min. Typ. Max. Unit
OE
I/O8
to
I/O15
VCC Power Supply 2.25 2.5 2.75 V
VSS Input High Voltage 0 0 0 V
VIH Input High Voltage 1.8 - VCC + 0.2 V
VIL Input Low Voltage -1.0 - 0.8 V
PRELIMINARY (June, 2001, Version 0.0) 3 AMIC Technology, Inc.
Page 5
A42U0616 Series
Truth Table
signal (
RAS
L
L
L
L
L
L
L H H X X Row High-Z
UCAS
H→L
H→L
H→L
H→L
H→L
H→L
LCAS
UCAS
UCAS
or
UCAS
LCAS
Function
Standby H X X X X X High-Z
Read: Word L L L H L Row/Col. Data Out
Read: Lower Byte L H L H L Row/Col. I/O0-7 = Data Out
Read: Upper Byte L L H H L Row/Col. I/O0-7 = High-Z
Write: Word L L L L H Row/Col. Data In
Write: Lower Byte L H L L H Row/Col. I/O0-7 = Data In
Write: Upper Byte L L H L H Row/Col. I/O0-7 = X
Read-Write L L L H→L L→H Row/Col. Data Out → Data In 1,2
EDO-Page-Mode Read: Hi-Z
-First cycle
-Subsequent Cycles
EDO-Page-Mode Write
-First cycle
-Subsequent Cycles
EDO-Page-Mode Read-Write
-First cycle
-Subsequent Cycles
Hidden Refresh Read L→H→L L L H L Row/Col. Data Out 2
Hidden Refresh Write L→H→L L L L X Row/Col. Data In → High-Z 1
RAS-Only Refresh
CBR Refresh H→L L L X X X High-Z 3
Self Refresh H→L L L H X X High-Z
Note: 1. Byte Write may be executed with either
2. Byte Read may be executed with either
3. Only one
CAS
WE OE
H→L
H→L
H→L
H→L
H→L
H→L
) must be active.
or
or
H
H
L
L
H→L
H→L
LCAS
LCAS
H→L
H→L
H
H
L→H
L→H
active.
active.
Address I/Os Notes
I/O8-15 = High-Z
I/O8-15 = Data Out
I/O8-15 = X
I/O8-15 = Data In
Row/Col.
Col.
Row/Col.
Col.
Row/Col.
Col.
Data Out → Data In
Data Out → Data In
Data Out
Data Out
Data In
Data In
2
2
1
1
1, 2
1, 2
PRELIMINARY (June, 2001, Version 0.0) 4 AMIC Technology, Inc.
Page 6
A42U0616 Series
Absolute Maximum Ratings*
Input Voltage (Vin) . . . . . . . . . . . . . . . -0.5V to VCC+0.5V
Output Voltage (Vout) . . . . . . . . . . . . . -0.5V to VCC+0.5V
Power Supply Voltage (VCC) . . . . . . . -0.5V to VCC+0.5V
Operating Temperature (TOPR) . . . . . . . . . . 0°C to +70°C
Storage Temperature (TSTG) . . . . . . . . . -55°C to +150°C
Soldering Temperature X Time (TSOLDER) . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C X 10sec
Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . 1W
Short Circuit Output Current (Iout) . . . . . . . . . . . . . . 50mA
*Comments
Stresses above thos e listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended
periods may affect device reliability.
Latch-up Current . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA
DC Electrical Characteristics (VCC = 2.5V ± 10%, VSS = 0V, Ta = 0°C to +70°C)
Symbol Parameter
IIL Input Leakage
Current
IOL Output Leakage
Current
ICC1 Operating Power
Supply Current
-50 -60 -80
Min. Max. Min. Max. Min. Max.
-5 +5 -5 +5 -5 +5 µA 0V ≤ Vin ≤ Vin + 0.2V
-5 +5 -5 +5 -5 +5 µA DOUT disabled,
- 120 - 110 - 100 mA
Unit Test Conditions Notes
Pins not under
Test = 0V
0V ≤ Vout ≤ + VCC
RAS,
UCAS,LCAS
Address cycling; tRC = min.
1, 2
ICC2 TTL Standby Power
- 1 - 1 - 1 mA
RAS=
UCAS=LCAS
=VIH
Supply Current
ICC3 Average Power
Supply Current,
RAS Refresh Mode
ICC4 EDO Page Mode
Average Power
Supply Current
ICC5
CAS -before-RAS
Refresh Power
- 120 - 110 - 100 mA
- 100 - 90 - 80 mA
- 110 - 100 - 90 mA
RAS cycling,
UCAS=LCAS
= V IH,
tRC = min.
RAS = VIL,
UCAS,LCAS
Address
cycling; tPC = min.
RAS,
UCAS, LCAS
cycling; tRC = min.
1, 2
Supply Current
ICC6 CMOS Standby
Power Supply
- 0.2 - 0.2 - 0.2 mA
RAS=
UCAS=LCAS
VCC - 0.2V
=
Current
ICC7 Self Refresh Mode
Current
- 250 - 250 - 250 µA
RAS=
≤ VSS+0.2V
CAS
All other input high levels
are VCC-0.2V or input low
levels are VSS +0.2V
VOH 2.0 - 2.0 - 2.0 - V IOUT = -2mA
Output Voltage
VOL
- 0.4 - 0.4 - 0.4 V IOUT = 2mA
1
1
PRELIMINARY (June, 2001, Version 0.0) 5 AMIC Technology, Inc.
Page 7
A42U0616 Series
AC Characte ristics (VCC = 2.5V ±10%, VSS = 0V, Ta = 0°C to +70°C)
Test Conditions:
Input timing reference level: V IH/VIL=1.8V/0.8V
Output reference level: V OH/VOL=1.6V/0.8V
Output Load: 1TTL gate + CL (100pF)
Assumed tT=2ns
Std
#
Symbol
tT Transition Time (Rise and Fall) 1 50 1 50 1 50 ns 4, 5
tREF Refresh Period - 16 - 16 - 16 ms 3
1 tRC Random Read or Write Cycle Time 84 - 104 - 134 - ns
2 tRP
3 tRAS
4 tCAS
5 tRCD
6 tRAD
7 tRSH
8 tCSH
9 tCRP
10 tASR Row Address Setup Time 0 - 0 - 0 - ns
RAS Precharge Time
RAS Pulse Width
CAS Pulse Width
RAS to CAS Delay Time
RAS to Column Address Delay Time
CAS to RAS Hold Time
CAS Hold Time
CAS to RAS Precharge Time
Parameter
-50 -60 -80
Min. Max. Min. Max. Min. Max.
30 - 40 - 50 - ns
50 10K 60 10K 80 10K ns
7 10K 10 10K 15 10K ns
11 37 14 45 20 60 ns 6
9 25 12 30 15 40 ns 7
7 - 10 - 10 - ns
37 - 40 - 50 - ns
5 - 5 - 5 - ns
Unit Notes
11 tRAH Row Address Hold Time 7 - 10 - 10 - ns
12 tCLZ
13 tRAC
14 tCAC
15 tAA Access Time from Column Address - 25 - 30 - 40 ns 7, 12
16 tAR
17 tRCS Read Command Setup Time 0 - 0 - 0 - ns
18 tRCH Read Command Hold Time 0 - 0 - 0 - ns 9
19 tRRH
CAS to Output in Low Z
Access Time from RAS
Access Time from CAS
Column Address Hold Time from RAS
Read Command Hold Time Reference
to RAS
0 - 0 - 0 - ns 8
- 50 - 60 - 80 ns 6,7
- 13 - 15 - 20 ns 6, 12
44 - 55 - 70 - ns
0 - 0 - 0 - ns 9
PRELIMINARY (June, 2001, Version 0.0) 6 AMIC Technology, Inc.
Page 8
A42U0616 Series
AC Characteristics (continued) (VCC = 2.5V ±10%, VSS = 0V, Ta = 0°C to +70°C)
Test Conditions:
Input timing reference level: V IH/VIL=1.8V/0.8V
Output reference level: V OH/VOL=1.6V/0.8V
Output Load: 1TTL gate + CL (100pF)
Assumed tT=2ns
Std
#
Symbol
20 tRAL
21 tCOH
22 tODS Output Disable Setup Time 0 - 0 - 0 - ns
23 tOFF Output Buffer Turn-Off Delay Time 0 13 0 15 0 20 ns 8, 10
24 tASC Column Address Setup Time 0 - 0 - 0 - ns
25 tCAH Column Address Hold Time 7 - 10 - 10 - ns
26 tOES
27 tWCS Write Command Setup Time 0 - 0 - 0 - ns 11
28 tWCH Write Command Hold Time 7 - 10 - 10 - ns 11
29 tWCR
30 tWP Write Command Pulse Width 7 - 10 - 10 - ns
31 tRWL
Column Address to RAS Lead Time
Output Hold After CAS Low
Low to CAS High Set Up
OE
Write Command Hold Time to RAS
Write Command to RAS Lead Time
Parameter
-50 -60 -80
Min. Max. Min. Max. Min. Max.
25 - 30 - 40 - ns
5 - 5 - 3 - ns
5 - 5 - 10 - ns
44 - 55 - 70 - ns
13 - 15 - 20 - ns
Unit Notes
32 tCWL
33 tDS Data-in setup Time 0 - 0 - 0 - ns
34 tDH Data-in Hold Time 7 - 10 - 15 - ns
35 tDHR
36 tRWC Read-Modify-Write Cycle Time 110 - 135 - 180 - ns
37 tRWD
38 tCWD
39 tAWD
PRELIMINARY (June, 2001, Version 0.0) 7 AMIC Technology, Inc.
Write Command to CAS Lead Time
Data-in Hold Time to RAS
RAS to WE Delay Time (Read-Modify-
Write)
CAS to WE Delay Time (Read-Modify-
Write)
Column Address to WE Delay Time
(Read-Modify-Write)
7 - 10 - 10 - ns
44 - 55 - 70 - ns
67 - 79 - 107 - ns 11
30 - 34 - 47 - ns 11
42 - 49 - 67 - ns 11
Page 9
A42U0616 Series
AC Characteristics (continued) (VCC = 2.5V ± 10%, VSS = 0V, Ta = 0°C to +70°C)
Test Conditions:
Input timing reference level: V IH/VIL=1.8V/0.8V
Output reference level: V OH/VOL=1.6V/0.8V
Output Load: 1TTL gate + CL (100pF)
Assumed tT=2ns
Std
#
Symbol
40 tOEH
41 tOEP
42 tPC Read or Write Cycle Time (EDO Page) 20 - 25 - 35 - ns 13
43 tCPA
44 tCP
45 tPCM EDO Page Mode RMW Cycle Time 58 - 68 - 80 - ns
46 tCRW
47 tRASP
48 tCSR
49 tCHR
50 tRPC
OE Hold Time from WE
OE High Pulse Width
Access Time from CAS Precharge
(EDO Page)
CAS Precharge Time (EDO Page)
EDO Page Mode CAS Pulse Width
(RMW)
RAS Pulse Width (EDO Page)
CAS Setup Time (CAS -before-RAS)
CAS Hold Time (CAS -before-RAS)
RAS to CAS Precharge Time
(CAS -before-RAS)
Parameter
-50 -60 -80
Min. Max. Min. Max. Min. Max.
7 - 10 - 20 - ns
2 - 2 - 5 - ns
- 28 - 33 - 45 ns 12
7 - 10 - 10 - ns
34 - 38 - 42 - ns
50 100K 60 100K 80 100
K
5 - 5 - 5 - ns 3
10 - 10 - 15 - ns 3
5 - 5 - 5 - ns
Unit Notes
ns
51 tROH
52 tOEA
53 tOED
54 tOEZ
55 tRASS
56 tRPS
57 tCHS
PRELIMINARY (June, 2001, Version 0.0) 8 AMIC Technology, Inc.
RAS Hold Time Reference to OE
OE Access Time
OE to Data Delay
Output Buffer Turn-off Delay from OE
RAS pulse width (C-B-Rself-refresh)
RAS precharge time
(C-B-Rself-refresh)
CAS hold time (C-B-Rself-refresh)
5 - 5 - 5 - ns
- 13 - 15 - 20 ns
13 - 15 - 20 - ns
0 13 0 15 0 20 ns 8
100 - 100 - 100 - µs
84 - 104 - 134 - ns
- 50 - 50 - 50 ns
Page 10
A42U0616 Series
Notes:
1. ICC1, ICC3, ICC4, and ICC5 depend on cycle rate.
2. ICC1 and ICC4 depend on output loading. Specified values are obtained with the outputs open.
3. An initial pause of 200µs is required after power-up followed by any 8 RAS cycles before proper device operation is
achieved. In the case of an internal refresh counter, a minimum of 8 CAS -before-RAS initialization cycles instead of
8RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks.
4. AC Characteristics assume tT = 2ns. All AC parameters are measured with a load equivalent to one TTL load and
100pF, V IL (min.) ≥ GND and VIH (max.) ≤ VCC.
5. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are measured
between V IH and VIL.
6. Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference
point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled exclusively by tCAC.
7. Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference
point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled exclusively by tAA.
8. Assumes three state test load (5pF and a 500Ω Thevenin equivalent).
9. Either tRCH or tRRH must be satisfied for a read cycle.
10. tOFF (max.) defines the time at which the output achieves the open circuit condition; it is not referenced to output
voltage levels.
11. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet
as electrical characteristics only. If tWCS ≥ tWCS (min.) and tWCH ≥ tWCH (min.), the cycle is an early write cycle
and data-out pins will remain open circuit, high impedance, throughout the entire cycle. If tRWD ≥ tRWD (min.) , tCWD ≥
tCWD (min.) and tAWD ≥ tAWD (min.), the cycle is a read-modify-write cycle and the data out will contain data read from
the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is
indeterminate.
12. Access time is determined by the longer of tAA or tCAC or tCPA.
13. tASC ≥ tCP to achieve tPC (min.) and tCPA (max.) values.
PRELIMINARY (June, 2001, Version 0.0) 9 AMIC Technology, Inc.
Page 11
A42U0616 Series
Word Read Cycle
tRC(1)
tRAS(3) tRP(2)
RAS
tCSH(8)
tCRP(9)
tRCD(5) tRSH(7)
tCRP(9)
UCAS
LCAS
Address
WE
OE
tRAD(6) tRAL(20)
tASR(10)
tRAH(11)
tASC(24) tCAH(25)
Row Address Column Address
tAR(16)
tRCS(17)
tAA(15)
tRAC(13)
tCAS(4)
tRCH(18)
tRRH(19)
tROH(51)
tOEA(52)
tCAC(14)
tOFF(23)
tOEZ(54)
I/O0 ~
I/O15
High-Z
Valid Data-out
tCLZ(12)
: High or Low
PRELIMINARY (June, 2001, Version 0.0) 10 AMIC Technology, Inc.
Page 12
A42U0616 Series
Word Write Cycle (Early Write)
tRC(1)
tRAS(3) tRP(2)
RAS
tCSH(8)
tCRP(9)
tRCD(5) tRSH(7)
tCRP(9)
UCAS
LCAS
Address
WE
OE
tCAS(4)
tAR(16)
tRAD(6) tRAL(20)
tASR(10)
tRAH(11)
tASC(24)
tCAH(25)
Row Address Column Address
tWCR(29)
tCWL(32)
tRWL(31)
tWP(30)
tWCS(27)
tWCH(28)
tDHR(35)
tDS(33) tDH(34)
I/O0 ~
I/O15
Valid Data-in
: High or Low
PRELIMINARY (June, 2001, Version 0.0) 11 AMIC Technology, Inc.
Page 13
A42U0616 Series
Word Write Cycle (Late Write)
tRC(1)
RAS
UCAS
LCAS
Address
WE
tRAS(3)
tCSH(8)
tCRP(9)
tASR(10)
tRAH(11)
tRCD(5) tRSH(7)
tAR(16)
tRAD(6) tRAL(20)
tASC(24)
tCAH(25)
Row Address Column Address
tWCR(29)
tRP(2)
tCRP(9)
tCAS(4)
tCWL(32)
tRWL(31)
tWP(30)
tOED(53)
tOEH(40)
OE
tDHR(35)
I/O0 ~
I/O15
tDS(33)
High-Z
Vaild Data-in
tDH(34)
: High or Low
PRELIMINARY (June, 2001, Version 0.0) 12 AMIC Technology, Inc.
Page 14
A42U0616 Series
Word Read-Modify-Write Cycle
tRWC(36)
tRAS(3) tRP(2)
RAS
tCSH(8)
tCRP(9)
tRCD(5) tRSH(7)
tCRP(9)
UCAS
LCAS
WE
OE
I/O0 ~
I/O15
tASR(10)
Row Address Column AddressAddress
tAR(16)
tRAD(6)
tRAH(11) tCAH(25)
t
RCS(17)
tRAC(13)
tASC(24)
tRWD(37)
tOEA(52)
tCAC(14)
tAA(15)
High-Z
tCLZ(12)
tCAS(4)
tAWD(39)
tCWD38)
tOED(53)
tOEZ(54)
tDS(33) tDH(34)
Data-out Data-in
tCWL(32)
tRWL(31)
tWP(30)
tOEH(40)
: High or Low
PRELIMINARY (June, 2001, Version 0.0) 13 AMIC Technology, Inc.
Page 15
A42U0616 Series
EDO Page Mode Word Read Cycle
tRASP(47) tRP(2)
RAS
UCAS
LCAS
Address
WE
OE
I/O0 ~
I/O15
tCRP(9)
tASR(10) tRAH(11)
Row Column Column Column
tRCD(5)
tRAD(6)
tRCS(17)
tCSH(8)
tCSH(8)
tAR(16)
tRAC(13)
tASC(24)
tAA(15)
tCAC(14)
tPC(42) tRSH(7)
tCAH(25)
tOES(26)
tCLZ(12)
tCP(44)
tOEA(52)
tRCH(25)
tCPA(43)
tCAC(14)
tCAH(25)
tOEP(41)
tCOH(21)
tCAS(4)tCAS(4)tCAS(4)
tRAL(20)
tCAH(25)
tASC(24)
tRCS(17)tRCS(17)
tAA(15)
tOEA(52)
tCAC(14)
tOEZ(54)
Data-out Data-out Data-out
tCLZ(12)
tCRP(9)
tRCH(25)
tRRH(19)
tOFF(23)
tOEZ(54)
: High or Low
PRELIMINARY (June, 2001, Version 0.0) 14 AMIC Technology, Inc.
Page 16
A42U0616 Series
EDO Page Mode Early Word Write Cycle
tRASP(47) tRP(2)
RAS
UCAS
LCAS
WE
OE
t
tCRP(9) tCRP(9)
tRAD(6)
tASR(10)
tRAH(11)
Row Column ColumnAddress
tWCS(27) tWCS(27)
tRCD(5)
t
ASC(24)
CSH(8)
t
CAH(25)
tASC(24)
t
CWL(32)
tWCH(28)
tWP(30) tWP(30)
Column
t
CWL(32)
t
PC(42)
t
CAH(25)
tASC(24)
tWCS(27)
tWCH(28)
t
tWP(30)
tCAS(4)tCP(44)tCAS(4)tCP(44)tCAS(4)
tRAL(20)
CWL(32)
t
RWL(31)
t
RSH(7)
t
CAH(25)
tWCH(28)
I/O0 ~
I/O15
tDH(34)
tDS(33) tDS(33)
tDS(33)
Data-in Data-in Data-in
tDH(34)
tDH(34)
PRELIMINARY (June, 2001, Version 0.0) 15 AMIC Technology, Inc.
: High or Low
Page 17
A42U0616 Series
EDO Page Mode Word Read-Modify-Write Cycle
RAS
UCAS
LCAS
Address
WE
OE
tRASP(47)
tCRP(9)
tRAD(6)
tASR(10) tRAH(11)
tCSH(8)
tRCD(5)
tCAH(25)
tASC(24)
tPCM(45) tRSH(7)
tCAH(25)
tASC(24)
Row Column Column Column
tCWL(32)
tRWD(37)
tRCS(17) tCWD(38)
tAWD(39)
tAA(15)
tOEA(52) tOEA(52)
tOEH(40)
tOED(53)
tCAC(14)
tCPA(43)
tCWD(38)
tWP(30) tWP(30) tWP(30)
tAWD(39) tAWD(39)
tOED(53)
tAA(15)
tCWL(32)
tCPA(43)
tAA(15)
tCAS(4)tCP(44)tCAS(4)tCP(44)tCAS(4)
tRAL(20)
tCAH(25)
tASC(24)
tCWD(38)
ROH(51)
t
tOEA(52)
tOED(53)
tRP(2)
CRP(9)
t
tCWL(32)
tRWL(31)
I/O 0 ~
High-Z
tRAC(13)
tOEZ(54)
tDH(34)
tDS(33)
tOEZ(54)
tDS(33)
tDH(34)
tOEZ(54)
tDH(34)
tDS(33)
I/O 15
tCLZ(12) tCLZ(12) tCLZ(12)
Data-out
Data-in
Data-out
Data-in
Data-in
Data-out
: High or Low
PRELIMINARY (June, 2001, Version 0.0) 16 AMIC Technology, Inc.
Page 18
A42U0616 Series
RAS Only Refresh Cycle
tRC(1)
tRAS(3) tRP(2)
RAS
tCRP(9)
UCAS
LCAS
tASR(10) tRAH(11)
Address
Row
Note: WE, OE = Don't care.
CAS Before RAS Refresh Cycle
tRP(2)
RAS
tRPC(50)
tRPC(50)
: High or Low
tRC(1)
tRAS(3) tRP(2)
tCHR(49)
tPC(42)
tCSR(48)
UCAS
LCAS
tOFF(23)
High-Z
I/O0 ~
I/O15
: High or LowNote: WE, OE, Address = Don't care.
PRELIMINARY (June, 2001, Version 0.0) 17 AMIC Technology, Inc.
Page 19
A42U0616 Series
Hidden Refresh Cycle (Word Read)
RAS
UCAS
LCAS
Address
WE
tAR(16)
t
CRP(9)
tASR(10)
tRCD(5)
tRAD(6)
tRAH(11)
tASC(24)
Row Column
tRC(1)
tRAS(3) tRP(2)
tRSH(7)
tRAL(20)
tCAH(25)
tRC(1)
tRAS(3) tRP(2)
tCHR(49)
tRRH(19)tRCS(17)
tCRP(9)
OE
I/O0 ~
I/O15
High-Z
tCLZ(12)
tRAC(13)
t
AA(15)
tCAC(14)
tOFF(23)
Valid Data-out
: High or Low
PRELIMINARY (June, 2001, Version 0.0) 18 AMIC Technology, Inc.
Page 20
A42U0616 Series
Hidden Refresh Cycle (Early Word Write)
RAS
UCAS
LCAS
Address
WE
tAR(16)
tCRP(9)
tASR(10)
tRCD(5)
tRAD(6)
tRAH(11)
tASC(24)
Row Column
t
WCS(27)
tRC(1)
tRAS(3) tRP(2)
tRSH(7)
tRAL(20)
tCAH(25)
t
WCH(28)
tWP(30)
tRC(1)
tRAS(3) tRP(2)
tCHR(49)
tCRP(9)
OE
tDS(33) tDH(34)
I/O0 ~
I/O
15
PRELIMINARY (June, 2001, Version 0.0) 19 AMIC Technology, Inc.
Valid Data-in
: High or Low
Page 21
A42U0616 Series
EDO Page Mode Read-Early-Write Cycle (Pseudo Read-Modify-Write)
RAS
UCAS
LCAS
Address
WE
tCRP(9)
tASR(10)
tRASP(47)
tCSH(8)
tRCD(5) tCAS(4) tCP(44) tCAS(4) tCP(44) tCAS(4) tCPR(9)
tRAD(6)
tRAD(6)
tRAH(11)
tASC(24)
tCAH(25)
tCAH(25)tASC(24)
Row Column Column
tRCH(18)
tRCS(17)
tAA(15)
tAA(15)
tRAC(13)
tCAC(14)
tCAP(43)
tCAC(14)
tRP(2)
tRSH(7)tPC(42)tPC(42)
tRAL(20)
tCAH(25)tASC(24)
Column
tWCS(27) tWCH(28)
tDS(33)
tDH(34)
tOEA(52)
OE
tCOH(21)
I/O0 ~
I/O15
Data-out Data-out Data-in
: High or Low
PRELIMINARY (June, 2001, Version 0.0) 20 AMIC Technology, Inc.
Page 22
A42U0616 Series
Self Refresh Mode
RAS
UCAS
LCAS
A0 ~ A7
I/O0 ~
I/O15
tRPC(50)
CPN(42)
t
tOFF(23)
Note: WE, OE = Don't care.
tCSR(48)
High-Z
tRASS(55)tRP(2)
tCHS(57)
tRPS(56)
tCRP(9)
tASR(10)
ROW COL
: High or Low
n Self Refresh Mode.
a. Entering the Self Refresh Mode:
The A42U0616 Self Refresh Mode is entered by using CAS before RAS cycle and holding RAS and CAS signal
"low" longer than 100µs.
b. Continuing the Self Refresh Mode:
The Self Refresh Mode is continued by holding RAS "low" after entering the Self Refresh Mode.
It does not depend on CAS being "high" or "low" after entering the Self Refresh Mode continue the Self Refresh Mode.
c. Exiting the Self Refresh Mode:
The A42U0616 exits the Self Refresh Mode when the RAS signal is brought "high".
PRELIMINARY (June, 2001, Version 0.0) 21 AMIC Technology, Inc.
Page 23
A42U0616 Series
Capacitance
Symbol Signals Parameter Max. Unit Test Conditions
CIN1 A0 – A9 5 pF Vin = 0V
CIN2
CI/O I/O0 - I/O15 I/O Capacitance 10 pF Vin = Vout = 0V
(Ta = Room Temperature, VCC = 2.5V ± 10%)
RAS,
,OE
CAS
, WE
Input Capacitance 7 pF Vin = 0V
Ordering Codes
Package\RAS Access Time
42L SOJ (400mil) A42U0616S-50 A42U0616S-60 A42U0616S-80 1K Yes
50(44)L TSOP type II (400mil) A42U0616V-50 A42U0616V-60 A42U0616V-80 1K Yes
50ns 60ns 80ns Refresh
Cycle
Self-
Refresh
PRELIMINARY (June, 2001, Version 0.0) 22 AMIC Technology, Inc.
Page 24
A42U0616 Series
Package Information
SOJ 42L Outline Dimensions unit: inches/mm
2242
E
HE
1
S
Seating Plane
D
b
1
b
e
21
A
A1 A2
y
D
L
e 1
θ
C
Symbol
A 0.128 0.138 0.148 3.25 3.51 3.76
A1 0.025 - - 0.64 - A2 0.105 0.110 0.115 2.67 2.79 2.92
b1
b 0.015 0.018 0.020 0.38 0.46 0.51
C 0.007 0.008 0.013 0.18 0.20 0.33
D 1.075 1.080 1.085 27.31 27.43 27.56
E 0.395 0.400 0.405 10.03 10.16 10.29
e - 0.050 - - 1.27 -
e1
HE
L 0.082 - - 2.08 - S - - 0.045 - - 1.14
y - - 0.003 - - 0.075
θ 0° - 10° 0° - 10°
Dimensions in inches Dimensions in mm
Min Nom Max Min Nom Max
0.026 0.028 0.032 0.66 0.71 0.81
- 0.370 - - 9.4 -
0.435 0.440 0.445 11.05 11.18 11.30
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e1 is for PC Board surface mount pad pitch design
reference only.
4. Dimension S includes end flash.
PRELIMINARY (June, 2001, Version 0.0) 23 AMIC Technology, Inc.
Page 25
A42U0616 Series
Package Information
TSOP 50/44L (Type II) Outline Dimensions unit: inches/mm
50
1
D
26
RAD R
E
HE
25
Detail "A"
A
Detail "A"
θ
L
L
1
RAD R1
c
S
B
Seating Plane
e
D
y
A1 A2
Symbol
A - - 0.048 - - 1.20
A1 0.002 - 0.006 0.05 - 0.15
A2 0.037 0.039 0.042 0.95 1.00 1.05
B 0.012 - 0.018 0.30 - 0.45
c 0.005 - 0.008 0.12 - 0.21
D 0.820 0.825 0.830 20.82 20.95 21.08
E 0.395 0.400 0.405 10.03 10.16 10.29
e 0.0315 BSC 0.80 BSC
HE 0.455 0.463 0.471 11.56 11.76 11.96
L 0.016 0.020 0.024 0.40 0.50 0.60
R 0.005 - 0.010 0.12 - 0.25
R1 0.005 - - 0.12 - -
S 0.0435 REF 0.875 BSC
θ 0° - 5° 0° - 5°
y - - 0.004 - - 0.1
Dimensions in inches Dimensions in mm
Min Nom Max Min Nom Max
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
PRELIMINARY (June, 2001, Version 0.0) 24 AMIC Technology, Inc.
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