Datasheet A42L2604V-45U, A42L2604V-45LU, A42L2604V-45L, A42L2604V-50LU, A42L2604V-50L Datasheet (AMIC)

A42L2604 Series

Preliminary 4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE

Preliminary (November, 2001, Version 0.2) AMIC Technology, Inc.

Document Title
4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE

Revision History

Rev. No. History Issue Date Remark

0.0 Initial issue June 13, 2001 Preliminary

0.1 Modify symbol HE dimensions in TSOP 24L package information July 10, 2001

0.2 Add -45 grade and modify the AC, DC data November 30, 2001

Add -U type spec.

A42L2604 Series

Preliminary 4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE

PRELIMINARY (November, 2001, Version 0.2) 1 AMIC Technology, Inc.

Features

n Organization: 4,194,304 words X 4 bits
n Part Identification

- A42L2604 (2K Ref.)

- A42L2604-L (2K Ref. with self-refresh)

n Single 3.3V power supply/built-in VBB generator
n Low power consumption

- Operating: 80mA (-45 max)

- Standby: 1mA (TTL), 1mA (CMOS),
350µA (Self-refresh current)

n High speed

- 45/50 ns RAS access time

- 20/22 ns column address access time

- 12/13 ns CAS access time

- 18/20 ns EDO Page Mode Cycle Time

n Industrial operating temperature range: -40°C to +85°C

for -U

n Fast Page Mode with Extended Data Out
n 2K Refresh Cycle in 32ms

n Read-modify-write, RAS -only, CAS -before- RAS ,

Hidden refresh capability

n TTL-compatible, three-state I/O
n JEDEC standard packages

- 300mil, 24/26-pin SOJ

- 300mil, 24/26-pin TSOP type II package

General Description

The A42L2604 is a new generation randomly accessed
memory for graphics, organized in a 4,194,304-word by
4-bit configuration. This product can execute Write and

Read operation via

CAS

pin.

The A42L2604 offers an accelerated Fast Page Mode

Pin Configuration

nn SOJ nn TSOP

VCC

I/O

0

I/O

1

A3

CAS

I/O

2

I/O

3

VSS

A42L2604S

OE

WE

RAS

A10

A0
A1
A2

VCC

NC

VSS

A4

A5

A6

A7

A8

A9

13

12

11

10

9

8

6

5

4

3

2

1

14

15

16

17

18

19

21

22

23

24

25

26

VCC

I/O

0

I/O

1

A3

CAS

I/O

2

I/O

3

VSS

A42L2604V

OE

WE

RAS

A10

A0
A1
A2

VCC

NC

VSS

A4

A5

A6

A7

A8

A9

13

12

11

10

9

8

6

5

4

3

2

1

14

15

16

17

18

19

21

22

23

24

25

26

cycle with a feature called Extended Data Out (EDO).
This allow random access of up to 2048(2K Ref.) words
within a row at a 56/50 MHz EDO cycle, making the
A42L2604 ideally suited for graphics, digital signal
processing and high performance computing systems.

Pin Descriptions

Symbol Description

A0 – A10 Address Inputs (2K product)
I/O0 - I/O3 Data Input/Output

RAS

Row Address Strobe

CAS

Column Address Strobe

WE

Write Enable

OE

Output Enable

VCC 3.3V Power Supply
VSS Ground
NC No Connection

A42L2604 Series

PRELIMINARY (November, 2001, Version 0.2) 2 AMIC Technology, Inc.

Selection Guide

Symbol Description -45 -50 Unit

tRAC

Maximum RAS Access Time

45 50 ns

tAA Maximum Column Address Access Time 20 22 ns

tCAC

Maximum CAS Access Time

12 13 ns

tOEA

Maximum Output Enable (OE) Access Time

12 13 ns

tRC Minimum Read or Write Cycle Time 76 84 ns

tPC Minimum EDO Cycle Time 18 20 ns

Functional Description

The A42L2604 reads and writes data by multiplexing an
22-bit address into a 11-bit(2K) row and column address.

RAS

and

CAS

are used to strobe the row address and the

column address, respectively.

A Read cycle is performed by holding the WE signal high
during RAS/

CAS

operation. A Write cycle is executed by

holding the WE signal low during RAS /

CAS

operation;

the input data is latched by the falling edge of WE or

CAS

, whichever occurs later. The data inputs and outputs

are routed through 4 common I/O pins, with RAS ,

CAS

,

WE and OE controlling the in direction.

EDO Page Mode operation all 2048(2K) columns within a
selected row to be randomly accessed at a high data rate.
A EDO Page Mode cycle is initiated with a row address

latched by RAS followed by a column address latched by

CAS

. While holding RAS low,

CAS

can be toggled to

strobe changing column addresses, thus achieving shorter
cycle times.
The A42L2604 offers an accelerated Fast Page Mode
cycle through a feature called Extended Data Out, which

keeps the output drivers on during the

CAS

precharge

time (tcp). Since data can be output after

CAS

goes high,

the user is not required to wait for valid data to appear
before starting the next access cycle. Data-out will remain

valid as long as RAS and OE are low, and WE is high;
this is the only characteristic which differentiates Extended
Data Out operation from a standard Read or Fast Page
Read.

A memory cycle is terminated by returning both RAS and

CAS

high. Memory cell data will retain its correct state by

maintaining power and accessing all 2048(2K)
combinations of the 11-bit(2K) row addresses, regardless

of sequence, at least once every 32ms through any RAS
cycle (Read, Write) or RAS Refresh cycle (RAS -only,

CBR, or Hidden). The CBR Refresh cycle automatically
controls the row addresses by invoking the refresh counter
and controller.

Power-On

The initial application of the VCC supply requires a 200 µs
wait followed by a minimum of any eight initialization cycles

containing a RAS clock. During Power-On, the VCC
current is dependent on the input levels of RAS and

CAS

.

It is recommended that RAS and

CAS

track with VCC or

be held at a valid VIH during Power-On to avoid current
surges.

A42L2604 Series

PRELIMINARY (November, 2001, Version 0.2) 3 AMIC Technology, Inc.

Block Diagram

Recommended Operating Conditions (Ta = 0°C to +70°C or -40°C to +85°C)

Symbol Description Min. Typ. Max. Unit

VCC Power Supply 3.0 3.3 3.6 V

VSS Input High Voltage 0 0 0 V

VIH Input High Voltage 2.0 - VCC + 0.3 V

VIL Input Low Voltage -1.0 - 0.8 V

Control

Clocks

VBB Generator

Refresh Timer

Refresh control

Refresh Counter

Row Address Buffer

Col. Address Buffer

Row Decoder

Column Decoder

Memory Array
4,194,304 X 4

Cells

Sense Amps & I/O

Data in

Buffer

Data out

Buffer

Vcc
Vss

RAS
CAS

WE

A0~A10

A0~A10

I/O0

to

I/O3

OE

A42L2604 Series

PRELIMINARY (November, 2001, Version 0.2) 4 AMIC Technology, Inc.

Truth Table

Function

RAS

CAS

WE OE

Address I/Os

Standby H H X X X High-Z
Read: Word L L H L Row/Col. Data Out
Read L L H L Row/Col. Data Out
Write: Word (Early) L L L X Row/Col. Data In
Write (Early) L L L X Row/Col. Data In
Read-Write L L

H→L L→H

Row/Col.

Data Out → Data In

EDO-Page-Mode Read: Hi-Z

-First cycle

-Subsequent Cycles

L
L

H→L
H→L

H
H

H→L
H→L

Row/Col.

Col.

Data Out
Data Out

EDO-Page-Mode Write (Early)

-First cycle

-Subsequent Cycles

L
L

H→L
H→L

L
L

X
X

Row/Col.

Col.

Data In
Data In

EDO-Page-Mode Read-Write

-First cycle

-Subsequent Cycles

L
L

H→L
H→L

H→L
H→L

L→H
L→H

Row/Col.

Col.

Data Out → Data In
Data Out → Data In

Hidden Refresh Read

L→H→L

L H L Row/Col. Data Out

Hidden Refresh Write

L→H→L

L L X Row/Col.

Data In → High-Z

RAS-Only Refresh

L H X X Row High-Z

CBR Refresh

H→L

L X X X High-Z

Self Refresh (L-ver only)

H→L

L H X X High-Z

A42L2604 Series

PRELIMINARY (November, 2001, Version 0.2) 5 AMIC Technology, Inc.

Absolute Maximum Ratings*

Input Voltage (Vin) . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V

Output Voltage (Vout) . . . . . . . . . . . . . . . . -0.5V to +4.6V

Power Supply Voltage (VCC) . . . . . . . . . . . -0.5V to +4.6V

Operating Temperature (TOPR) . . . . . . . . . . 0°C to +70°C

Storage Temperature (TSTG) . . . . . . . . . -55°C to +150°C

Soldering Temperature X Time (TSOLDER) . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C X 10sec

Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . 1W

Short Circuit Output Current (Iout) . . . . . . . . . . . . . 50mA

Latch-up Current . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA

*Comments

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended
periods may affect device reliability.

DC Electrical Characteristics (VCC = 3.3V, VSS = 0V, Ta = 0°C to +70°C or -40°C to +85°C)

-45 -50

Symbol Parameter

Min. Max. Min. Max.

Unit Test Conditions Notes

IIL Input Leakage Current -5 +5 -5 +5

µA 0V ≤ Vin ≤ Vin + 0.3V

Pins not under
Test = 0V

IOL Output Leakage Current -5 +5 -5 +5

µA

DOUT disabled,
0V ≤ Vout ≤ + VCC

ICC1 Operating Power Supply

Current

- 80 - 75 mA

RAS,

UCAS,LCAS

and

Address cycling; tRC = min.

1, 2

ICC2 TTL Standby Power

Supply Current

- 1 - 1 mA

RAS=

UCAS=LCAS

=VIH

ICC3 Average Power

Supply Current,

RAS Refresh Mode

- 80 - 75 mA

RAS and Address cycling,

UCAS=LCAS

= VIH,

tRC = min.

1

ICC4 EDO Page Mode

Average Power
Supply Current

- 40 - 35 mA

RAS = VIL,

UCAS,LCAS

and Address

cycling; tPC = min.

1, 2

ICC5

CAS-before-RAS

Refresh Power
Supply Current

- 75 - 70 mA

RAS,

UCAS

and

LCAS

cycling; tRC = min.

1

ICC6 CMOS Standby Power

Supply Current

- 1 - 1 mA

RAS=

UCAS=LCAS

=

VCC - 0.2V

ICC7 Self Refresh Mode

Current

- 350 - 350

µA

RAS=

CAS

≤VSS+0.2V

All other input high levels are
VCC-0.2V or input low levels

are VSS +0.2V
VOH 2.4 - 2.4 - V IOUT = -2.0mA
VOL

Output Voltage

- 0.4 - 0.4 V IOUT =2.0mA

A42L2604 Series

PRELIMINARY (November, 2001, Version 0.2) 6 AMIC Technology, Inc.

AC Characteristics (VCC = 3.3V ± 10%, VSS = 0V, Ta = 0°C to +70°C or -40°C to +85°C)

Test Conditions:

Input timing reference level: VIH/VIL=2.0V/0.8V
Output reference level: VOH/VOL=2.0V/0.8V
Output Load: 2TTL gate + CL (50pF)
Assumed tT=2ns

-45 -50

#

Std

Symbol

Parameter

Min. Max. Min. Max.

Unit Notes

tT Transition Time (Rise or Fall) 1 50 1 50 ns 4, 5
1 tRC Random Read or Write Cycle Time 76 - 84 - ns
2 tRP

RAS Precharge Time

27 - 30 - ns

3 tRAS

RAS Pulse Width

45 10K 50 10K ns

4 tCAS

CAS Pulse Width

7 10K 8 10K ns

5 tRCD

RAS to CASDelay Time

10 33 11 37 ns 6

6 tRAD

RAS to Column Address Delay Time

8 25 9 28 ns 7

7 tRSH

CAS to RAS Hold Time

7 - 8 - ns

8 tCSH

CAS Hold Time

35 - 37 - ns

9 tCRP

CAS to RAS Precharge Time

5 - 5 - ns

10 tASR Row Address Setup Time 0 - 0 - ns
11 tRAH Row Address Hold Time 7 - 8 - ns
12 tCLZ

CAS to Output in Low Z

3 - 3 - ns 8

13 tRAC

Access Time from RAS

- 45 - 50 ns 6,7

14 tCAC

Access Time from CAS

- 12 - 13 ns 6, 12

15 tAA Access Time from Column Address - 20 - 22 ns 7, 12
16 tOEA

Access Time from OE

- 12 - 13 ns

17 tAR

Column Address Hold Time from RAS

40 - 45 - ns

18 tRCS Read Command Setup Time 0 - 0 - ns
19 tRCH Read Command Hold Time 0 - 0 - ns 9

A42L2604 Series

PRELIMINARY (November, 2001, Version 0.2) 7 AMIC Technology, Inc.

AC Characteristics (continued) (VCC = 3.3V ± 10%, VSS = 0V, Ta = 0°C to +70°C or -40°C to +85°C)

Test Conditions:

Input timing reference level: VIH/VIL=2.0V/0.8V
Output reference level: VOH/VOL=2.0V/0.8V
Output Load: 2TTL gate + CL (50pF)
Assumed tT=2ns

-45 -50

#

Std

Symbol

Parameter

Min. Max. Min. Max.

Unit Notes

20 tRRH

Read Command Hold Time Reference to RAS

0 - 0 - ns 9

21 tRAL

Column Address to RAS Lead Time

20 - 22 - ns

22 tCOH

Output Hold After CAS Low

- 2 - 3 ns

23 tOFF Output Buffer Turn-Off Delay Time - 2 - 3 ns 8, 10
24 tASC Column Address Setup Time 0 - 0 - ns
25 tCAH Column Address Hold Time 7 - 8 - ns
26 tOES

OE

Low to CAS High Set Up

10 - 10 - ns

27 tWCS Write Command Setup Time 0 - 0 - ns 11
28 tWCH Write Command Hold Time 7 - 8 - ns 11
29 tWCR

Write Command Hold Time to RAS

40 - 45 - ns

30 tWP Write Command Pulse Width 7 - 8 - ns
31 tRWL

Write Command to RAS Lead Time

12 - 13 - ns

32 tCWL

Write Command to CAS Lead Time

7 - 8 - ns

33 tDS Data-in setup Time 0 - 0 - ns
34 tDH Data-in Hold Time 7 - 8 - ns
35 tDHR

Data-in Hold Time to RAS

40 - 45 - ns

36 tRWC Read-Modify-Write Cycle Time 104 - 114 - ns
37 tRWD

RAS to WE Delay Time (Read-Modify-Write)

59 - 65 - ns 11

38 tCWD

CAS to WE Delay Time (Read-Modify-Write)

26 - 28 - ns 11

39 tAWD

Column Address to WE Delay Time
(Read-Modify-Write)

34 - 37 - ns 11

A42L2604 Series

PRELIMINARY (November, 2001, Version 0.2) 8 AMIC Technology, Inc.

AC Characteristics (continued) (VCC = 3.3V ± 10%, VSS = 0V, Ta = 0°C to +70°C or -40°C to +85°C)

Test Conditions:

Input timing reference level: VIH/VIL=2.0V/0.8V
Output reference level: VOH/VOL=2.0V/0.8V
Output Load: 2TTL gate + CL (50pF)
Assumed tT=2ns

-45 -50

#

Std

Symbol

Parameter

Min. Max. Min. Max.

Unit Notes

40 tOEH

OE Hold Time from WE

7 - 8 - ns

41 tOEP

OE High Pulse Width

5 - 5 - ns

42 tPC Read or Write Cycle Time (EDO Page) 18 - 20 - ns 13

43 tCPA

Access Time from CAS Precharge
(EDO Page)

- 21 - 23 ns 12

44 tCP

CAS Precharge Time

7 - 8 - ns

45 tPCM EDO Page Mode RMW Cycle Time 46 - 50 - ns

46 tCRW

EDO Page Mode CAS Pulse Width
(RMW)

35 - 38 - ns

47 tRASP

RAS Pulse Width (EDO Page)

45 200K 50 200K ns

48 tCSR

CAS Setup Time ( CAS -before-RAS)

5 - 5 - ns 3

49 tCHR

CAS Hold Time ( CAS -before-RAS)

10 - 10 - ns 3

50 tRPC

RAS to CAS Precharge Time

10 - 10 - ns

51 tOEZ

Output Buffer Turn-off Delay from OE

- 2 - 3 ns 8

52 tRASS

RAS pulse width (C-B-Rself refresh)

100 - 100 -

µs

53 tRPS

RAS precharge time (C-B-Rself refresh)

76 - 84 - ns

54 tCHS

CAShold time (C-B-Rself refresh)

-50 - -50 - ns

A42L2604 Series

PRELIMINARY (November, 2001, Version 0.2) 9 AMIC Technology, Inc.

Notes:

1. ICC1, ICC3, ICC4, and ICC5 depend on cycle rate.

2. ICC1 and ICC4 depend on output loading. Specified values are obtained with the outputs open.

3. An initial pause of 200µs is required after power-up followed by any 8 RAS cycles before proper device operation is
achieved. In the case of an internal refresh counter, a minimum of 8 CAS -before-RAS initialization cycles instead of 8

RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks.

4. AC Characteristics assume tT = 2ns. All AC parameters are measured with a load equivalent to two TTL loads and

50pF, VIL (min.) ≥ GND and VIH (max.) ≤ VCC.

5. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are measured

between VIH and VIL.

6. Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference

point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled exclusively by tCAC.

7. Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference

point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled exclusively by tAA.

8. Assumes three state test load (5pF and a 500Ω Thevenin equivalent).

9. Either tRCH or tRRH must be satisfied for a read cycle.

10. tOFF (max.) defines the time at which the output achieves the open circuit condition; it is not referenced to output

voltage levels.

11. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet

as electrical characteristics only. If tWCS ≥ tWCS (min.) and tWCH ≥ tWCH (min.), the cycle is an early write cycle
and data-out pins will remain open circuit, high impedance, throughout the entire cycle. If tRWD ≥ tRWD (min.) , tCWD ≥
tCWD (min.) and tAWD ≥ tAWD (min.), the cycle is a read-modify-write cycle and the data out will contain data read from
the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is
indeterminate.

12. Access time is determined by the longer of tAA or tCAC or tCPA.

13. tASC ≥ tCP to achieve tPC (min.) and tCPA (max.) values.

A42L2604 Series

PRELIMINARY (November, 2001, Version 0.2) 10 AMIC Technology, Inc.

Word Read Cycle

t

RAS(3)

t

RP(2)

t

RC(1)

t

CRP(9)

t

CSH(8)

t

RCD(5)

t

RSH(7)

t

CAS(4)

t

ASR(10)

t

CRP(9)

t

RAH(11)

t

ASC(24)

t

CAH(25)

t

RAD(6)

t

RAL(21)

t

RCH(19)

t

RRH(20)

t

AR(17)

t

RCS(18)

t

OEA(16)

t

RAC(13)

t

AA(15)

t

CAC(14)

t

CLZ(12)

t

OEZ(51)

t

OFF(23)

High-Z

: High or Low

Valid Data-out

Row Address Column Address

I/O0 ~
I/O

3

OE

WE

Address

CAS

RAS

A42L2604 Series

PRELIMINARY (November, 2001, Version 0.2) 11 AMIC Technology, Inc.

Word Write Cycle (Early Write)

t

RAS(3)

t

RP(2)

t

RC(1)

t

CRP(9)

t

CSH(8)

t

RCD(5)

t

RSH(7)

t

CAS(4)

t

ASR(10)

t

CRP(9)

t

RAH(11)

t

ASC(24)

t

CAH(25)

t

RAD(6)

t

RAL(21)

t

WCH(28)

: High or Low

Row Address Column Address

I/O0 ~
I/O

3

OE

Address

CAS

RAS

t

AR(17)

t

CWL(32)

t

RWL(31)

t

WP(30)

t

WCS(27)

Valid Data-in

t

DS(33)

t

DH(34)

WE

t

WCR(29)

t

DHR(35)

A42L2604 Series

PRELIMINARY (November, 2001, Version 0.2) 12 AMIC Technology, Inc.

Word Write Cycle (Late Write)

t

RAS(3)

t

RP(2)

t

RC(1)

t

CRP(9)

t

CSH(8)

t

RCD(5)

t

RSH(7)

t

CAS(4)

t

ASR(10)

t

CRP(9)

t

ASC(24)

t

CAH(25)

t

RAD(6)

t

RAL(21)

Row Address Column Address

Address

CAS

RAS

t

AR(17)

t

CWL(32)

t

RWL(31)

t

WP(30)

t

RAH(11)

t

OEH(40)

t

DS(33)

t

DH(34)

I/O0 ~
I/O

3

: High or Low

OE

WE

High-Z

Vaild Data-in

t

WCR(29)

t

DHR(35)

A42L2604 Series

PRELIMINARY (November, 2001, Version 0.2) 13 AMIC Technology, Inc.

Word Read-Modify-Write Cycle

t

RAS(3)

t

RP(2)

t

RWC(36)

t

CRP(9)

t

CSH(8)

t

RCD(5)

t

RSH(7)

t

ASR(10)

t

CRP(9)

t

RAH(11)

t

CAH(25)

t

RAD(6)

Row Address Column AddressAddress

CAS

RAS

t

AR(17)

t

RWL(31)

t

ASC(24)

t

CWL(32)

t

AWD(39)

t

CWD38)

t

RWD(37)

t

WP(30)

t

OEA(16)

t

OEZ(51)

t

CLZ(12)

t

CAC(14)

t

AA(15)

t

RAC(13)

t

DS(33)tDH(34)

High-Z

Data-out Data-in

: High or Low

I/O0 ~
I/O

3

OE

WE

t

OEH(40)

t

RCS(18)

A42L2604 Series

PRELIMINARY (November, 2001, Version 0.2) 14 AMIC Technology, Inc.

EDO Page Mode Word Read Cycle

t

RASP(47)

t

RP(2)

RAS

CAS

t

CAS(4)

t

CAS(4)

t

CAS(4)

t

RCD(5)

t

CSH(8)

t

CRP(9)

t

CRP(9)

t

PC(42)

t

RSH(7)

t

ASR(10)tRAH(11)

t

RAD(6)

t

AR(16)

t

RAL(21)

Address

OE

WE

I/O0 ~
I/O

3

: High or Low

t

ASC(24)

t

CP(44)

t

CSH(8)

t

ASC(24)

t

CAH(25)

t

CAH(25)

Row Column Column Column

t

RCH(19)

t

RCS(18)

t

RCS(18)

t

RCH(25)

t

RCS(18)

t

CAH(25)

t

RRH(20)

t

OFF(23)

t

OEZ(51)

t

AA(15)

t

OEA(16)

t

OEP(41)

t

CAC(14)

t

CLZ(12)

t

OEZ(51)

t

CPA(43)

t

OES(26)

t

AA(15)

t

OEA(16)

t

COH(22)

t

CAC(14)

t

RAC(13)

t

CAC(14)

t

CLZ(12)

Data-out Data-out Data-out

A42L2604 Series

PRELIMINARY (November, 2001, Version 0.2) 15 AMIC Technology, Inc.

EDO Page Mode Early Word Write Cycle

t

RASP(47)

t

RP(2)

RAS

CAS

t

CAS(4)

t

CP(44)

t

CAS(4)

t

CP(44)

t

CAS(4)

t

RCD(5)

t

CSH(8)

t

CRP(9)

t

CRP(9)

t

PC(42)

t

RSH(7)

t

ASR(10)

t

RAH(11)

t

RAD(6)

t

ASC(24)

t

CAH(25)

t

ASC(24)

t

CAH(25)

t

CAH(25)

t

ASC(24)

t

RAL(21)

Row Column ColumnAddress

WE

t

CWL(32)

t

WCH(28)

t

WCS(27)

t

WCS(27)

Column

t

CWL(32)

t

WCH(28)

t

WCS(27)

t

WCH(28)

t

CWL(32)

t

RWL(31)

t

WP(30)

t

WP(30)

t

WP(30)

t

DH(34)

t

DS(33)

t

DH(34)

t

DS(33)

t

DS(33)

t

DH(34)

Data-in Data-in Data-in

I/O0 ~
I/O

3

OE

: High or Low

A42L2604 Series

PRELIMINARY (November, 2001, Version 0.2) 16 AMIC Technology, Inc.

EDO Page Mode Word Read-Modify-Write Cycle

t

RASP(47)

RAS

t

CRW(46)

t

CP(44)

t

CRW(46)

t

CP(44)

t

CRW(46)

t

RCD(5)

t

CSH(8)

t

CRP(9)

t

CRP(9)

t

PCM(45)

t

RSH(7)

t

RP(2)

t

ASR(10)

t

RAH(11)

t

RAD(6)

t

ASC(24)

t

CAH(25)

t

ASC(24)

t

CAH(25)

t

ASC(24)

t

CAH(25)

t

RAL(21)

t

RCS(18)

t

CWD(38)

t

RWD(37)

t

CWL(32)

t

CWD(38)

t

CWL(32)

t

CWD(38)

t

CWL(32)

t

RWL(31)

t

OEA(16)

t

OEA(16)

t

OEA(16)

t

WP(30)

t

WP(30)

t

WP(30)

t

AWD(39)

t

AWD(39)

t

AWD(39)

t

CAC(14)

t

AA(15)

t

RAC(13)

t

OEZ(51)

t

DS(33)

t

AA(15)

t

CPA(43)

t

DH(34)

t

OEZ(51)

t

DS(33)

t

DH(34)

t

OEZ(51)

t

DS(33)

t

DH(34)

t

AA(15)

t

CPA(43)

t

CLZ(12)

t

CLZ(12)

t

CLZ(12)

High-Z

: High or Low

I/O0 ~

I/O

3

OE

WE

Address

CAS

Data-out

Data-in

Data-out

Data-in

Data-out

Data-in

Row Column Column Column

t

OEH(40)

A42L2604 Series

PRELIMINARY (November, 2001, Version 0.2) 17 AMIC Technology, Inc.

RAS Only Refresh Cycle

CAS Before RAS Refresh Cycle

t

RAS(3)

t

RP(2)

t

RC(1)

RAS

t

CRP(9)

t

RPC(50)

t

ASR(10)

t

RAH(11)

Address

: High or Low

Row

Note: WE, OE = Don't care.

CAS

t

RAS(3)

t

RP(2)

t

RC(1)

RAS

t

RP(2)

t

RPC(50)

t

PC(44)

t

CSR(48)

t

CHR(49)

t

OFF(23)

I/O0 ~
I/O

3

CAS

High-Z

: High or LowNote: WE, OE, Address = Don't care.

A42L2604 Series

PRELIMINARY (November, 2001, Version 0.2) 18 AMIC Technology, Inc.

Hidden Refresh Cycle (Word Read)

t

RAS(3)

t

RP(2)

t

RC(1)

t

CRP(9)

t

AR(17)

t

RCD(5)

t

ASR(10)

t

CRP(9)

t

ASC(24)

t

CAH(25)

t

RAD(6)

Address

CAS

RAS

t

RAH(11)

t

RRH(20)

t

RCS(18)

I/O0 ~
I/O

3

: High or Low

OE

High-Z

t

RAS(3)

t

RP(2)

t

CHR(49)

t

RC(1)

t

RSH(7)

t

RAL(21)

t

CAC(14)

t

OFF(23)

t

AA(15)

t

CLZ(12)

t

RAC(13)

WE

Row Column

Valid Data-out

A42L2604 Series

PRELIMINARY (November, 2001, Version 0.2) 19 AMIC Technology, Inc.

Hidden Refresh Cycle (Early Word Write)

t

RAS(3)

t

RP(2)

t

RC(1)

t

CRP(9)

t

AR(17)

t

RCD(5)

t

ASR(10)

t

CRP(9)

t

ASC(24)

t

CAH(25)

t

RAD(6)

Address

RAS

t

RAH(11)

: High or Low

OE

t

RAS(3)

t

RP(2)

t

CHR(49)

t

RC(1)

t

RSH(7)

t

RAL(21)

WE

Row Column

t

WCS(27)

t

WCH(28)

t

WP(30)

t

DS(33)

t

DH(34)

Valid Data-in

0

~

3

A42L2604 Series

PRELIMINARY (November, 2001, Version 0.2) 20 AMIC Technology, Inc.

EDO Page Mode Read-Early-Write Cycle (Pseudo Read-Modify-Write)

RAS

: High or Low

I/O0 ~
I/O

3

OE

WE

Address

CAS

t

RP(2)

t

RASP(47)

t

CRP(9)

t

CSH(8)

t

RCD(5)

t

CAS(4)

t

CP(44)

t

CAS(4)

t

CP(44)

t

CAS(4)

t

CPR(9)

t

RSH(7)

t

PC(42)

t

PC(42)

Row Column Column

t

RAL(21)

t

CAH(25)

t

ASC(24)

t

CAH(25)

t

ASC(24)

t

CAH(25)

t

ASC(24)

t

ASR(10)

t

RAH(11)

t

RAD(6)

t

RAD(6)

Column

t

RCS(18)

t

RCH(19)

t

WCS(27)

t

WCH(28)

Data-out Data-out Data-in

t

DH(34)

t

DS(33)

t

AA(15)

t

CAP(43)

t

CAC(14)

t

COH(22)

t

AA(15)

t

RAC(13)

t

CAC(14)

t

OEA(16)

A42L2604 Series

PRELIMINARY (November, 2001, Version 0.2) 21 AMIC Technology, Inc.

Self Refresh Mode

n Self Refresh Mode.
a. Entering the Self Refresh Mode:

The A42L2604 Self Refresh Mode is entered by using CAS before RAS cycle and holding RAS and CAS signal “low”
longer than 100µs.

b. Continuing the Self Refresh Mode:

The Self Refresh Mode is continued by holding RAS “low” after entering the Self Refresh Mode.
It does not depend on CAS being “high” or “low” after entering the Self Refresh Mode continue the Self Refresh Mode.

c. Exiting the Self Refresh Mode:

The A42L2604 exits the Self Refresh Mode when the RAS signal is brought “high”.

t

RASS(52)

t

RP(2)

t

CRP(9)

t

CSR(48)

t

RPC(50)

RAS

t

RPS(53)

t

CHS(54)

t

ASR(10)

t

CP(44)

t

OFF(23)

A0 ~ A10

: High or Low

High-Z

I/O0 ~ I/O

3

UCAS
LCAS

ROW COL

Note: WE, OE = Don't care.

A42L2604 Series

PRELIMINARY (November, 2001, Version 0.2) 22 AMIC Technology, Inc.

Capacitance

(f = 1MHz, Ta = Room Temperature, VCC = 3.3V ± 10%)

Symbol Signals Parameter Max. Unit Test Conditions

CIN1 A0 – A10 5 pF Vin = 0V
CIN2

RAS,

CAS

,

WE, OE

Input Capacitance 7 pF Vin = 0V

CI/O I/O0 - I/O3 I/O Capacitance 7 pF Vin = Vout = 0V

Ordering Codes

Package\

RAS

Access Time

45ns 50ns Refresh Cycle Self-Refresh

24/26L SOJ (300mil) A42L2604S-45 A42L2604S-50 2K No
24/26L TSOP type II (300mil) A42L2604V-45 A42L2604V-50 2K No
24/26L TSOP type II (300mil) A42L2604V-45U A42L2604V-50U 2K No

24/26L SOJ (300mil) A42L2604S-45L A42L2604S-50L 2K Yes
24/26L TSOP type II (300mil) A42L2604V-45L A42L2604V-50L 2K Yes
24/26L TSOP type II (300mil) A42L2604V-45LU A42L2604V-50LU 2K Yes

Note: -U is for industrial operating temperature range.

A42L2604 Series

PRELIMINARY (November, 2001, Version 0.2) 23 AMIC Technology, Inc.

Package Information
SOJ 24L/26L (300mil) Outline Dimensions unit: inches/mm

E

1

E

A

2

e

E2

12

1324

S

y

A1

b

2

b

19 18

1 6 7

Pin 1 Identifier

- y -

Seating Plane 0.004

A

A

A

θ

D

C

Dimensions in inches Dimensions in mm

Symbol

Min Nom Max Min Nom Max

A - - 0.140 - - 3.56
A1 0.070 0.080 0.090 1.78 2.03 2.29
A2 0.095 0.100 0.105 2.41 2.54 2.67

b 0.016 0.018 0.022 0.41 0.46 0.56

b2 0.026 0.028 0.032 0.66 0.71 0.81

C 0.008 0.010 0.014 0.20 0.25 0.36

D - 0.675 0.686 - 17.15 17.42

E 0.327 0.337 0.347 8.31 8.56 8.81
E1

0.295 0.300 0.305 7.49 7.62 7.75

E2

0.245 0.265 0.285 6.22 6.73 7.24

e 0.044 0.050 0.056 1.12 1.27 1.42

S - - 0.048 - - 1.22

θ 0°

-

10° 0°

-

10°

Notes:

1. The maximum value of dimension D includes end flash.

2. Dimension E1 does not include resin fins.

3. Dimension E2 is for PC Board surface mount pad pitch design
reference only.

4. Dimension S includes end flash.

A42L2604 Series

PRELIMINARY (November, 2001, Version 0.2) 24 AMIC Technology, Inc.

Package Information
TSOP 24/26L (TYPE II) Outline Dimensions unit: inches/mm

E

D

S B

13

121

24

e

H

E

L1

θ

0.010

D

y

A

2A

1

A

L1 L

c

Dimensions in inches

Dimensions in mm

Symbol

Min Nom Max Min Nom Max

A - - 0.047 - - 1.20
A1 0.002 - - 0.05 - ­A2 0.037 0.039 0.041 0.95 1.00 1.05

B 0.012 0.016 0.020 0.30 0.40 0.50

c - 0.005 - - 0.127 ­D 0.671 0.675 0.679 17.04 17.14 17.24
E 0.298 0.300 0.302 7.57 7.62 7.67

e - 0.050 - - 1.27 -

HE 0.355 0.363 0.371 9.02 9.22 9.42

L - 0.031 - - 0.80 -

L1 0.016 0.020 0.024 0.40 0.50 0.60

S - 0.037 - - 0.95 -

y - - 0.004 - - 0.10

θ 0°

-

5° 0°

-

5°

Notes:

1. Dimension D&E do not included interiead flash.

2. Dimension B does not included dambar protrusion / intrusion.

3. Dimension S includes end flash.