Datasheet A42L2604V, A42L2604V-50, A42L2604V-50U, A42L2604S-50, A42L2604S Datasheet (AMICC)
Page 1
A42L2604 Series
Preliminary 4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Document Title
4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Revision History
Rev. No. History Issue Date Remark
0.0 Initial issue June 13, 2001 Preliminary
0.1 Modify symbol HE dimensions in TSOP 24L package information July 10, 2001
0.2 Add -45 grade and modify the AC, DC data November 30, 2001
0.3 Modify DC data and all parts guarantee self-refresh mode June 10, 2002
Add -U type spec.
PRELIMINARY (June, 2002, Version 0.3) AMIC Technology, Inc.
Page 2
A42L2604 Series
Preliminary 4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Features
n Organization: 4,194,304 words X 4 bits
n Part Identification
- A42L2604 (2K Ref.)
n Single 3.3V power supply/built-in VBB generator
n Low power consumption
- Operating: 80mA (-45 max)
- Standby: 1.0mA (TTL), 1.5mA (CMOS),
350µA (Self-refresh current)
n High speed
- 45/50 ns RAS access time
- 20/22 ns column address access time
- 12/13 ns CAS access time
- 18/20 ns EDO Page Mode Cycle Time
General Description
The A42L2604 is a new generation randomly accessed
memory for graphics, organized in a 4,194,304-word by
4-bit configuration. This product can execute Write and
Read operation via
CAS
pin.
The A42L2604 offers an accelerated Fast Page Mode
Pin Configuration
nn SOJ nn TSOP
VCC
I/O
I/O
WE
RAS
NC
A10
VCC
26
1
2
0
1
3
4
A42L2604S
5
6
8
A0
9
A1
10
A2
11
A3
12
13
VSS
25
I/O
3
I/O
24
23
22
21
19
18
17
16
15
14
2
CAS
OE
A9
A8
A7
A6
A5
A4
VSS
VCC
I/O
I/O
WE
RAS
NC
A10
VCC
0
1
A0
A1
A2
A3
26
1
25
2
3
24
4
23
A42L2604V
5
22
6
21
8
19
9
18
10
17
11
16
12
15
13
14
VSS
I/O
I/O
CAS
OE
A9
A8
A7
A6
A5
A4
VSS
3
2
n Industrial operating temperature range: -40°C to +85°C
for -U
n Fast Page Mode with Extended Data Out
n 2K Refresh Cycle in 32ms
n Read-modify-write, RAS -only, CAS -before- RAS ,
Hidden refresh capability
n TTL-compatible, three-state I/O
n JEDEC standard packages
- 300mil, 24/26-pin SOJ
- 300mil, 24/26-pin TSOP type II package
cycle with a feature called Extended Data Out (EDO).
This allow random access of up to 2048(2K Ref.) words
within a row at a 56/50 MHz EDO cycle, making the
A42L2604 ideally suited for graphics, digital signal
processing and high performance computing systems.
Pin Descriptions
Symbol Description
A0 – A10 Address Inputs (2K product)
I/O0 - I/O3 Data Input/Output
RAS
CAS
WE
OE
VCC 3.3V Power Supply
VSS Ground
NC No Connection
Row Address Strobe
Column Address Strobe
Write Enable
Output Enable
PRELIMINARY (June, 2002, Version 0.3) 1 AMIC Technology, Inc.
Page 3
A42L2604 Series
Selection Guide
Symbol Description -45 -50 Unit
tRAC
tAA Maximum Column Address Access Time 20 22 ns
tCAC
tOEA
tRC Minimum Read or Write Cycle Time 76 84 ns
tPC Minimum EDO Cycle Time 18 20 ns
Maximum RAS Access Time
Maximum CAS Access Time
Maximum Output Enable (OE) Access Time
45 50 ns
12 13 ns
12 13 ns
Functional Description
The A42L2604 reads and writes data by multiplexing an
22-bit address into a 11-bit(2K) row and column address.
and
RAS
column address, respectively.
A Read cycle is performed by holding the WE signal high
during RAS/
holding the WE signal low during RAS /
the input data is latched by the falling edge of WE or
, whichever occurs later. The data inputs and outputs
CAS
are routed through 4 common I/O pins, with RAS,
WE and OE controlling the in direction.
EDO Page Mode operation all 2048(2K) columns within a
selected row to be randomly accessed at a high data rate.
A EDO Page Mode cycle is initiated with a row address
latched by RAS followed by a column address latched by
. While holding RAS low,
CAS
strobe changing column addresses, thus achieving shorter
cycle times.
The A42L2604 offers an accelerated Fast Page Mode
cycle through a feature called Extended Data Out, which
keeps the output drivers on during the
time (tcp). Since data can be output after
the user is not required to wait for valid data to appear
before starting the next access cycle. Data-out will remain
are used to strobe the row address and the
CAS
operation. A Write cycle is executed by
CAS
CAS
can be toggled to
CAS
CAS
CAS
operation;
CAS
precharge
goes high,
valid as long as RAS and OE are low, and WE is high;
this is the only characteristic which differentiates Extended
Data Out operation from a standard Read or Fast Page
Read.
A memory cycle is terminated by returning both RAS and
high. Memory cell data will retain its correct state by
CAS
maintaining power and accessing all 2048(2K)
combinations of the 11-bit(2K) row addresses, regardless
of sequence, at least once every 32ms through any RAS
cycle (Read, Write) or RAS Refresh cycle (RAS -only,
,
CBR, or Hidden). The CBR Refresh cycle automatically
controls the row addresses by invoking the refresh counter
and controller.
Power-On
The initial application of the VCC supply requires a 200 µs
wait followed by a minimum of any eight initialization cycles
containing a RAS clock. During Power-On, the VCC
current is dependent on the input levels of RAS and
It is recommended that RAS and
be held at a valid VIH during Power-On to avoid current
surges.
CAS
CAS
track with VCC or
.
PRELIMINARY (June, 2002, Version 0.3) 2 AMIC Technology, Inc.
Page 4
A42L2604 Series
Block Diagram
RAS
CAS
WE
Control
Clocks
VBB Generator
Vcc
Vss
Row Decoder
Memory Array
4,194,304 X 4
Cells
Column Decoder
Data in
Buffer
Data out
Buffer
Sense Amps & I/O
OE
A0~A10
A0~A10
Refresh Timer
Refresh control
Refresh Counter
Row Address Buffer
Col. Address Buffer
Recommended Operating Conditions (Ta = 0°C to +70°C or -40°C to +85°C)
Symbol Description Min. Typ. Max. Unit
VCC Power Supply 3.0 3.3 3.6 V
I/O0
to
I/O3
VSS Input High Voltage 0 0 0 V
VIH Input High Voltage 2.0 - VCC + 0.3 V
VIL Input Low Voltage -0.5 - 0.8 V
PRELIMINARY (June, 2002, Version 0.3) 3 AMIC Technology, Inc.
Page 5
A42L2604 Series
Truth Table
Function
Standby H H X X X High-Z
Read: Word L L H L Row/Col. Data Out
Read L L H L Row/Col. Data Out
Write: Word (Early) L L L X Row/Col. Data In
Write (Early) L L L X Row/Col. Data In
Read-Write L L
EDO-Page-Mode Read: Hi-Z
-First cycle
-Subsequent Cycles
EDO-Page-Mode Write (Early)
-First cycle
-Subsequent Cycles
EDO-Page-Mode Read-Write
-First cycle
-Subsequent Cycles
Hidden Refresh Read
Hidden Refresh Write
RAS-Only Refresh
CBR Refresh
Self Refresh
RAS
L
L
L
L
L
L
L→H→L
L→H→L
L H X X Row High-Z
H→L
H→L
CAS
H→L
H→L
H→L
H→L
H→L
H→L
L H L Row/Col. Data Out
L L X Row/Col.
L X X X High-Z
L H X X High-Z
WE OE
H→L L→H
H
H
L
L
H→L
H→L
H→L
H→L
X
X
L→H
L→H
Address I/Os
Row/Col.
Row/Col.
Col.
Row/Col.
Col.
Row/Col.
Col.
Data Out → Data In
Data Out
Data Out
Data In
Data In
Data Out → Data In
Data Out → Data In
Data In → High-Z
PRELIMINARY (June, 2002, Version 0.3) 4 AMIC Technology, Inc.
Page 6
A42L2604 Series
Absolute Maximum Ratings*
Input Voltage (Vin) . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V
Output Voltage (Vout) . . . . . . . . . . . . . . . . -0.5V to +4.6V
Power Supply Voltage (VCC) . . . . . . . . . . . -0.5V to +4.6V
Operating Temperature (TOPR) . . . . . . . . . . 0°C to +70°C
Storage Temperature (TSTG) . . . . . . . . . -55°C to +150°C
Soldering Temperature X Time (TSOLDER) . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C X 10sec
Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . 1W
Short Circuit Output Current (Iout) . . . . . . . . . . . . . 50mA
Latch-up Current . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended
periods may affect device reliability.
DC Electrical Characteristics (VCC = 3.3V ± 0.3V, VSS = 0V, Ta = 0°C to +70°C or -40°C to +85°C)
Symbol Parameter
IIL Input Leakage Current -5 +5 -5 +5
IOL Output Leakage Current -5 +5 -5 +5
ICC1 Operating Power Supply
Current
-45 -50
Min. Max. Min. Max.
- 80 - 75 mA
Unit Test Conditions Notes
µA 0V ≤ Vin ≤ Vin + 0.3V
Pins not under
Test = 0V
DOUT disabled,
µA
0V ≤ Vout ≤ + VCC
RAS,
UCAS,LCAS
Address cycling; tRC = min.
and
1, 2
ICC2 TTL Standby Power
Supply Current
ICC3 Average Power
Supply Current,
RAS Refresh Mode
ICC4 EDO Page Mode
Average Power
Supply Current
ICC5
ICC6 CMOS Standby Power
ICC7 Self Refresh Mode
VOH 2.4 - 2.4 - V IOUT = -2.0mA
VOL
CAS-before-RAS
Refresh Power
Supply Current
Supply Current
Current
Output Voltage
- 1.5 - 1.5 mA
- 80 - 75 mA
- 80 - 75 mA
- 80 - 75 mA
- 1.0 - 1.0 mA
- 350 - 350
- 0.4 - 0.4 V IOUT =2.0mA
RAS=
UCAS=LCAS
RAS and Address cycling,
UCAS=LCAS
tRC = min.
RAS = VIL,
UCAS,LCAS
cycling; tPC = min.
RAS,
cycling; tRC = min.
RAS=
VCC - 0.2V
µA
RAS=
All other input high levels are
VCC-0.2V or input low levels
are VSS +0.2V
and
UCAS
UCAS=LCAS
≤VSS+0.2V
CAS
=VIH
= VIH,
and Address
LCAS
=
1, 2
1
1
PRELIMINARY (June, 2002, Version 0.3) 5 AMIC Technology, Inc.
Page 7
A42L2604 Series
AC Characteristics (VCC = 3.3V ± 0.3V, VSS = 0V, Ta = 0°C to +70°C or -40°C to +85°C)
Test Conditions:
Input timing reference level: VIH/VIL=2.0V/0.8V
Output reference level: VOH/VOL=2.0V/0.8V
Output Load: 2TTL gate + CL (50pF)
Assumed tT=2ns
Std
#
Symbol
tT Transition Time (Rise or Fall) 1 50 1 50 ns 4, 5
1 tRC Random Read or Write Cycle Time 76 - 84 - ns
2 tRP
3 tRAS
4 tCAS
5 tRCD
6 tRAD
7 tRSH
8 tCSH
9 tCRP
10 tASR Row Address Setup Time 0 - 0 - ns
11 tRAH Row Address Hold Time 7 - 8 - ns
RAS Precharge Time
RAS Pulse Width
CAS Pulse Width
RAS to CAS Delay Time
RAS to Column Address Delay Time
CAS to RAS Hold Time
CAS Hold Time
CAS to RAS Precharge Time
Parameter
-45 -50
Min. Max. Min. Max.
27 - 30 - ns
45 10K 50 10K ns
7 10K 8 10K ns
10 33 11 37 ns 6
8 25 9 28 ns 7
7 - 8 - ns
35 - 37 - ns
5 - 5 - ns
Unit Notes
12 tCLZ
13 tRAC
14 tCAC
15 tAA Access Time from Column Address - 20 - 22 ns 7, 12
16 tOEA
17 tAR
18 tRCS Read Command Setup Time 0 - 0 - ns
19 tRCH Read Command Hold Time 0 - 0 - ns 9
CAS to Output in Low Z
Access Time from RAS
Access Time from CAS
Access Time from OE
Column Address Hold Time from RAS
3 - 3 - ns 8
- 45 - 50 ns 6,7
- 12 - 13 ns 6, 12
- 12 - 13 ns
40 - 45 - ns
PRELIMINARY (June, 2002, Version 0.3) 6 AMIC Technology, Inc.
Page 8
A42L2604 Series
AC Characteristics (continued) (VCC = 3.3V ± 0.3V, VSS = 0V, Ta = 0°C to +70°C or -40°C to +85°C)
Test Conditions:
Input timing reference level: VIH/VIL=2.0V/0.8V
Output reference level: VOH/VOL=2.0V/0.8V
Output Load: 2TTL gate + CL (50pF)
Assumed tT=2ns
Std
#
Symbol
20 tRRH
21 tRAL
22 TCOH
23 tOFF Output Buffer Turn-Off Delay Time - 2 - 3 ns 8, 10
24 tASC Column Address Setup Time 0 - 0 - ns
25 tCAH Column Address Hold Time 7 - 8 - ns
26 tOES
27 tWCS Write Command Setup Time 0 - 0 - ns 11
28 tWCH Write Command Hold Time 7 - 8 - ns 11
29 tWCR
30 tWP Write Command Pulse Width 7 - 8 - ns
31 tRWL
Read Command Hold Time Reference to RAS
Column Address to RAS Lead Time
Output Hold After CAS Low
Low to CAS High Set Up
OE
Write Command Hold Time to RAS
Write Command to RAS Lead Time
Parameter
-45 -50
Min. Max. Min. Max.
0 - 0 - ns 9
20 - 22 - ns
2 - 3 - ns
10 - 10 - ns
40 - 45 - ns
12 - 13 - ns
Unit Notes
32 tCWL
33 tDS Data-in setup Time 0 - 0 - ns
34 tDH Data-in Hold Time 7 - 8 - ns
35 tDHR
36 tRWC Read-Modify-Write Cycle Time 104 - 114 - ns
37 tRWD
38 tCWD
39 tAWD
PRELIMINARY (June, 2002, Version 0.3) 7 AMIC Technology, Inc.
Write Command to CAS Lead Time
Data-in Hold Time to RAS
RAS to WE Delay Time (Read-Modify-Write)
CAS to WE Delay Time (Read-Modify-Write)
Column Address to WE Delay Time
(Read-Modify-Write)
7 - 8 - ns
40 - 45 - ns
59 - 65 - ns 11
26 - 28 - ns 11
34 - 37 - ns 11
Page 9
A42L2604 Series
AC Characteristics (continued) (VCC = 3.3V ± 0.3V, VSS = 0V, Ta = 0°C to +70°C or -40°C to +85°C)
Test Conditions:
Input timing reference level: VIH/VIL=2.0V/0.8V
Output reference level: VOH/VOL=2.0V/0.8V
Output Load: 2TTL gate + CL (50pF)
Assumed tT=2ns
Std
#
Symbol
40 tOEH
41 tOEP
42 tPC Read or Write Cycle Time (EDO Page) 18 - 20 - ns 13
43 tCPA
44 tCP
45 tPCM EDO Page Mode RMW Cycle Time 46 - 50 - ns
46 tCRW
47 tRASP
48 tCSR
49 tCHR
50 tRPC
OE Hold Time from WE
OE High Pulse Width
Access Time from CAS Precharge
(EDO Page)
CAS Precharge Time
EDO Page Mode CAS Pulse Width
(RMW)
RAS Pulse Width (EDO Page)
CAS Setup Time (CAS -before-RAS)
CAS Hold Time (CAS -before-RAS)
RAS to CAS Precharge Time
Parameter
-45 -50
Min. Max. Min. Max.
7 - 8 - ns
5 - 5 - ns
- 21 - 23 ns 12
7 - 8 - ns
35 - 38 - ns
45 200K 50 200K ns
5 - 5 - ns 3
10 - 10 - ns 3
10 - 10 - ns
Unit Notes
51 tOEZ
52 tRASS
53 tRPS
54 tCHS
PRELIMINARY (June, 2002, Version 0.3) 8 AMIC Technology, Inc.
Output Buffer Turn-off Delay from OE
RAS pulse width (C-B-Rself refresh)
RAS precharge time (C-B-Rself refresh)
CAShold time (C-B-Rself refresh)
- 2 - 3 ns 8
100 - 100 -
76 - 84 - ns
-50 - -50 - ns
µs
Page 10
A42L2604 Series
Notes:
1. ICC1, ICC3, ICC4, and ICC5 depend on cycle rate.
2. ICC1 and ICC4 depend on output loading. Specified values are obtained with the outputs open.
3. An initial pause of 200µs is required after power-up followed by any 8 RAS cycles before proper device operation is
achieved. In the case of an internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8
RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks.
4. AC Characteristics assume tT = 2ns. All AC parameters are measured with a load equivalent to two TTL loads and
50pF, VIL (min.) ≥ GND and VIH (max.) ≤ VCC.
5. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are measured
between VIH and VIL.
6. Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference
point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled exclusively by tCAC.
7. Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference
point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled exclusively by tAA.
8. Assumes three state test load (5pF and a 500Ω Thevenin equivalent).
9. Either tRCH or tRRH must be satisfied for a read cycle.
10. tOFF (max.) defines the time at which the output achieves the open circuit condition; it is not referenced to output
voltage levels.
11. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet
as electrical characteristics only. If tWCS ≥ tWCS (min.) and tWCH ≥ tWCH (min.), the cycle is an early write cycle
and data-out pins will remain open circuit, high impedance, throughout the entire cycle. If tRWD ≥ tRWD (min.) , tCWD ≥
tCWD (min.) and tAWD ≥ tAWD (min.), the cycle is a read-modify-write cycle and the data out will contain data read from
the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is
indeterminate.
12. Access time is determined by the longer of tAA or tCAC or tCPA.
13. tASC ≥ tCP to achieve tPC (min.) and tCPA (max.) values.
PRELIMINARY (June, 2002, Version 0.3) 9 AMIC Technology, Inc.
Page 11
A42L2604 Series
Word Read Cycle
RAS
CAS
t
CRP(9)
t
ASR(10)
t
RAH(11)
t
RAD(6)
t
RCD(5)
t
t
CSH(8)
t
ASC(24)
RAS(3)
t
RC(1)
t
RAL(21)
t
CAH(25)
t
RSH(7)
t
CAS(4)
t
RP(2)
t
CRP(9)
Address
WE
OE
I/O0 ~
I/O
Row Address Column Address
t
AR(17)
t
t
RCS(18)
RAC(13)
t
AA(15)
t
CAC(14)
t
OEA(16)
t
t
OEZ(51)
t
RCH(19)
t
RRH(20)
OFF(23)
High-Z
3
t
CLZ(12)
Valid Data-out
: High or Low
PRELIMINARY (June, 2002, Version 0.3) 10 AMIC Technology, Inc.
Page 12
A42L2604 Series
Word Write Cycle (Early Write)
t
RC(1)
t
RAS
CAS
t
CRP(9)
t
ASR(10)
t
RAH(11)
t
RAD(6)
t
RCD(5)
t
t
ASC(24)
AR(17)
t
CSH(8)
RAS(3)
t
CAH(25)
t
CAS(4)
t
RAL(21)
t
RSH(7)
t
RP(2)
t
CRP(9)
Address
WE
OE
I/O0 ~
I/O
3
Row Address Column Address
t
WCR(29)
t
CWL(32)
t
t
WP(30)
t
WCS(27)
t
DHR(35)
t
DS(33)
t
Valid Data-in
RWL(31)
t
WCH(28)
DH(34)
: High or Low
PRELIMINARY (June, 2002, Version 0.3) 11 AMIC Technology, Inc.
Page 13
A42L2604 Series
Word Write Cycle (Late Write)
t
RC(1)
t
RAS
CAS
t
CRP(9)
t
ASR(10)
t
RAH(11)
t
RAD(6)
t
RCD(5)
t
AR(17)
t
ASC(24)
t
CSH(8)
RAS(3)
t
CAH(25)
t
CAS(4)
t
RAL(21)
t
RSH(7)
t
RP(2)
t
CRP(9)
Address
WE
OE
I/O0 ~
I/O
3
Row Address Column Address
t
WCR(29)
t
t
DHR(35)
t
DS(33)
High-Z
Vaild Data-in
t
CWL(32)
OEH(40)
t
DH(34)
t
RWL(31)
t
WP(30)
: High or Low
PRELIMINARY (June, 2002, Version 0.3) 12 AMIC Technology, Inc.
Page 14
A42L2604 Series
Word Read-Modify-Write Cycle
t
RWC(36)
t
RAS
CAS
t
CRP(9)
t
ASR(10)
Row Address Column AddressAddress
t
RAH(11)
t
RAD(6)
t
RCD(5)
t
AR(17)
t
ASC(24)
t
CAH(25)
t
CSH(8)
RAS(3)
t
RSH(7)
t
RP(2)
t
CRP(9)
WE
OE
I/O0 ~
I/O
t
t
RCS(18)
t
RAC(13)
t
CAC(14)
t
AA(15)
t
RWD(37)
t
OEA(16)
AWD(39)
t
CWD38)
t
OEZ(51)
t
t
CWL(32)
t
RWL(31)
t
WP(30)
t
OEH(40)
DS(33)tDH(34)
High-Z
3
t
CLZ(12)
Data-out Data-in
: High or Low
PRELIMINARY (June, 2002, Version 0.3) 13 AMIC Technology, Inc.
Page 15
A42L2604 Series
EDO Page Mode Word Read Cycle
t
RAS
CAS
t
CRP(9)
t
ASR(10)tRAH(11)
t
RAD(6)
t
RCD(5)
t
AR(16)
t
CSH(8)
t
CSH(8)
t
ASC(24)
t
CAS(4)
RASP(47)
t
CP(44)
t
CAS(4)
t
t
PC(42)
CAH(25)
t
t
CAS(4)
t
RAL(21)
t
ASC(24)
RSH(7)
t
CAH(25)
t
RP(2)
t
CRP(9)
Address
WE
OE
I/O0 ~
I/O
Row Column Column Column
t
t
RCS(18)
t
RAC(13)
t
AA(15)
t
CAC(14)
CAH(25)
t
OES(26)
t
CLZ(12)
t
OEA(16)
t
RCH(25)
t
CPA(43)
t
t
RCS(18)
CAC(14)
t
COH(22)
t
OEP(41)
t
AA(15)
t
OEZ(51)
t
RCS(18)
t
OEA(16)
t
CAC(14)
t
t
RRH(20)
t
OFF(23)
t
OEZ(51)
RCH(19)
Data-out Data-out Data-out
3
t
CLZ(12)
: High or Low
PRELIMINARY (June, 2002, Version 0.3) 14 AMIC Technology, Inc.
Page 16
A42L2604 Series
EDO Page Mode Early Word Write Cycle
t
RASP(47)
RAS
t
CAS
t
CRP(9)
t
ASR(10)
t
RAH(11)
t
t
RAD(6)
t
ASC(24)
RCD(5)
CSH(8)
t
CAS(4)
t
CAH(25)
t
ASC(24)
t
CP(44)
t
CAS(4)
t
PC(42)
t
CAH(25)
t
ASC(24)
t
CP(44)
t
RSH(7)
t
CAS(4)
t
RAL(21)
t
CAH(25)
t
RP(2)
t
CRP(9)
WE
OE
I/O0 ~
I/O
Row Column ColumnAddress
t
CWL(32)
t
WCS(27)
t
WP(30)
t
DS(33)
3
Data-in Data-in Data-in
t
WCS(27)
t
WCH(28)
t
DH(34)
t
DS(33)
Column
t
CWL(32)
t
WP(30)
t
t
WCH(28)
t
DH(34)
WCS(27)
t
DS(33)
t
WP(30)
t
CWL(32)
t
RWL(31)
t
DH(34)
t
WCH(28)
: High or Low
PRELIMINARY (June, 2002, Version 0.3) 15 AMIC Technology, Inc.
Page 17
A42L2604 Series
EDO Page Mode Word Read-Modify-Write Cycle
RAS
CAS
t
CRP(9)
t
ASR(10)
t
t
RAH(11)
t
RAD(6)
RCD(5)
t
CSH(8)
t
CRW(46)
t
ASC(24)
t
CAH(25)
t
CP(44)
t
RASP(47)
t
CRW(46)
t
CAH(25)
t
ASC(24)
t
PCM(45)
t
CP(44)
t
CRW(46)
t
RAL(21)
t
ASC(24)
t
RSH(7)
t
CAH(25)
t
RP(2)
t
CRP(9)
Address
WE
OE
I/O0 ~
I/O
Row Column Column Column
t
t
RCS(18)
t
RAC(13)
t
RWD(37)
t
t
AA(15)
t
CWD(38)
AWD(39)
t
OEA(16)
t
CAC(14)
t
OEZ(51)
t
OEH(40)
t
DS(33)
CWL(32)
t
WP(30)
t
CPA(43)
t
AA(15)
t
DH(34)
t
CWD(38)
t
AWD(39)
t
OEA(16)
t
OEZ(51)
t
DS(33)
t
CWL(32)
t
t
CPA(43)
t
t
DH(34)
WP(30)
t
AA(15)
t
CWD(38)
AWD(39)
t
OEA(16)
t
OEZ(51)
t
DS(33)
t
CWL(32)
t
RWL(31)
t
WP(30)
t
DH(34)
High-Z
3
t
CLZ(12)
Data-out
t
CLZ(12)
Data-in
Data-out
t
CLZ(12)
Data-in
Data-in
Data-out
: High or Low
PRELIMINARY (June, 2002, Version 0.3) 16 AMIC Technology, Inc.
Page 18
A42L2604 Series
RAS Only Refresh Cycle
t
RC(1)
t
RAS
CAS
t
ASR(10)
t
CRP(9)
t
RAH(11)
RAS(3)
t
RPC(50)
t
RP(2)
Address
Row
Note: WE, OE = Don't care.
CAS Before RAS Refresh Cycle
t
RP(2)
RAS
t
RPC(50)
t
PC(44)
CAS
t
OFF(23)
I/O0 ~
I/O
3
t
CSR(48)
t
CHR(49)
t
RAS(3)
High-Z
t
RC(1)
t
RP(2)
: High or Low
: High or LowNote: WE, OE, Address = Don't care.
PRELIMINARY (June, 2002, Version 0.3) 17 AMIC Technology, Inc.
Page 19
A42L2604 Series
Hidden Refresh Cycle (Word Read)
tRC(1)
tRC(1)
RAS
UCAS
LCAS
A0~A8
WE
tAR(17)
tCRP(9)
tASR(10)
tRCD(5)
tRAD(6)
tRAH(11)
tASC(24)
Row Column
tRAS(3) tRP(2)
tRSH(7)
tRAL(21)
tCAH(25)
tAA(15)
tOEA(16)
tRAS(3) tRP(2)
tCHR(49)
tRRH(20)tRCS(18)
tOEZ(51)
tCRP(9)
OE
I/O0 ~
I/O
15
tCAC(14)
tCLZ(12)
tRAC(13)
High-Z
Valid Data-out
tOFF(23)
: High or Low
PRELIMINARY (June, 2002, Version 0.3) 18 AMIC Technology, Inc.
Page 20
A42L2604 Series
Hidden Refresh Cycle (Early Word Write)
RAS
Address
WE
t
AR(17)
t
CRP(9)
t
ASR(10)
t
RAD(6)
t
RAH(11)
t
t
RCD(5)
ASC(24)
Row Column
t
WCS(27)
t
RAS(3)
t
RC(1)
t
RAL(21)
t
CAH(25)
t
WP(30)
t
RSH(7)
t
WCH(28)
t
RP(2)
t
t
CHR(49)
RAS(3)
t
RC(1)
t
CRP(9)
t
RP(2)
OE
t
DS(33)
0
~
3
Valid Data-in
t
DH(34)
: High or Low
PRELIMINARY (June, 2002, Version 0.3) 19 AMIC Technology, Inc.
Page 21
A42L2604 Series
EDO Page Mode Read-Early-Write Cycle (Pseudo Read-Modify-Write)
t
RASP(47)
RAS
t
CSH(8)
t
t
t
RAL(21)
t
CAH(25)
RSH(7)
CAS(4)
CAS
t
CRP(9)
t
ASR(10)
t
RAH(11)
t
RAD(6)
t
RCD(5)
t
ASC(24)
t
CAS(4)
t
PC(42)
t
CAH(25)
t
CP(44)
t
ASC(24)
t
CAS(4)
t
CAH(25)
t
PC(42)
t
CP(44)
t
ASC(24)
t
RP(2)
t
CPR(9)
Address
WE
OE
I/O0 ~
I/O
Row Column Column
t
RCH(19)
t
RCS(18)
t
AA(15)
t
AA(15)
t
RAC(13)
t
CAC(14)
t
OEA(16)
3
t
CAP(43)
t
CAC(14)
t
COH(22)
Data-out Data-out Data-in
t
WCS(27)
t
DS(33)
Column
t
WCH(28)
t
DH(34)
: High or Low
PRELIMINARY (June, 2002, Version 0.3) 20 AMIC Technology, Inc.
Page 22
A42L2604 Series
Self Refresh Mode
RAS
UCAS
LCAS
t
RPC(50)
t
RP(2)
t
CP(44)
t
CSR(48)
t
RASS(52)
t
CHS(54)
t
RPS(53)
t
CRP(9)
t
ASR(10)
A0 ~ A10
t
OFF(23)
I/O0 ~ I/O
3
Note: WE, OE = Don't care.
n Self Refresh Mode.
a. Entering the Self Refresh Mode:
The A42L2604 Self Refresh Mode is entered by using CAS before RAScycle and holding RAS and CAS signal “low”
longer than 100µs.
b. Continuing the Self Refresh Mode:
The Self Refresh Mode is continued by holding RAS “low” after entering the Self Refresh Mode.
It does not depend on CAS being “high” or “low” after entering the Self Refresh Mode continue the Self Refresh Mode.
c. Exiting the Self Refresh Mode:
The A42L2604 exits the Self Refresh Mode when the RAS signal is brought “high”.
ROW COL
High-Z
: High or Low
PRELIMINARY (June, 2002, Version 0.3) 21 AMIC Technology, Inc.
Page 23
A42L2604 Series
RAS
Capacitance
Symbol Signals Parameter Max. Unit Test Conditions
CIN1 A0 – A10 5 pF Vin = 0V
CIN2
CI/O I/O0 - I/O3 I/O Capacitance 7 pF Vin = Vout = 0V
(f = 1MHz, Ta = Room Temperature, VCC = 3.3V ± 10%)
RAS,
CAS
WE, OE
,
Input Capacitance 7 pF Vin = 0V
Ordering Codes
Package
SOJ 24/26L (300mil) A42L2604S-45 A42L2604S-50 2K Yes
TSOP 24/26L type II (300mil) A42L2604V-45 A42L2604V-50 2K Yes
TSOP 24/26L type II (300mil) A42L2604V-45U A42L2604V-50U 2K Yes
Note: -U is for industrial operating temperature range.
Access Time
45ns 50ns Refresh Cycle Self-Refresh
PRELIMINARY (June, 2002, Version 0.3) 22 AMIC Technology, Inc.
Page 24
A42L2604 Series
Package Information
SOJ 24/26L (300mil) Outline Dimensions unit: inches/mm
D
19 18
1324
1
E
E
1 6 7
Pin 1 Identifier
- y S
Seating Plane 0.004
b
b
2
12
2
A
e
y
A
A1
E2
A
C
A
θ
Symbol
A - - 0.140 - - 3.56
A1 0.070 0.080 0.090 1.78 2.03 2.29
A2 0.095 0.100 0.105 2.41 2.54 2.67
b 0.016 0.018 0.022 0.41 0.46 0.56
b2 0.026 0.028 0.032 0.66 0.71 0.81
C 0.008 0.010 0.014 0.20 0.25 0.36
D - 0.675 0.686 - 17.15 17.42
E 0.327 0.337 0.347 8.31 8.56 8.81
E1
E2
e 0.044 0.050 0.056 1.12 1.27 1.42
S - - 0.048 - - 1.22
θ 0°
Dimensions in inches Dimensions in mm
Min Nom Max Min Nom Max
0.295 0.300 0.305 7.49 7.62 7.75
0.245 0.265 0.285 6.22 6.73 7.24
-
10° 0°
-
10°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E1 does not include resin fins.
3. Dimension E2 is for PC Board surface mount pad pitch design
reference only.
4. Dimension S includes end flash.
PRELIMINARY (June, 2002, Version 0.3) 23 AMIC Technology, Inc.
Page 25
A42L2604 Series
Dimensions in inches
Dimensions in mm
Package Information
TSOP 24/26L (TYPE II) (300mil) Outline Dimensions unit: inches/mm
24
D
S B
e
13
E
E
H
121
2A
A
A
1
y
D
0.010
θ
L1
L1 L
c
Symbol
A - - 0.047 - - 1.20
A1 0.002 - - 0.05 - A2 0.037 0.039 0.041 0.95 1.00 1.05
B 0.012 0.016 0.020 0.30 0.40 0.50
c - 0.005 - - 0.127 D 0.671 0.675 0.679 17.04 17.14 17.24
E 0.298 0.300 0.302 7.57 7.62 7.67
e - 0.050 - - 1.27 -
HE 0.355 0.363 0.371 9.02 9.22 9.42
L - 0.031 - - 0.80 -
L1 0.016 0.020 0.024 0.40 0.50 0.60
S - 0.037 - - 0.95 -
y - - 0.004 - - 0.10
θ 0°
Min Nom Max Min Nom Max
-
5° 0°
-
5°
3. Dimension S includes end flash.
PRELIMINARY (June, 2002, Version 0.3) 24 AMIC Technology, Inc.
Notes:
1. Dimension D&E do not included interlead flash.
2. Dimension B does not included dambar protrusion / intrusion.
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