Page 1
A428316 Series
Preliminary 256K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Document Title
256K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Revision History
Rev. No. History Issue Date Remark
0.0 Initial issue June 13, 2001 Preliminary
0.1 Modify AC data April 26, 2002
0.2 Modify DC data and all parts guarantee self-refresh mode June 10, 2002
0.3 Delete -30,-40 grade and add -25 grade August 20, 2002
PRELIMINARY (August, 2002, Version 0.3) AMIC Technology, Inc.
Page 2
A428316 Series
Preliminary 256K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Features
n Organization: 262,144 words X 16 bits
n Part Identification
- A428316 (512 Ref.)
n Single 5.0V power supply/built-in VBB generator
n Low power consumption
- Operating: 110mA (-25 max)
- Standby: 2.5mA (TTL), 1.0mA (CMOS)
1.0mA (Self-refresh current)
n High speed
- 25/35 ns RAS access time
- 12/17 ns column address access time
- 8/10 ns CAS access time
- 12/16 ns EDO Page Mode Cycle Time
General Description
The A428316 is a new generation randomly accessed
memory for graphics, organized in a 262,144-word by 16bit configuration. This product can execute Byte Write
and Byte Read operation via two
CAS
pins.
The A428316 offers an accelerated Fast Page Mode
Pin Configuration
nnSOJ nn TSOP
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
VCC
40
1
2
3
4
5
6
7
A428316S
8
9
10
11
12
13
14
15
A0
16
A1
17
A2
18
19
A3
20
VSS
39
I/O15
I/O14
38
37
I/O13
36
I/O12
35
VSS
34
I/O11
33
I/O10
32
I/O9
31
I/O8
30
NC
LCAS
29
UCAS
28
OE
27
26
A8
25
A7
A6
24
23
A5
A4
22
21
VSS
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
VCC
1
2
3
4
5
6
7
A428316V
8
9
10
13
14
15
16
17
A0
18
A1
19
A2
20
21
A3
22
VSS
44
43
I/O15
I/O14
42
41
I/O13
40
I/O12
39
VSS
38
I/O11
37
I/O10
36
I/O9
35
I/O8
32
NC
31
LCAS
30
UCAS
29
OE
28
A8
27
A7
A6
26
25
A5
A4
24
VSS
23
n Industrial operating temperature range: -40°C to 85°C
for -U
n Fast Page Mode with Extended Data Out
n Separate
CAS
(
UCAS
,
LCAS
) for byte selection
n 512 Refresh Cycle in 8ms
n Read-modify-write, RAS -only, CAS -before- RAS ,
Hidden refresh capability
n TTL-compatible, three-state I/O
n JEDEC standard packages
- 400mil, 40-pin SOJ
- 400mil, 40/44 TSOP type II package
This allow random access of up to 512 words within a row
at a 83/62 MHz EDO cycle, making the A428316 ideally
suited for graphics, digital signal processing and high
performance computing systems.
Pin Descriptions
Symbol Description
A0 – A8 Address Inputs
I/O0 - I/O15 Data Input/Output
RAS
LCAS
UCAS
WE
OE
VCC 5.0V Power Supply
VSS Ground
NC No Connection
Row Address Strobe
Column Address Strobe for Lower Byte
(I/O0 – I/O7)
Column Address Strobe for Upper Byte
(I/O8 – I/O15)
Write Enable
Output Enable
cycle with a feature called Extended Data Out (EDO).
PRELIMINARY (August, 2002, Version 0.3) 1 AMIC Technology, Inc.
Page 3
A428316 Series
Selection Guide
Symbol Description -25 -35 Unit
tRAC
tAA Maximum Column Address Access Time 12 17 ns
tCAC
tOEA
tRC Minimum Read or Write Cycle Time 44 62 ns
tPC Minimum EDO Cycle Time 12 16 ns
Maximum RAS Access Time
Maximum CAS Access Time
Maximum Output Enable (OE) Access Time
25 35 ns
8 10 ns
8 10 ns
Functional Description
The A428316 reads and writes data by multiplexing an 18bit address into a 9-bit row and 9-bit column address.
and
RAS
column address, respectively.
The A428316 has two
I/O7, and
function in an identical manner to
generate an internal
timing are determined by the first
LCAS
Byte Read and Byte Write are controlled by using
and
UCAS
A Read cycle is performed by holding the WE signal high
during RAS/
holding the WE signal low during RAS /
the input data is latched by the falling edge of WE or
, whichever occurs later. The data inputs and outputs
CAS
are routed through 16 common I/O pins, with RAS,
WE and OE controlling the in direction.
EDO Page Mode operation all 512 columns within a
selected row to be randomly accessed at a high data rate.
A EDO Page Mode cycle is initiated with a row address
latched by RAS followed by a column address latched by
. While holding RAS low,
CAS
strobe changing column addresses, thus achieving shorter
cycle times.
are used to strobe the row address and the
CAS
inputs:
CAS
UCAS
) to transition low and by the last to transition high.
controls I/O8 - I/O15,
signal. The
CAS
LCAS
CAS
controls I/O0-
UCAS
and
LCAS
in that either will
function and
CAS
(
CAS
UCAS
or
LCAS
separately.
operation. A Write cycle is executed by
CAS
operation;
CAS
CAS
can be toggled to
CAS
The A428316 offers an accelerated Fast Page Mode cycle
through a feature called Extended Data Out, which keeps
the output drivers on during the
Since data can be output after
not required to wait for valid data to appear before starting
the next access cycle. Data-out will remain valid as long as
RAS and OE are low, and WE is high; this is the only
characteristic which differentiates Extended Data Out
operation from a standard Read or Fast Page Read.
A memory cycle is terminated by returning both RAS and
high. Memory cell data will retain its correct state by
CAS
maintaining power and accessing all 512 combinations of
the 9-bit row addresses, regardless of sequence, at least
once every 8ms through any RAS cycle (Read, Write) or
RAS Refresh cycle (RAS-only, CBR, or Hidden). The CBR
Refresh cycle automatically controls the row addresses by
invoking the refresh counter and controller.
precharge time (tcp).
CAS
goes high, the user is
CAS
Power-On
The initial application of the VCC supply requires a 200 µs
,
wait followed by a minimum of any eight initialization cycles
containing a RAS clock. During Power-On, the VCC
current is dependent on the input levels of RAS and
It is recommended that RAS and
be held at a valid VIH during Power-On to avoid current
surges.
track with VCC or
CAS
CAS
.
PRELIMINARY (August, 2002, Version 0.3) 2 AMIC Technology, Inc.
Page 4
A428316 Series
Block Diagram
OE
UCAS
LCAS
A0 - A8
RAS
WE
CAS Clock
Generator
Column
Address
Buffers
Refresh
Counter &
Controller
Row
Address
Buffers
RAS Clock
Generator
AY0 - AY8
AX0 - AX8
WE Clock
Generator
ROW DECODER
512
.
.
.
.
.
.
Generator
Column Decoders
Sense Amplifiers
. .
Memory Array
512 x 512 x 16
512 x 16
. .
OE Clock
Data I/O
Buffers
I/O
to
I/O
VCC
VSS
0
15
Recommended Operating Conditions (Ta = 0°C to +70°C or -40°C to +85°C)
Symbol Description Min. Typ. Max. Unit Notes
VCC Power Supply 4.5 5.0 5.5 V 1
VSS Input High Voltage 0.0 0.0 0.0 V 1
VIH Input High Voltage 2.4 - VCC + 1.0 V 1
VIL Input Low Voltage -0.5 - 0.8 V 1
PRELIMINARY (August, 2002, Version 0.3) 3 AMIC Technology, Inc.
Page 5
A428316 Series
Truth Table
Function
Standby H H H X X X High-Z
Read: Word L L L H L Row/Col. Data Out
Read: Lower Byte L H L H L Row/Col. I/O0-7 = Data Out
Read: Upper Byte L L H H L Row/Col. I/O0-7 = High-Z
Write: Word L L L L H Row/Col. Data In
Write: Lower Byte L H L L H Row/Col. I/O0-7 = Data In
Write: Upper Byte L L H L H Row/Col. I/O0-7 = X
Read-Write L L L
EDO-Page-Mode Read: Hi-Z
-First cycle
-Subsequent Cycles
EDO-Page-Mode Write
-First cycle
-Subsequent Cycles
EDO-Page-Mode Read-Write
-First cycle
-Subsequent Cycles
Hidden Refresh Read
Hidden Refresh Write
RAS-Only Refresh
CBR Refresh
Self Refresh
Note: 1. Byte Write may be executed with either
2. Byte Read may be executed with either
3. Only one
CAS
L→H→L
L→H→L
signal (
RAS
L
L
L
L
L
L
L H H X X Row High-Z
H→L
H→L
UCAS
H→L
H→L
H→L
H→L
H→L
H→L
L L H L Row/Col. Data Out 2
L L L X Row/Col.
L L X X X High-Z 3
L L H X X High-Z
UCAS
UCAS
UCAS
or
LCAS
LCAS
H→L
H→L
H→L
H→L
H→L
H→L
) must be active.
WE OE
H→L L→H
H
H
L
L
H→L
H→L
or
LCAS
or
LCAS
H→L
H→L
H
H
L→H
L→H
active.
active.
Address I/Os Notes
I/O8-15 = High-Z
I/O8-15 = Data Out
I/O8-15 = X
I/O8-15 = Data In
Row/Col.
Row/Col.
Col.
Row/Col.
Col.
Row/Col.
Col.
Data Out → Data In
Data Out
Data Out
Data In
Data In
Data Out → Data In
Data Out → Data In
Data In → High-Z
1,2
2
2
1
1
1, 2
1, 2
1
PRELIMINARY (August, 2002, Version 0.3) 4 AMIC Technology, Inc.
Page 6
A428316 Series
Absolute Maximum Ratings*
Input Voltage (Vin) . . . . . . . . . . . . . . . . . . . . -1.0V to +7.0V
Output Voltage (Vout) . . . . . . . . . . . . . . . . . -1.0V to +7.0V
Power Supply Voltage (VCC) . . . . . . . . . . . -1.0V to +7.0V
Operating Temperature (TOPR) . . . . . . . . . . . . 0°C to +70°C
Storage Temperature (TSTG) . . . . . . . . . . . -55°C to +150°C
Soldering Temperature X Time (TSOLDER) . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C X 10sec
Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
Short Circuit Output Current (Iout) . . . . . . . . . . . . . . . 50mA
Latch-up Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended
periods may affect device reliability.
DC Electrical Characteristics (VCC = 5.0V ± 10%, VSS = 0V, Ta = 0°C to +70°C or -40°C to +85°C)
-25 -35 Unit Test Conditions Notes Symbol Parameter
Min. Max. Min. Max.
IIL Input Leakage Current -5 +5 -5 +5
IOL Output Leakage Current -5 +5 -5 +5
ICC1 Operating Power Supply
Current
- 115 - 105 mA
µA 0V ≤ Vin ≤ VCC
Pins not under
Test = 0V
DOUT disabled,
µA
0V ≤ Vout ≤ VCC
RAS,
UCAS,LCAS
Address cycling;
tRC = min.
and
1, 2
ICC2 TTL Supply Current Supply
Current
ICC3 Average Power Supply
Current, RAS Refresh
Mode
ICC4 EDO Page Mode Average
Power Supply Current
ICC5
ICC6 CMOS Standby Power
ICC7 Self Refresh Mode Current - 1.0 - 1.0 mA
VOH 2.4 - 2.4 - V IOUT = -5.0mA
VOL
CAS-before-RAS Refresh
Power Supply Current
Supply Current
Output Voltage
- 2.5 - 2.5 mA
- 115 - 105 mA
- 115 - 105 mA
- 115 - 105 mA
- 1.0 - 1.0 mA
- 0.4 - 0.4 V IOUT = 4.2mA
RAS=
UCAS=LCAS
RAS and Address cycling,
UCAS=LCAS
tRC = min.
RAS and address = VIL,
UCAS,LCAS
Address cycling;
tPC = min.
RAS and
LCAS
tRC = min.
RAS=
VCC - 0.2V
RAS=
All other input high levels
are VCC-0.2V or input low
levels are VSS +0.2V
UCAS
cycling;
UCAS=LCAS
≤VSS+0.2V
CAS
= VIH
= VIH,
and
or
=
1, 2
1
1
PRELIMINARY (August, 2002, Version 0.3) 5 AMIC Technology, Inc.
Page 7
A428316 Series
AC Characteristics (VCC = 5.0V ± 10%, VSS = 0V, Ta = 0°C to +70°C or -40°C to +85°C)
Test Conditions:
Input timing reference level: VIH/VIL=2.4V/0.8V
Output reference level: VOH/VOL=2.0V/0.8V
Output Load: 2TTL gate + CL (50pF)
Assumed tT=2ns
Std
#
Symbol
tT Transition Time (Rise and Fall) 1 50 1 50 ns 4, 5
1 tRC Random Read or Write Cycle Time 44 - 62 - ns
2 tRP
3 tRAS
4 tCAS
5 tRCD
6 tRAD
7 tRSH
8 tCSH
9 tCRP
10 tASR Row Address Setup Time 0 - 0 - ns
RAS Precharge Time
RAS Pulse Width
CAS Pulse Width
RAS to CAS Delay Time
RAS to Column Address Delay Time
CAS to RAS Hold Time
CAS Hold Time
CAS to RAS Precharge Time
Parameter
-25 -35
Min. Max. Min. Max.
15 - 23 - ns
25 10K 35 10K ns
4 10K 6 10K ns
10 21 10 25 ns 6
8 14 8 18 ns 7
5 - 6 - ns
25 - 31 - ns
5 - 5 - ns
Unit Notes
11 tRAH Row Address Hold Time 5 - 6 - ns
12 tCLZ
13 tRAC
14 tCAC
15 tAA Access Time from Column Address - 12 - 17 ns 7, 13
16 tOEA
17 tAR
18 tRCS Read Command Setup Time 0 - 0 - ns
19 tRCH Read Command Hold Time 0 - 0 - ns 9
CAS to Output in Low Z
Access Time from RAS
Access Time from CAS
OE Access Time
Column Address Hold Time from RAS
3 - 3 - ns 8
- 25 - 35 ns 6,7
- 8 - 10 ns 6, 13
- 8 - 10 ns
22 - 31 - ns
PRELIMINARY (August, 2002, Version 0.3) 6 AMIC Technology, Inc.
Page 8
A428316 Series
AC Characteristics (continued) (VCC = 5.0V ± 10%, VSS = 0V, Ta = 0°C to +70°C or -40°C to +85°C)
Test Conditions:
Input timing reference level: VIH/VIL=2.4V/0.8V
Output reference level: VOH/VOL=2.0V/0.8V
Output Load: 2TTL gate + CL (50pF)
Assumed tT=2ns
Std
#
Symbol
20 tRRH
21 tRAL
22 tCOH
23 tOFF Output Buffer Turn-Off Delay Time - 3 - 3 ns 8, 10
24 tASC Column Address Setup Time 0 - 0 - ns
25 tCAH Column Address Hold Time 5 - 6 - ns
26 tOES
27 tWCS Write Command Setup Time 0 - 0 - ns 11
28 tWCH Write Command Hold Time 5 - 6 - ns 11
29 tWCR
30 tWP Write Command Pulse Width 5 - 6 - ns
Read Command Hold Time Reference to RAS
Column Address to RAS Lead Time
Output Hold After CAS Low
Low to CAS High Set Up
OE
Write Command Hold Time to RAS
Parameter
-25 -35
Min. Max. Min. Max.
0 - 0 - ns 9
12 - 17 - ns
3 - 3 - ns
5 - 7 - ns
22 - 31 - ns
Unit Notes
31 tRWL
32 tCWL
33 tDS Data-in setup Time 0 - 0 - ns 12
34 tDH Data-in Hold Time 5 - 6 - ns 12
35 tDHR
36 tRWC Read-Modify-Write Cycle Time 62 - 85 - ns
37 tRWD
38 tCWD
PRELIMINARY (August, 2002, Version 0.3) 7 AMIC Technology, Inc.
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data-in Hold Time to RAS
RAS to WE Delay Time (Read-Modify-Write)
CAS to WE Delay Time (Read-Modify-Write)
7 - 10 - ns
5 - 7 - ns
22 - 31 - ns
34 - 46 - ns 11
17 - 21 - ns 11
Page 9
A428316 Series
R
self refresh)
AC Characteristics (continued) (VCC = 5.0V ± 10%, VSS = 0V, Ta = 0°C to +70°C or -40°C to +85°C)
Test Conditions:
Input timing reference level: V
Output reference level: V
Output Load: 2TTL gate + CL (50pF)
Assumed t
T=2ns
IH/VIL=2.4V/0.8V
OH/VOL=2.0V/0.8V
#
Std
Symbol
Parameter
-25 -35
Unit Notes
Min. Max. Min. Max.
39 tAWD
Column Address to
WE Delay Time
21 - 28 - ns 11
(Read-Modify-Write)
40 tOEH
41 tOEP
OE Hold Time from WE
OE High Pulse Width
5 - 6 - ns
5 - 5 - ns
42 tPC Read or Write Cycle Time (EDO Page) 12 - 16 - ns 14
43 tCPA
44 tCP
Access Time from
CAS Precharge (EDO Page)
CAS Precharge Time
- 14 - 18 ns 13
4 - 6 - ns
45 tPCM EDO Page Mode RMW Cycle Time 32 - 40 - ns
46 tCRW
47 tRASP
48 tCSR
EDO Page Mode
CAS Pulse Width (RMW)
RAS Pulse Width (EDO Page)
CAS Setup Time (CAS -before-RAS )
24 - 30 - ns
30 200K 35 200K ns
5 - 5 - ns 3
49 tCHR
50 tRPC
51 tOEZ
52 tRASS
53 tRPS
54 tCHS
CAS Hold Time (CAS -before-RAS )
RAS to CAS Precharge Time
Output Buffer Turn-off Delay from
RAS pulse width (C-B-Rself refresh)
RAS precharge time (C-B-
CAShold time (C-B-Rself refresh)
OE
7 - 10 - ns 3
10 - 10 - ns 3
- 3 - 3 ns 8
100 - 100 -
µs
44 - 62 - ns
-50 - -50 - ns
PRELIMINARY (August, 2002, Version 0.3) 8 AMIC Technology, Inc.
Page 10
A428316 Series
Notes:
1. ICC1, ICC3, ICC4, and ICC5 depend on cycle rate.
2. ICC1 and ICC4 depend on output loading. Specified values are obtained with the outputs open.
3. An initial pause of 200µs is required after power-up followed by any 8 RAS cycles before proper device operation is
achieved. In the case of an internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8
RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks.
4. AC Characteristics assume tT = 2ns. All AC parameters are measured with a load equivalent to two TTL loads and
50pF, VIL (min.) ≥ GND and VIH (max.) ≤ VCC.
5. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are measured
between VIH and VIL.
6. Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference
point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled exclusively by tCAC.
7. Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference
point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled exclusively by tAA.
8. Assumes three state test load (5pF and a 500Ω Thevenin equivalent).
9. Either tRCH or tRRH must be satisfied for a read cycle.
10. tOFF (max.) defines the time at which the output achieves the open circuit condition; it is not referenced to output
voltage levels.
11. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet
as electrical characteristics only. If tWCS ≥ tWCS (min.) and tWCH ≥ tWCH (min.), the cycle is an early write cycle
and data-out pins will remain open circuit, high impedance, throughout the entire cycle. If tRWD ≥ tRWD (min.) , tCWD ≥
tCWD (min.) and tAWD ≥ tAWD (min.), the cycle is a read-modify-write cycle and the data out will contain data read from
the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is
indeterminate.
12. These parameters are referenced to
read-modify-write cycles.
13. Access time is determined by the longer of tAA or tCAC or tCPA.
14. tASC ≥ tCP to achieve tPC (min.) and tCPA (max.) values.
UCAS
and
leading edge in early write cycles and to WE leading edge in
LCAS
PRELIMINARY (August, 2002, Version 0.3) 9 AMIC Technology, Inc.
Page 11
A428316 Series
Word Read Cycle
RAS
UCAS
LCAS
t
CRP(9)
t
ASR(10)
t
RAH(11)
t
RAD(6)
t
RCD(5)
t
CSH(8)
t
ASC(24)
t
RAS(3)
t
RC(1)
t
RAL(21)
t
CAH(25)
t
RSH(7)
t
CAS(4)
t
RP(2)
t
CRP(9)
A0~A8
WE
OE
I/O0 ~
I/O
15
Row Address Column Address
t
AR(17)
t
RCS(18)
t
t
AA(15)
t
RAC(13)
High-Z
t
CLZ(12)
t
CAC(14)
OEA(16)
t
t
OFF(23)
t
OEZ(51)
Valid Data-out
t
RCH(19)
RRH(20)
: High or Low
PRELIMINARY (August, 2002, Version 0.3) 10 AMIC Technology, Inc.
Page 12
A428316 Series
Word Write Cycle (Early Write)
t
RC(1)
t
RAS
UCAS
LCAS
t
CRP(9)
t
ASR(10)
t
RAH(11)
t
RAD(6)
t
RCD(5)
t
t
ASC(24)
AR(17)
t
CSH(8)
RAS(3)
t
CAH(25)
t
CAS(4)
t
RAL(21)
t
RSH(7)
t
RP(2)
t
CRP(9)
A0~A8
WE
OE
I/O0 ~
I/O
15
Row Address Column Address
t
WCR(29)
t
CWL(32)
t
RWL(31)
t
WP(30)
t
WCS(27)
t
DHR(35)
t
DS(33)
t
Valid Data-in
t
WCH(28)
DH(34)
: High or Low
PRELIMINARY (August, 2002, Version 0.3) 11 AMIC Technology, Inc.
Page 13
A428316 Series
Word Write Cycle (Late Write)
t
RC(1)
t
RAS
t
CRP(9)
t
RCD(5)
t
CSH(8)
RAS(3)
t
RSH(7)
t
RP(2)
t
CRP(9)
UCAS
LCAS
A0~A8
WE
OE
I/O0 ~
I/O
15
t
CAS(4)
t
AR(17)
t
t
ASR(10)
t
RAH(11)
RAD(6)
t
ASC(24)
t
CAH(25)
t
RAL(21)
Row Address Column Address
t
WCR(29)
t
t
DHR(35)
t
DS(33)
High-Z
Vaild Data-in
t
CWL(32)
OEH(40)
t
DH(34)
t
RWL(31)
t
WP(30)
: High or Low
PRELIMINARY (August, 2002, Version 0.3) 12 AMIC Technology, Inc.
Page 14
A428316 Series
Word Read-Modify-Write Cycle
t
RWC(36)
t
RAS
UCAS
LCAS
t
CRP(9)
t
ASR(10)
Row Address Column AddressA0~A8
t
RAH(11)
t
RAD(6)
t
RCD(5)
t
AR(17)
t
ASC(24)
t
CAH(25)
RAS(3)
t
CSH(8)
t
RSH(7)
t
RP(2)
t
CRP(9)
WE
OE
I/O0 ~
I/O
15
High-Z
t
RCS(18)
t
RAC(13)
t
CAC(14)
t
CLZ(12)
t
AA(15)
t
RWD(37)
t
OEA(16)
t
AWD(39)
t
CWD(38)
t
OEZ(51)
t
DS(33)tDH(34)
Data-out Data-in
t
CWL(32)
t
RWL(31)
t
WP(30)
t
OEH(40)
: High or Low
PRELIMINARY (August, 2002, Version 0.3) 13 AMIC Technology, Inc.
Page 15
A428316 Series
EDO Page Mode Word Read Cycle
t
RAS
UCAS
t
CRP(9)
t
RCD(5)
t
CSH(8)
t
CAS(4)
RASP(47)
t
CP(44)
t
CAS(4)
t
PC(42)
t
RSH(7)
t
CAS(4)
t
RP(2)
t
CRP(9)
LCAS
A0~A8
WE
OE
I/O0 ~
I/O
15
t
CSH(8)
t
AR(16)
t
t
ASR(10)tRAH(11)
RAD(6)
t
ASC(24)
t
CAH(25)
Row Column Column Column
t
t
RCS(18)
t
RAC(13)
t
AA(15)
t
CAC(14)
CAH(25)
t
OES(26)
t
CLZ(12)
t
OEA(16)
t
RCH(25)
t
CPA(43)
t
CAC(14)
t
RCS(18)
t
COH(22)
Data-out Data-out Data-out
t
OEP(41)
t
AA(15)
t
OEZ(51)
t
RAL(21)
t
ASC(24)
t
RCS(18)
t
OEA(16)
t
CAC(14)
t
CAH(25)
t
CLZ(12)
t
t
RRH(20)
t
OFF(23)
t
OEZ(51)
RCH(19)
: High or Low
PRELIMINARY (August, 2002, Version 0.3) 14 AMIC Technology, Inc.
Page 16
A428316 Series
EDO Page Mode Early Word Write Cycle
t
RASP(47)
RAS
t
UCAS
t
CRP(9)
t
RCD(5)
CSH(8)
t
CAS(4)
t
CP(44)
t
CAS(4)
t
PC(42)
t
CP(44)
t
t
CAS(4)
RSH(7)
t
CRP(9)
t
RP(2)
LCAS
WE
OE
I/O0 ~
I/O
15
t
ASR(10)
t
RAL(21)
t
RAD(6)
t
RAH(11)
t
ASC(24)
Row Column ColumnA0~A8
t
CWL(32)
t
WCS(27)
t
WP(30)
t
DS(33)
t
CAH(25)
t
ASC(24)
t
WCS(27)
t
WCH(28)
t
DH(34)
t
DS(33)
Column
t
CWL(32)
t
WP(30)
t
CAH(25)
t
ASC(24)
t
t
WCH(28)
t
DH(34)
WCS(27)
t
DS(33)
t
WP(30)
t
CWL(32)
t
RWL(31)
t
CAH(25)
t
t
DH(34)
WCH(28)
Data-in Data-in Data-in
: High or Low
PRELIMINARY (August, 2002, Version 0.3) 15 AMIC Technology, Inc.
Page 17
A428316 Series
EDO Page Mode Word Read-Modify-Write Cycle
RAS
UCAS
LCAS
t
CRP(9)
t
ASR(10)
t
RAH(11)
t
RAD(6)
t
RCD(5)
t
CSH(8)
t
CRW(46)
t
ASC(24)
t
CAH(25)
t
CP(44)
t
RASP(47)
t
CRW(46)
t
t
ASC(24)
t
PCM(45)
CAH(25)
t
CP(44)
t
CRW(46)
t
RAL(21)
t
ASC(24)
t
RSH(7)
t
CAH(25)
t
RP(2)
t
CRP(9)
A0~A8
WE
OE
I/O0 ~
I/O
15
Row Column Column Column
t
t
RCS(18)
t
RAC(13)
t
RWD(37)
t
t
AA(15)
t
CWD(38)
AWD(39)
t
OEA(16)
t
CAC(14)
t
OEZ(51)
t
OEH(40)
t
DS(33)
CWL(32)
t
WP(30)
t
CPA(43)
t
AA(15)
t
DH(34)
t
CWD(38)
t
AWD(39)
t
OEA(16)
t
OEZ(51)
t
t
t
DS(33)
CWL(32)
t
WP(30)
CPA(43)
t
AA(15)
t
DH(34)
High-Z
t
CLZ(12)
Data-out
t
CLZ(12)
Data-in
Data-out
t
CLZ(12)
Data-in
t
CWD(38)
t
AWD(39)
t
Data-out
OEA(16)
t
OEZ(51)
Data-in
t
DS(33)
t
CWL(32)
t
RWL(31)
t
WP(30)
t
DH(34)
: High or Low
PRELIMINARY (August, 2002, Version 0.3) 16 AMIC Technology, Inc.
Page 18
A428316 Series
RAS Only Refresh Cycle
t
RC(1)
t
RAS
UCAS
LCAS
t
ASR(10)
t
CRP(9)
t
RAH(11)
RAS(3)
t
RPC(50)
t
RP(2)
A0~A8
Row
Note: WE, OE = Don't care.
CAS Before RAS Refresh Cycle
t
RP(2)
RAS
t
RPC(50)
t
CP(44)
UCAS
LCAS
t
I/O0 ~
I/O
15
OFF(23)
t
CSR(48)
t
CHR(49)
t
RAS(3)
High-Z
t
RC(1)
t
RP(2)
: High or Low
: High or LowNote: WE, OE, Address = Don't care.
PRELIMINARY (August, 2002, Version 0.3) 17 AMIC Technology, Inc.
Page 19
A428316 Series
Hidden Refresh Cycle (Word Read)
RAS
UCAS
LCAS
A0~A8
WE
tAR(17)
tCRP(9)
tASR(10)
tRCD(5)
tRAD(6)
tRAH(11)
tASC(24)
Row Column
tRC(1)
tRAS(3) tRP(2)
tRSH(7)
tRAL(21)
tCAH(25)
tAA(15)
tRC(1)
tRAS(3) tRP(2)
tCHR(49)
tRRH(20)tRCS(18)
tCRP(9)
OE
I/O0 ~
I/O
15
High-Z
tCLZ(12)
tRAC(13)
tOEA(16)
tCAC(14)
Valid Data-out
tOEZ(51)
tOFF(23)
: High or Low
PRELIMINARY (August, 2002, Version 0.3) 18 AMIC Technology, Inc.
Page 20
A428316 Series
Hidden Refresh Cycle (Early Word Write)
RAS
UCAS
LCAS
t
CRP(9)
t
ASR(10)
t
RAD(6)
t
RAH(11)
t
ASC(24)
t
RCD(5)
t
AR(17)
t
RAS(3)
t
RC(1)
t
RAL(21)
t
CAH(25)
t
RSH(7)
t
RP(2)
t
t
CHR(49)
RAS(3)
t
RC(1)
t
CRP(9)
t
RP(2)
A0~A8
WE
OE
I/O0 ~
I/O
15
Row Column
t
WCS(27)
t
WP(30)
t
DS(33)
Valid Data-in
t
WCH(28)
t
DH(34)
: High or Low
PRELIMINARY (August, 2002, Version 0.3) 19 AMIC Technology, Inc.
Page 21
A428316 Series
EDO Page Mode Read-Early-Write Cycle (Pseudo Read-Modify-Write)
RAS
UCAS
t
CRP(9)
t
RCD(5)
t
CSH(8)
t
CAS(4)
t
PC(42)
t
CP(44)
t
RASP(47)
t
CAS(4)
t
PC(42)
t
CP(44)
t
RSH(7)
t
CAS(4)
t
RP(2)
t
CPR(9)
LCAS
A0~A8
WE
OE
I/O0 ~
I/O
15
t
ASR(10)
t
t
RAH(11)
RAD(6)
t
ASC(24)
t
CAH(25)
t
ASC(24)
t
CAH(25)
Row Column Column
t
RCH(19)
t
RCS(18)
t
AA(15)
t
t
RAC(13)
t
OEA(16)
AA(15)
t
CAC(14)
t
CAP(43)
t
COH(22)
t
CAC(14)
Data-out Data-out Data-in
t
ASC(24)
t
WCS(27)
t
DS(33)
t
RAL(21)
t
Column
CAH(25)
t
WCH(28)
t
DH(34)
: High or Low
PRELIMINARY (August, 2002, Version 0.3) 20 AMIC Technology, Inc.
Page 22
A428316 Series
Self Refresh Mode
RAS
UCAS
LCAS
t
RPC(50)
t
RP(2)
t
CP(44)
t
CSR(48)
t
RASS(52)
t
CHS(54)
t
RPS(53)
t
CRP(9)
t
ASR(10)
A0~A8
t
OFF(23)
I/O0 ~
I/O
15
Note: WE, OE = Don't care.
n Self Refresh Mode.
a. Entering the Self Refresh Mode:
The A428316 Self Refresh Mode is entered by using CAS before RAS cycle and holding RAS and CAS signal “low”
longer than 100µs.
b. Continuing the Self Refresh Mode:
The Self Refresh Mode is continued by holding RAS “low” after entering the Self Refresh Mode.
ROW COL
High-Z
: High or Low
It does not depend on CAS being “high” or “low” after entering the Self Refresh Mode continue the Self Refresh Mode.
c. Exiting the Self Refresh Mode:
The A428316 exits the Self Refresh Mode when the RAS signal is brought “high”.
PRELIMINARY (August, 2002, Version 0.3) 21 AMIC Technology, Inc.
Page 23
A428316 Series
RAS
Capacitance
Symbol Signals Parameter Max. Unit Test Conditions
CIN1 A0 - A8 5 pF Vin = 0V
CIN2
CI/O I/O0 - I/O15 I/O Capacitance 7 pF Vin = Vout = 0V
(f = 1MHz, Ta = Room Temperature, VCC = 5.0V ± 10%)
RAS ,
LCAS
OE
UCAS
, WE ,
Input Capacitance 7 pF Vin = 0V
,
Ordering Codes
Package
SOJ 40L (400mil) A428316S-25 A428316S-35 Yes
TSOP 40/44 L type II (400mil) A428316V-25 A428316V-35 Yes
TSOP 40/44 L type II (400mil) A428316V-25U A428316V-35U Yes
Note: -U is for industrial operating temperature range.
Access Time
25ns 35ns Self-Refresh
PRELIMINARY (August, 2002, Version 0.3) 22 AMIC Technology, Inc.
Page 24
A428316 Series
Package Information
SOJ 40L (400mil) Outline Dimensions unit: inches/mm
2140
E
HE
1
S
Seating Plane
D
b
1
b
e
20
A
A1 A2
y
D
L
e1
θ
C
Symbol
A - - 0.144 - - 3.66
A1 0.025 - - 0.64 - A2 0.105 0.110 0.115 2.67 2.79 2.92
b1
b 0.016 0.018 0.022 0.41 0.46 0.56
C 0.008 0.010 0.014 0.20 0.25 0.36
D 1.020 1.025 1.030 25.91 26.04 26.16
E 0.395 0.400 0.405 10.03 10.16 10.29
e 0.044 0.050 0.056 1.12 1.27 1.42
e1
HE
L 0.081 0.093 0.105 2.083 2.39 2.70
S - - 0.050 - - 1.27
y - - 0.004 - - 0.10
θ 0°
Dimensions in inches Dimensions in mm
Min Nom Max Min Nom Max
0.026 0.028 0.032 0.66 0.71 0.81
0.355 0.366 0.376 9.114 9.383 9.652
0.430 0.440 0.450 10.92 11.18 11.43
-
10° 0°
-
10°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e1 is for PC Board surface mount pad pitch design
reference only.
4. Dimension S includes end flash.
PRELIMINARY (August, 2002, Version 0.3) 23 AMIC Technology, Inc.
Page 25
A428316 Series
Package Information
TSOP 40/44L (Type II) (400mil) Outline Dimensions unit: inches/mm
44
E
HE
θ
L
1
1
D
A
L
c
S
B
e
y
D
A1 A2
L
L1
Symbol
A - - 0.047 - - 1.20
A1 0.002 - 0.006 0.05 - 0.15
A2 0.037 0.039 0.041 0.95 1.00 1.05
B 0.013 0.015 0.017 0.32 0.37 0.42
c 0.003 0.005 0.009 0.08 0.13 0.23
D 0.720 0.725 0.730 18.28 18.41 18.54
E 0.395 0.400 0.405 10.03 10.16 10.29
e 0.031 BSC 0.80 BSC
HE 0.455 0.463 0.471 11.56 11.76 11.96
L 0.016 0.020 0.024 0.40 0.50 0.60
L1 - 0.031 - - 0.80 S - - 0.035 - - 0.90
y - - 0.004 - - 0.10
θ
Dimensions in inches Dimensions in mm
Min Nom Max Min Nom Max
1° 3° 5° 1° 3° 5°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
PRELIMINARY (August, 2002, Version 0.3) 24 AMIC Technology, Inc.
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