Datasheet A416316BV, A416316BS-40L, A416316BS-35L, A416316BS, A416316BS-30L Datasheet (AMICC)

A416316B Series

Preliminary 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE

Document Title
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE

Revision History

Rev. No. History Issue Date Remark

0.0 Initial issue November 15, 2000 Preliminary

PRELIMINARY (November, 2000, Version 0.0) AMIC Technology, Inc.

A416316B Series

Preliminary 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE

Features

n Organization: 65,536 words X 16 bits
n Part Identification:

- A416316B

- A416316B-L (with self-refresh mode)

n High speed

- 30/35/40 ns RAS access time

- 16/18/20 ns column address access time

- 10/11/12 ns CAS access time
n Low power consumption

- Operating: 75mA (-30 max)

- Standby: 3 mA (TTL)

Pin Configuration Pin Descriptions

nn SOJ nnTSOP

VCC

I/O0
I/O1
I/O2
I/O3

VCC

I/O4

I/O5
I/O6
I/O7

NC
NC

WE

RAS

NC

VCC

40

1
2
3
4
5
6
7

A416316BS

8
9
10
11
12
13
14
15

A0

16

A1

17

A2

18
19

A3

20

I/O15

39

I/O14

38
37

I/O13

36

I/O12

35

VSS

34

I/O11

33

I/O10

32

I/O9

31

I/O8

30

NC
LCAS

29

UCAS

28

OE

27

NC

26
25

A7
A6

24
23

A5
A4

22
21

VSS

VCC

I/O0
I/O1
I/O2
I/O3

VCC

I/O4

I/O5
I/O6
I/O7

NC
NC

WE

RAS

NC

VCC

1
2
3
4
5
6
7

A416316BV

8
9
10

13
14
15
16
17

A0

18

A1

19

A2

20
21

A3

22

VSS

44

I/O15

43

I/O14

42
41

I/O13

40

I/O12

39

VSS

38

I/O11

37

I/O10

36

I/O9

35

I/O8

32

NC

31

LCAS

30

UCAS
OE

29
28

NC

27

A7
A6

26
25

A5
A4

24

VSS

23

VSS

n Separate CAS (

UCAS

,

LCAS

) for byte selection

n Self refresh mode
n 256 refresh cycles, 4 ms refresh interval

n Read-modify-write, RAS -only, CAS -before-RAS ,

Hidden refresh capability

n TTL-compatible, three-state I/O
n JEDEC standard packages

- 400mil, 40-pin SOJ

- 400mil, 40/44 TSOP type II package

n Single 5V power supply/built-in VBB generator

Symbol Description

A0 – A7 Address Inputs
I/O0 - I/O15 Data Input/Output

RAS

UCAS

LCAS

WE

OE

VCC +5V Power Supply
VSS Ground
NC No Connection

Row Address Strobe
Column Address Strobe/Upper Byte Control

Column Address Strobe/Lower Byte Control
Write Enable
Output Enable

PRELIMINARY (November, 2000, Version 0.0) 1 AMIC Technology, Inc.

A416316B Series

Selection Guide

Symbol Description -30 -35 -40 Unit

tRAC

tAA Maximum Column Address Access Time 16 18 20 ns

tCAC
tOEA

tRC Minimum Read or Write Cycle Time 65 70 75 ns

tPC Minimum Fast Page Mode Cycle Time 19 21 23 ns
ICC1 Maximum Operating Current 95 85 75 mA
ICC6 Maximum CMOS Standby Current 2 2 2 mA

Maximum RAS Access Time

Maximum CAS Access Time
Maximum Output Enable (OE ) Access Time

30 35 40 ns

10 11 12 ns
10 11 12 ns

Functional Description

The A416316B is a high performance CMOS Dynamic
Random Access Memory organized as 65,536 words X
16 bits. The A416316B is fabricated with advanced
CMOS technology and designed with innovative design
techniques resulting in high speed, extremely low power
and wide operating margins at component and system
levels.

The A416316B features a high speed page mode
operation in which high speed read, write and read-write
are performed on any of the bits defined by the column
address. The asynchronous column address uses an
extremely short row address capture time to ease the
system level timing constraints associated with
multiplexed addressing. Output is tri-stated by a column

address strobe (
output enable independent of RAS. Very fast

to output access time eases system design.

LCAS

All inputs are TTL compatible. Fast Page Mode
operation allows random access up to 256 X 16 bits
within a page, with cycle time as short as 19/21/23 ns.

The A416316B is best suited for graphics, digital signal
processing and high performance peripherals.

The A416316B is available in JEDEC standard 40-pin
plastic SOJ package and 40/44 TSOP type II package.

UCAS

and

) which acts as an

LCAS

UCAS

and

PRELIMINARY (November, 2000, Version 0.0) 2 AMIC Technology, Inc.

A416316B Series

Block Diagram

I/O15
I/O14
I/O13
I/O12
I/O11
I/O10

I/O9
I/O8

VCC
VSS

REFRESH

CONTROLLER

Y0 - Y7

COLUMN

DECODER

SENSE AMP

UPPER

BYTE
DATA

I/O

BUFFER

RAS

UCAS

LCAS

WE

OE

RAS CLOCK

GENERATOR

UCAS CLOCK

GENERATOR

LCAS CLOCK

GENERATOR

WE CLOCK

GENERATOR

OE CLOCK

GENERATOR

256 X 16

LOWER

A0
A1
A2
A3

A4
A5
A6
A7

ADDRESS BUFFERS

X0 - X7

ROW DECODER

256

256 X 256 X 16

ARRAY

SUBSTRATE

BIAS

GENERATOR

BYTE
DATA

I/O

BUFFER

I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0

Recommended Operating Conditions (Ta = 0°C to +70°C)

Symbol Description Min. Typ. Max. Unit

VCC

Supply Voltage

VSS 0.0 0.0 0.0 V

VIH

Input Voltage

VIL -1.0 - 0.8 V

PRELIMINARY (November, 2000, Version 0.0) 3 AMIC Technology, Inc.

4.5 5.0 5.5 V

2.4 - VCC + 1 V

A416316B Series

Truth Table

Function

Standby H H H L L L L
Read: Word L L L H L Row/Col. Data Out
Read: Lower Byte L H L H L Row/Col. I/O0-7 = Data Out

RAS

UCAS

LCAS

WE OE

Address I/Os Notes

I/O8-15 = High-Z

Read: Upper Byte L L H H L Row/Col. I/O0-7 = High-Z

I/O8-15 = Data Out

Write: Word(Early) L L L L X Row/Col. Data In
Write: Lower Byte(Early) L H L L X Row/Col. I/O0-7 = Data In

I/O8-15 = X

Write: Upper Byte(Early) L L H L X Row/Col. I/O0-7 = X

I/O8-15 = Data In

Read-Write L L L
Fast-Page-Mode Read: Hi-Z

-First cycle

-Subsequent Cycles
Fast-Page-Mode Write(Early)

-First cycle

-Subsequent Cycles
Fast-Page-Mode Read-Write

-First cycle

-Subsequent Cycles
Hidden Refresh Read
Hidden Refresh Write

RAS-Only Refresh

CBR Refresh
Self Refresh (L-ver only)
Note: 1. Byte Write may be executed with either

2. Byte Read may be executed with either

3. Only one

CAS

signal (

L
L

L
L

L
L

L→H→L
L→H→L

L H H X X Row High-Z

H→L
H→L

UCAS

H→L
H→L

H→L
H→L

H→L
H→L

or

H→L L→H

L L H L Row/Col. Data Out 2
L L L X Row/Col.

L L X X X High-Z 3
L L X X X High-Z

LCAS

H→L
H→L

H→L
H→L

H→L
H→L

UCAS
UCAS

) must be active.

or
or

H
H

L
L

H→L
H→L

LCAS

LCAS

H→L
H→L

X
X

L→H
L→H

active.

active.

Row/Col.

Row/Col.

Col.

Row/Col.

Col.

Row/Col.

Col.

Data Out → Data In

Data Out
Data Out

Data In
Data In

Data In
Data In

Data In → High-Z

1.2

2
2

1
1

1, 2
1, 2

1

PRELIMINARY (November, 2000, Version 0.0) 4 AMIC Technology, Inc.

A416316B Series

Absolute Maximum Ratings*

Input Voltage (Vin) . . . . . . . . . . . . . . . . . . . -1.0V to +7.0V

Output Voltage (Vout) . . . . . . . . . . . . . . . . -1.0V to +7.0V

Power Supply Voltage (VCC) . . . . . . . . . . -1.0V to +7.0V

Operating Temperature (TOPR) . . . . . . . . . . 0°C to +70°C

Storage Temperature (TSTG) . . . . . . . . . -55°C to +150°C

Soldering Temperature X Time (TSLODER) . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C X 10sec

Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . 1W

Short Circuit Output Current (Iout) . . . . . . . . . . . . . 50mA

*Comments

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended
periods may affect device reliability.

Latch-up Current . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA

DC Electrical Characteristics

(VCC = 5V ± 10%, VSS = 0V, Ta = 0°C to +70°C)

Symbol Parameter -30 -35 -40 Unit Test Conditions Notes

Min. Max. Min. Max. Min. Max.

IIL Input Leakage Current -10 +10 -10 +10 -10 +10

IOL Output Leakage

Current

ICC1 Operating Current - 95 - 85 - 75 mA

ICC2 TTL Standby Power

Supply Current

ICC3 Refresh Current

(RAS only Refresh)

ICC4 Fast Page Mode

Current

ICC5 Refresh Current

( CAS -before-

-10 +10 -10 +10 -10 +10

- 3 - 3 - 3 mA

- 95 - 85 - 75 mA

- 95 - 85 - 75 mA

- 95 - 85 - 75 mA

RAS Refresh )

ICC6 CMOS Standby

ICC7

VOH Output High Voltage 2.4 - 2.4 - 2.4 - V IOUT = -5.0mA
VOL Output Low Voltage - 0.4 - 0.4 - 0.4 V IOUT = 4.2mA

Power Supply Current
Self Refresh Mode

Current

- 2 - 2 - 2 mA

- 3 - 3 - 3 mA

µA 0V ≤ Vin ≤ +5.5V

Pins not under test = 0V
DOUT disabled,

µA

0V ≤ Vout ≤ +5.5V

RAS,

UCAS,LCAS

Address cycling
tRC = min.

RAS = CAS≥ VIH

All other inputs ≥ VSS

RAS cycling,

UCAS=LCAS

tRC = min.

RAS = VIL,

UCAS,LCAS

tPC = min.

RAS,

UCAS, LCAS

tRC = min.

RAS = CAS≥ VCC - 0.2V

All other inputs ≥ VSS

RAS = CAS ≤ VSS + 0.2V

All other inputs ≥ VSS

Address cycling

= VIH,

1, 2

1, 2

cycling

1

1

PRELIMINARY (November, 2000, Version 0.0) 5 AMIC Technology, Inc.

A416316B Series

AC Characteristics

(VCC = 5V ± 10%, VSS = 0V, Ta = 0°C to +70°C)

# Std

Symbol

Min. Max. Min. Max. Min. Max.

1 tRC Random Read or Write Cycle Time 65 - 70 - 75 - ns

2 tRP

3 tRAS

4 tCAS

5 tRCD

6 tRAD

7 tRSH

8 tCSH

9 tCRP

10 tASR Row Address Setup Time 0 - 0 - 0 - ns

RAS Precharge Time

RAS Pulse Width

CAS Pulse Width

RAS to CAS Delay Time

RAS to Column Address Delay Time

CAS to RAS Hold Time

CAS Hold Time

CAS to RAS Precharge Time

Parameter

-30 -35 -40
Unit Notes

25 - 25 - 25 - ns

30 75K 35 75K 40 75K ns

12 - 12 - 12 - ns

15 20 16 24 17 28 ns 6

10 14 11 17 12 20 ns 7

10 - 10 - 10 - ns

30 - 35 - 40 - ns

5 - 5 - 5 - ns

11 tRAH Row Address Hold Time 5 - 6 - 7 - ns

tT Transition Time (Rise and Fall) 2 50 2 50 2 52 ns 4, 5

tREF Refresh Period - 4 - 4 - 4 ms 3

12 tCLZ

13 tRAC

14 tCAC

15 tAA Access Time from Column Address - 16 - 18 - 20 ns 7, 13

16 tAR

17 tRCS Read Command Setup Time 0 - 0 - 0 - ns

PRELIMINARY (November, 2000, Version 0.0) 6 AMIC Technology, Inc.

CAS to Output in Low Z

Access Time from RAS

Access Time from CAS

Column Address Hold Time from RAS

0 - 0 - 0 - ns 8

- 30 - 35 - 40 ns 6,7

- 10 - 11 - 12 ns 6, 13

26 - 28 - 30 - ns

A416316B Series

AC Characteristics (continued)

(VCC = 5V ± 10%, VSS = 0V, Ta = 0°C to +70°C)

# Std

Symbol

Min. Max. Min. Max. Min. Max.

18 tRCH Read Command Hold Time 0 - 0 - 0 - ns 9

19 tRRH Read Command Hold Time Reference

to RAS

20 tRAL

21 tCOH

22 tODS Output Disable Setup Time 0 - 0 - 0 - ns

23 tOFF Output Buffer Turn-Off Delay Time 0 6 0 6 0 6 ns 8, 10

24 tASC Column Address Setup Time 0 - 0 - 0 - ns

25 tCAH Column Address Hold Time 5 - 5 - 5 - ns

26 tRPS

27 tWCS Write Command Setup Time 0 - 0 - 0 - ns 11

Column Address to RAS Lead Time

Output Hold After CAS Low

RAS Precharge Setup Time

Parameter

-30 -35 -40

Unit Notes

0 - 0 - 0 - ns 9

16 - 18 - 20 - ns

5 - 5 - 5 - ns

50 - 60 - 70 - ns

28 tWCH Write Command Hold Time 5 - 5 - 5 - ns 11

29 tWCR

30 tWP Write Command Pulse Width 5 - 5 - 5 - ns

31 tRWL

32 tCWL

33 tDS Data-in setup Time 0 - 0 - 0 - ns 12

34 tDH Data-in Hold Time 5 - 5 - 5 - ns 12

35 tDHR

36 tRMW Read-Modify-Write Cycle Time 100 - 105 - 100 - ns

37 tRWD

PRELIMINARY (November, 2000, Version 0.0) 7 AMIC Technology, Inc.

Write Command Hold Time to RAS

Write Command to RAS Lead Time

Write Command to CAS Lead Time

Data-in Hold Time to RAS

RAS to WE Delay Time

(Read-Modify-Write)

26 - 28 - 30 - ns

10 - 11 - 12 - ns

10 - 11 - 12 - ns

26 - 28 - 30 - ns

50 - 54 - 58 - ns 11

A416316B Series

Pulse Width (Self Refresh Mode)

Precharge Time

AC Characteristics (continued)

(VCC = 5V ± 10%, VSS = 0V, Ta = 0°C to +70°C)

# Std

Symbol

Min. Max. Min. Max. Min. Max.

38 tCWD

39 tAWD

40 tRASS

41 tCPN

42 tPC Read or Write Cycle Time (Fast Page) 19 - 21 - 23 - ns 14

43 tCPA

44 tCP

45 tPRM Fast Page Mode RMW Cycle Time 56 - 58 - 60 - ns

CAS to WE Delay Time

(Read-Modify-Write)
Column Address to WE Delay Time

(Read-Modify-Write)

RAS

CAS Precharge Time

(CAS before RAS)

Access Time from CAS Precharge
(Fast Page)

CAS Precharge Time (Fast Page)

Parameter

-30 -35 -40

Unit Notes

26 - 28 - 30 - ns 11

32 - 35 - 35 - ns 11

300 - 300 - 300 -

10 100K 10 100K 10 100K ns

- 19 - 21 - 23 ns 13

3 - 4 - 5 - ns

µs

46 tCRW

47 tRASP

48 tCSR

49 tCHR

50 tRPC

51 tROH

52 tOEA

53 tOED

54 tOEZ

Fast Page Mode CAS Pulse Width
(RMW)

RAS Pulse Width (Fast Page)

CAS Setup Time (CAS -before- RAS )

CAS Hold Time (CAS -before- RAS )

RAS to CAS

(CAS -before-RAS)

RAS Hold Time Reference to OE

OE Access Time

OE to Data Delay

Output Buffer Turn-off Delay from OE

- 44 - 46 - 48 ns

30 75K 35 75K 40 75K ns

0 - 0 - 0 - ns 3

7 - 8 - 8 - ns 3

0 - 0 - 0 - ns

6 - 7 - 8 - ns

- 10 - 11 - 12 ns

5 - 5 - 5 - ns

0 5 0 6 0 6 ns 8

PRELIMINARY (November, 2000, Version 0.0) 8 AMIC Technology, Inc.

A416316B Series

AC Characteristics (continued)

(VCC = 5V ± 10%, VSS = 0V, Ta = 0°C to +70°C)

# Std

Symbol

Min. Max. Min. Max. Min. Max.

55 tOEH

56 tCPT

Notes:

1. ICC1, ICC3, ICC4, and ICC5 depend on cycle rate.

2. ICC1 and ICC4 depend on output loading. Specified values are obtained with the outputs open.

3. An initial pause of 200µs is required after power-up followed by any 8 RAS cycles before proper device operation is
achieved. In the case of an internal refresh counter, a minimum of 8 CAS -before-RAS initialization cycles instead of 8
RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks (greater than

8ms).

4. AC Characteristics assume tT = 3ns. All AC parameters are measured with a load equivalent to one TTL loads and
50pF, VIL (min.) ≥ GND and VIH (max.) ≤ VCC.

5. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are measured
between VIH and VIL.

6. Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference
point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled exclusively by tCAC.

7. Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference
point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled exclusively by tAA.

8. Assumes three state test load (5pF and a 380Ω Thevenin equivalent).

9. Either tRCH or tRRH must be satisfied for a read cycle.

10. tOFF (max.) defines the time at which the output achieves the open circuit condition; it is not referenced to output
voltage levels.

11. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet
as electrical characteristics only. If tWCS ≥ tWCS (min.) and tWCH ≥ tWCH (min.), the cycle is an early write cycle
and data-out pins will remain open circuit, high impedance, throughout the entire cycle. If tRWD ≥ tRWD (min.) , tCWD ≥
tCWD (min.) and tAWD ≥ tAWD (min.), the cycle is a read-modify-write cycle and the data out will contain data read from
the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is
indeterminate.

12. These parameters are referenced to

read-modify-write cycles.

13. Access time is determined by the longer of tAA or tCAC or tCPA.

14. tASC ≥ tCP to achieve tPC (min.) and tCPA (max.) values.

15. These parameters are sampled and not 100% tested.

OE Command Hold Time

CAS Precharge Time

(CAS -before-RAS Counter Test)

Parameter

UCAS

and

-30 -35 -40

0 - 0 - 0 - ns

20 - 20 - 20 - ns

leading edge in early write cycles and to WE leading edge in

LCAS

Unit Notes

PRELIMINARY (November, 2000, Version 0.0) 9 AMIC Technology, Inc.

A416316B Series

Word Read Cycle

tRC(1)

RAS

UCAS
LCAS

A0 ~ A7

WE

tRAS(3)

tCSH(8)

tCRP(9)

tASR(10)

tRAH(11)

tRCD(5) tRSH(7)

tRAD(6) tRAL(20)

tASC(24) tCAH(25)

Row Address Column Address

tAR(16)

tRCS(17)

tRP(2)

tCRP(9)

tCAS(4)

tRCH(18)

tRRH(19)

tROH(51)

tOEA(52)

OE

tCAC(14)

I/O0 ~
I/O15

tAA(15)

tRAC(13)

High-Z

Valid Data-out

tCLZ(12)

tOFF(23)

tOEZ(54)

: High or Low

PRELIMINARY (November, 2000, Version 0.0) 10 AMIC Technology, Inc.

A416316B Series

Word Write Cycle (Early Write)

tRC(1)

RAS

UCAS
LCAS

A0 ~ A7

WE

tRAS(3)

tCSH(8)

tCRP(9)

tASR(10)

tRAH(11)

tRCD(5) tRSH(7)

tAR(16)

tRAD(6) tRAL(20)

tASC(24)

tCAH(25)

Row Address Column Address

tWCR(29)

tCWL(32)

tWP(30)

tRP(2)

tCRP(9)

tCAS(4)

tRWL(31)

tWCS(27)

tWCH(28)

OE

tDHR(35)

tDS(33) tDH(34)

I/O0 ~
I/O15

Valid Data-in

: High or Low

PRELIMINARY (November, 2000, Version 0.0) 11 AMIC Technology, Inc.

A416316B Series

Word Write Cycle (Late Write)

tRC(1)

RAS

UCAS
LCAS

A0 ~ A7

WE

tRAS(3)

tCSH(8)

tCRP(9)

tASR(10)

tRAH(11)

tRCD(5) tRSH(7)

tAR(16)

tRAD(6) tRAL(20)

tASC(24)

tCAH(25)

Row Address Column Address

tWCR(29)

tRP(2)

tCRP(9)

tCAS(4)

tCWL(32)

tRWL(31)

tWP(30)

tOED(54)

tOEH(55)

OE

tDHR(35)

I/O0 ~
I/O15

tDS(33)

High-Z

Vaild Data-in

tDH(34)

: High or Low

PRELIMINARY (November, 2000, Version 0.0) 12 AMIC Technology, Inc.

A416316B Series

Word Read-Modify-Write Cycle

tRMW(36)

RAS

UCAS
LCAS

WE

tCRP(9)

tASR(10)

Row Address Column AddressA0 ~ A7

tCSH(8)

tRCD(5) tRSH(7)

tAR(16)

tRAD(6)

tRAH(11) tCAH(25)

tASC(24)

tRWD(37)

tOEA(52)

tRAS(3)

tAWD(39)

tCWD38)

tOED(53)

tOEZ(54)

tCAS(4)

CWL(32)

t

tRWL(31)

tWP(30))

tRP(2)

tCRP(9)

OE

tCAC(14)

I/O0 ~
I/O15

tAA(15)

tRAC(13)

High-Z

Data-out Data-in

tCLZ(12)

tDS(33) tDH(34)

: High or Low

PRELIMINARY (November, 2000, Version 0.0) 13 AMIC Technology, Inc.

A416316B Series

Fast Page Mode Word Read Cycle

tRASP(47) tRP(2)

RAS

UCAS
LCAS

WE

OE

tCRP(9)

tASR(10)

Row Column ColumnA0 ~ A7

tRAH(11)

tRCD(5)

tRAD(6)

tASC(24)

tRCS(17)

tCSH(8)

tAR(16)

tOEA(52)

tRCH(18)

tCAH(25)

tASC(24)

tPC(42) tRSH(7)

tCAH(25) tCAH(25)

tASC(24)

Column

tAA(15) tAA(15)

tRCS(17) tRCS(17)

tRCH(18)

tCPA(43) tCPA(43)

tOEA(52) tOEA(52)

tCRP(9)

tCAS(4)tCP(44)tCAS(4)tCP(44)tCAS(4)

tRAL(20)

tRRH(19)

tRCH(18)

tROH(51)

I/O0 ~
I/O15

tRAC(13)

tAA(15)

tCAC(14)

tOFF(23) tOFF(23)

tCAC(14)

tOEZ(54)

tOEZ(54)

Data-out Data-out Data-out

tCLZ(12)tCLZ(12)

tOFF(23)

tCAC(14)

tOEZ(54)

tCLZ(12)

: High or Low

PRELIMINARY (November, 2000, Version 0.0) 14 AMIC Technology, Inc.

A416316B Series

Fast Page Mode Early Word Write Cycle

tRASP(47) tRP(2)

RAS

UCAS
LCAS

WE

OE

tCRP(9) tCRP(9)

tASR(10)

tRAH(11)

Row Column ColumnA0 ~ A7

tCSH(8)

tRCD(5)

tRAD(6)

tASC(24)

tCWL(32)

tWCS(27) tWCS(27)

tWP(30) tWP(30)

tCAH(25)

tASC(24)

tWCH(28)

Column

tCWL(32)

tPC(42) tRSH(7)

tCAS(4)tCP(44)tCAS(4)tCP(44)tCAS(4)

tRAL(20)

tCAH(25) tCAH(25)

tASC(24)

tCWL(32)

tRWL(31)

tWCS(27)

tWCH(28)

tWP(30)

tWCH(28)

I/O0 ~
I/O15

tDH(34)

tDS(33) tDS(33)

tDS(33)

Data-in Data-in Data-in

tDH(34)

tDH(34)

: High or Low

PRELIMINARY (November, 2000, Version 0.0) 15 AMIC Technology, Inc.

A416316B Series

Fast Page Mode Word Read-Modify-Write Cycle

RAS

A0 ~ A7

WE

OE

tRASP(47)

tCRP(9)

tASR(10)

tRAD(6)

tRAH(11)

tCSH(8)

tRCD(5)

tCAH(25)

tASC(24)

tPRMW(45) tRSH(7)

tCAS(4)tCP(44)tCAS(4)

tCAH(25)

tASC(24)

Row Column Column Column

tCWL(32)

tRWD(37)

tRCS(17) tCWD(38)

tAWD(39)

tOEA(52) tOEA(52)

tCWD(38)

tWP(30) tWP(30) tWP(30)

tAWD(39) tAWD(39)

tCWL(32)

tRP(2)

tCRP(9)

tCAS(4)tCP(44)

tRAL(20)

tCAH(25)

tASC(24)

tCWL(32)

tRWL(31)

tCWD(38)

tROH(51)
tOEA(52)

I/O0 ~

High-Z

tRAC(13)

tAA(15)

tCAC(14)

tOEZ(54)

tOED(53)

tCPA(43)

tAA(15)

tDH(34)

tDS(33)

tOED(53)

tOEZ(54)

tCPA(43)

tAA(15)

tOEZ(54)

tDH(34)

tDS(33)

I/O15

tCLZ(12) tCLZ(12) tCLZ(12)

Data-out

Data-in

Data-out

Data-in

Data-in

Data-out

: High or Low

PRELIMINARY (November, 2000, Version 0.0) 16 AMIC Technology, Inc.

tOED(53)

tDH(34)

tDS(33)

A416316B Series

Only Refresh Cycle

RAS

RC(1)

t

RAS

CRP(9)

t

UCAS
LCAS

ASR(10)

t

A0 ~ A7

Note: WE, OE = Don't care.

CAS Before RAS Refresh Cycle

Row

tRP(2)

RAH(11)

t

RAS(3)

t

tRAS(3)

tRC(1)

RPC(50)

t

tRP(2)

RP(2)

t

: High or Low

RAS

UCAS
LCAS

I/O0 ~
I/O15

PRELIMINARY (November, 2000, Version 0.0) 17 AMIC Technology, Inc.

tCPN(41)

tRPC(50)

tCHR(49)

tCSR(48)

tOFF(23)

High-Z

: High or LowNote: WE, OE, A0 ~ A7 = Don't care.

A416316B Series

CAS

RAS

Timing Waveform of

RAS

tCSR (48)

CAS

Address

I/O

WE

Read CycleWrite CycleRead-Write Cycle

OE

WE

-before-

tCHR (49)

Refresh Counter Test Cycle

tRAS (3)

tRSH (7)

tCPT (56)

tCAH (25)

Col Address

tAA (15)

tCLZ (12)

tOEA (52)

tWP(30)

tCAS (4)

tRAL (20)

tCAC (14)

Data Out

tROH (53)

tRWL(31)

tCWL(32)

tWCH(28)tWCS(27)

tRP (2)

tOFF (23)

tRRH (19)

tRCH (18)tRCS (17)

tDH (34)tDS (33)

I/O

OE

tRCS (17)

WE

OE

tAA (15)

tCLZ (12)

tCAC (14)

I/O

Data In

tAWD(39)

tCWD(38)

tOED (53)tOEA(52)

tOEZ(54)

tDS (33)

tWP (30)

tCWL(32)

tDH (34)

Data InData Out

PRELIMINARY (November, 2000, Version 0.0) 18 AMIC Technology, Inc.

A416316B Series

Hidden Refresh Cycle (Word Read)

RAS

UCAS
LCAS

A0 ~ A7

WE

tAR(16)

tCRP(9)

tASR(10)

tRCD(5)

tRAD(6)

tRAH(11)
tASC(24)

Row Column

tRC(1)

tRAS(3) tRP(2)

tRSH(7)

tRAL(20)

tCAH(25)

tRC(1)

tRAS(3) tRP(2)

tCHR(49)

tRRH(19)tRCS(17)

tCRP(9)

tAA(15)

OE

I/O0 ~
I/O15

tCAC(14)

tCLZ(12)

tRAC(13)

High-Z

Valid Data-out

tOFF(23)

: High or Low

PRELIMINARY (November, 2000, Version 0.0) 19 AMIC Technology, Inc.

A416316B Series

Hidden Refresh Cycle (Early Word Write)

RAS

UCAS
LCAS

A0 ~ A7

WE

tAR(16)

tCRP(9)

tASR(10)

tRCD(5)

tRAD(6)

tRAH(11)
tASC(24)

Row Column

tWCS(27) tWCH(28)

tRC(1)

tRAS(3) tRP(2)

tRSH(7)

tRAL(20)

tCAH(25)

tWP(30)

tRC(1)

tRAS(3) tRP(2)

tCHR(49)

tCRP(9)

OE

tDS(33) tDH(34)

I/O0 ~
I/O15

Valid Data-in

: High or Low

PRELIMINARY (November, 2000, Version 0.0) 20 AMIC Technology, Inc.

A416316B Series

Self Refresh Mode (A416316B-L Only)

RAS

UCAS
LCAS

A0 ~ A7

I/O0 ~
I/O15

tRPC(50)

tCPN(41)

tOFF(23)

Note: WE, OE = Don't care.

tCSR(48)

High-Z

tRASS(40)tPR(2)

tCHS(21)

tRPS(26)

tCRP(9)

tASR(10)

ROW COL

: High or Low

n Self Refresh Mode.
a. Entering the Self Refresh Mode:

The A416316B-L Self Refresh Mode is entered by using CAS before RAScycle and holding RAS and CAS signal
“low” longer than 300µs.

b. Continuing the Self Refresh Mode:

The Self Refresh Mode is continued by holding RAS “low” after entering the Self Refresh Mode.
It does not depend on CAS being “high” or “low” after entering the Self Refresh Mode continue the Self Refresh Mode.

c. Exiting the Self Refresh Mode:

The A416316B exits the Self Refresh Mode when the RAS signal is brought “high”.

PRELIMINARY (November, 2000, Version 0.0) 21 AMIC Technology, Inc.

A416316B Series

RAS

Capacitance

Symbol Signals Parameter Max. Unit Test Conditions

CIN1 A0 – A7 5 pF Vin = 0V
CIN2

CI/O I/O0 - I/O15 I/O Capacitance 7 pF Vin = Vout = 0V

15

(f = 1MHz, Ta = Room Temperature, VCC = 5V ± 10%)

RAS ,

LCAS

OE

UCAS

,WE ,

Input Capacitance 7 pF Vin = 0V

,

Ordering Codes

Package\

40L SOJ (400 mil) A416316BS-30 A416316BS-35 A416316BS-40 No

40/44L TSOP type II (400mil) A416316BV-30 A416316BV-35 A416316BV-40 No

40L SOJ (400mil) A416316BS-30L A416316BS-35L A416316BS-40L Yes

40/44L TSOP II (400mil) A416316BV-30L A416316BV-35L A416316BV-40L Yes

Access Time

30ns 35ns 40ns Self-Refresh

PRELIMINARY (November, 2000, Version 0.0) 22 AMIC Technology, Inc.

A416316B Series

Package Information
SOJ 40L Outline Dimensions unit: inches/mm

2140

E

HE

1

S

Seating Plane

D

b

1

b

e

20

A

A1 A2

y

D

L

e1

θ

C

Symbol

A - - 0.144 - - 3.66
A1 0.025 - - 0.64 - ­A2 0.105 0.110 0.115 2.67 2.79 2.92

b1

b 0.016 0.018 0.022 0.41 0.46 0.56

C 0.008 0.010 0.014 0.20 0.25 0.36
D 1.020 1.025 1.030 25.91 26.04 26.16

E 0.395 0.400 0.405 10.03 10.16 10.29

e 0.044 0.050 0.056 1.12 1.27 1.42

e1

HE

L 0.081 0.093 0.105 2.083 2.39 2.70

S - - 0.050 - - 1.27

y - - 0.004 - - 0.10

θ 0°

Dimensions in inches Dimensions in mm

Min Nom Max Min Nom Max

0.026 0.028 0.032 0.66 0.71 0.81

0.355 0.366 0.376 9.114 9.383 9.652

0.430 0.440 0.450 10.92 11.18 11.43

-

10° 0°

-

10°

Notes:

1. The maximum value of dimension D includes end flash.

2. Dimension E does not include resin fins.

3. Dimension e1 is for PC Board surface mount pad pitch design
reference only.

4. Dimension S includes end flash.

PRELIMINARY (November, 2000, Version 0.0) 23 AMIC Technology, Inc.

A416316B Series

Package Information
TSOP 40/44L (Type II) Outline Dimensions unit: inches/mm

44

E

HE

θ

L

1

D

A

L1

c

S

B

e

y

D

A1 A2

L

L1

Symbol

A - - 0.047 - - 1.20
A1 0.002 - 0.006 0.05 - 0.15
A2 0.037 0.039 0.041 0.95 1.00 1.05

B 0.013 0.015 0.017 0.32 0.37 0.42

c 0.003 0.005 0.009 0.08 0.13 0.23

D 0.720 0.725 0.730 18.28 18.41 18.54

E 0.395 0.400 0.405 10.03 10.16 10.29

e 0.031 BSC 0.80 BSC

HE 0.455 0.463 0.471 11.56 11.76 11.96

L 0.016 0.020 0.024 0.40 0.50 0.60
L1 - 0.031 - - 0.80 -

S - - 0.035 - - 0.90

y - - 0.004 - - 0.10

θ

Dimensions in inches Dimensions in mm

Min Nom Max Min Nom Max

1° 3° 5° 1° 3° 5°

Notes:

1. The maximum value of dimension D includes end flash.

2. Dimension E does not include resin fins.

3. Dimension S includes end flash.

PRELIMINARY (November, 2000, Version 0.0) 24 AMIC Technology, Inc.