Datasheet A3933SEQ Datasheet (Allegro)

GHC

GLB

GHB

GLA

GHA

26301.100†

Data Sheet

3933

THREE-PHASE POWER

MOSFET CONTROLLER

The A3933SEQ is a three-phase MOSFET controller for use with

SC

GLC

3

4

5

6

CC

7

8

SB

9

10

CB

11

12

SA

13

14

15

CA

VCCOUT

RESET

2

16

LCAP

PGND

1

FAULT

17

FAULT

DEAD

AGND

31

32

CONTROL LOGIC

18

19

VBB

MODE

REF

30

BRAKE

20

H1

29

28

27

26

25

24

23

19

22

21

Dwg. PP-068

SENSE

RC

PWM

BRKSEL

BRKCAP

BRAKE

DIR

H2

H3

bipolar brushless dc motors. It drives all n-channel external power

r

FETs, allowing system cost savings and minimizing

(DS)on

power loss.
The high-side drive block is implemented with bootstrap capacitors at
each output to provide the floating positive supply for the gate drive.
The high-side circuitry also employs a unique “intelligent” FET
monitoring circuit that ensures the gate voltages are at the proper levels
before turn-on and during the ON cycle. This device is targeted for
applications with motor supplies from 12 V to 28 V.

Internal fixed off-time PWM current-control circuitry can be used to
regulate the maximum load current to a desired value. The peak load­current limit is set by the user’s selection of an input reference voltage
and external sensing resistor. The fixed off-time pulse duration is set
by a user-selected external RC timing network.

A power-loss braking circuit brakes the motor on an under-voltage
condition. The device is configured to either coast or dynamically
brake the motor when this occurs.

The A3933SEQ is supplied in a 32-lead rectangular (9 x 7) plastic
chip carrier (quad pack) for minimum-area, surface-mount applica­tions.

ABSOLUTE MAXIMUM RATINGS

at TA = 25°C

Supply Voltage, VBB............................. 28 V

(peak) .............................................. 30 V

Terminal Voltage, V

(peak) .............................................. 15 V

Logic Input Voltage Range,

VIN.................. -0.3 V to V

Sense Voltage Range,

V

............................. -5 V to V

SENSE

Output Voltage Range,

VSA, VSB, VSC.................. -5 V to +30 V

V

, V

GHB

, V

GHC

GHA

VCA, VCB, VCC..................... VSX + 14 V

Operating Temperature Range,

TA................................. -20°C to +85°C

Junction Temperature, TJ................. +150°C

Storage Temperature Range,

TS............................... -55°C to +150°C

................. 13.2 V

CCOUT

LCAP

. -5 V to VBB + 14 V

+ 0.3 V

LCAP

FEATURES AND BENEFITS

■ Drives External N-Channel FETs

■ Intelligent High-Side Gate Drive

■ Selectable Coast or Dynamic Brake on Power Down

■ Adjustable Dead Time for Cross-Conduction Protection

■ Selectable Fast or Slow Current-Decay Modes

■ Internal PWM Peak Current Control

■ Reset/Coast Input

■ 120° Hall Commutation with Internal Pullup

■ Internal 5-V Regulator

■ Low-Side Synchronous Rectification

■ Direction Control

■ PWM Speed-Control Input

■ Fault-Diagnostic Output

■ Under-Voltage Protection

3933

THREE-PHASE POWER
MOSFET CONTROLLER

Functional Block Diagram

V

TO

CCOUT

RTC

DIR

RESET

MODE

PWM

T

REF

SENSE

BRAKE

BRKSEL

BRKCAP

H1

H2

H3

RC

LCAP

+

–

+V

V

BB

REGULATOR

CONTROL

LOGIC

RC BLANKING

(FIXED OFF TIME)

BRAKE

UNDER-

VOLTAGE

DETECT

BOOTSTRAP

MONITOR

GATE-SOURCE

MONITOR

LOW-SIDE

SYNCHRONOUS

RECTIFICATION

1 OF 3 LOW-SIDE DRIVERS

BOOTSTRAP LOW

UNDERVOLTAGE

V

CCOUT

V

GS

LOW

INVALID HALL

CONNECT FOR
12-V OPERATION

BOOTSTRAP

CHARGE

TURN-ON

DELAY

1 OF 3 HIGH-SIDE DRIVERS

TURN-ON

DELAY

HIGH-SIDE
DRIVER

DEAD-TIME

ADJUST

LOW-SIDE
DRIVER

C

X

GH

X

S

X

DEAD

GL

X

PGND

FAULT

AGND

C

boot

TO
1 OF 3
MOTOR
PHASES

TO
LCAP

R

S

TO

SENSE

Dwg. FP-045

Dwg. OA-007-32

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
Copyright © 1999, Allegro MicroSystems, Inc.

RECOMMENDED OPERATING CONDITIONS

Supply Voltage, VBB...................................... 15 V to 28 V

or, if VBB = V

Logic Input Voltage Range, VIN.............. -0.3 V to +4.8 V

Sense Voltage Range, V

RC Resistance .......................................... 10 kΩ to 100 kΩ

PWM Frequency, f

................................... 12 V ±10%

CCOUT

........................ -1 V to +1 V

SENSE

....................... 20 kHz to 100 kHz

PWM

3933

THREE-PHASE POWER

MOSFET CONTROLLER

ELECTRICAL SPECIFICATIONS at TA = 25°C, VBB = V

CCOUT

= 12 V, C

= 1000 pF, C

load

= 0.047 µF

boot

(unless noted otherwise).

Limits

Parameter Symbol Conditions Min Typ Max Units

Supply Current

Quiescent Current I

Reference Voltage V

Ref. Volt. Load Regulation ∆V

LCAP(∆ILCAP)ILCAP

Output Voltage V

Output Voltage Regulation

∆V

CCOUT(∆ICCOUT)VBB

BB

LCAP

CCOUT

RESET low, f

= 40 kHz – 16 19 mA

PWM

RESET high – 15 17 mA

4.75 5.0 5.25 V

= 0 to -2 mA – 10 25 mV

VBB = 28 V 10.8 12 13.2 V

= 28 V, I

= 0 to -10 mA – – 25 mV

CCOUT

Digital Logic Levels

Logic Input Voltage V

Logic Input Current I

IH

V

IL

IH

I

IL

VIH = 2 V – <1.0 10 µA

VIL = 0.8 V -70 – -130 µ A

2.0 – – V

––0.8V

Gate Drive

Low-Side Output Voltage V

High-Side Output Voltage V

Low-Side Output t
Switching Time

High-Side Output t
Switching Time

DEAD Time t
(Source OFF to Sink ON)

GLxH

V

GLxL

GHxH

V

GHxL

rGLx

t

fGLx

rGHx

t

fGHx

DEAD

I

= 1 mA – – 0.30 V

GLx

I

= 1 mA – – 0.25 V

GHx

1 V to 8 V – 50 – ns

8 V to 1 V – 40 – ns

1 V to 8 V – 100 – ns

8 V to 1 V – 100 – ns

I

= 10 µA – 3000 – ns

DEAD

I

= 215 µA – 180 – ns

DEAD

9.5 10.5 11.5 V

9.0 10.5 11.5 V

NOTES: 1. Typical Data is for design information only.

2. Negative current is defined as coming out of (sourcing) the specified device terminal.

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Continued —

3933

THREE-PHASE POWER
MOSFET CONTROLLER

ELECTRICAL SPECIFICATIONS at TA = 25°C, VBB = V

CCOUT

= 12 V, C

= 0.001 µF, C

load

= 0.047 µF

boot

(unless noted otherwise), continued.

Limits

Parameter Symbol Conditions Min Typ Max Units

Bootstrap Capacitor

Bootstrap Charge Current I

Bootstrap Output Voltage V

Leakage Current I

Cx

Cx

Cx

Reference Sx 9.5 10.5 11.5 V

High side switched high, Sx = V

BB

50 100 150 mA

–1520 µA

Current Limit

Offset Voltage V

Input bias current I

SENSE

RC Charge Current I

RC Voltage Threshold V

V

PWM frequency Range f

io

RC

RCL

RCH

PWM

Operating 20 – 100 kHz

–0±5.0 mV

– – -1.0 µA

850 945 1040 µA

1.0 1.1 1.2 V

2.7 3.0 3.2 V

Protection Circuitry

Undervoltage Threshold UVLO Increasing V

Decreasing V

Boot-Strap Capacitor Volt. V

High-Side Gate-Source Volt. V

Fault Output Voltage V

CxSx

GHxSx

FAULT

VBB = 12 V 9.5 – – V

IO = 1 mA – – 0.8 V

BB

BB

9.7 10.2 10.7 V

9.35 – 10.35 V

–6.3– V

Brake Function

Brake Cap. Supply Current I

Low-Side Gate Voltage V

BRKCAP

GLxH

VBB = 8 V, BRKSEL ≥ 2 V – 30 – µA

V

= 0, BRKCAP = 8 V – 6.6 – V

BB

NOTES: 1. Typical Data is for design information only.

2. Negative current is defined as coming out of (sourcing) the specified device terminal.

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

Terminal Descriptions

3933

THREE-PHASE POWER

MOSFET CONTROLLER

Terminal Name

1 PGND

2 RESET

3GLC

4SC

5 GHC

6CC

7GLB

8SB

9 GHB

10 CB

11 GLA

12 SA

13 GHA

14 CA

15 V

16 LCAP

17 FAULT

18 MODE

19 V

20 H1

21 H3

22 H2

23 DIR

24 BRAKE

25 BRKCAP

26 BRKSEL

27 PWM

28 RC

29 SENSE

30 REF

31 DEAD

32 AGND

CCOUT

BB

RESET — A logic input used to enable the device, internally
pulled up to V
device and force all gate drivers to 0 V, coasting the motor. A
logic LOW allows the gate drive to follow commutation logic.
This input overrides BRAKE.

GLA/GLB/GLC — Low-side, gate-drive outputs for external
NMOS drivers. External series-gate resistors (as close as
possible to the NMOS gate) can be used to control the slew rate
seen at the power-driver gate, thereby controlling the di/dt and
dv/dt of the SA/SB/SC outputs. Each output is designed and
specified to drive a 1000 pF load with a rise time of 50 ns.

SA/SB/SC — Directly connected to the motor, these terminals
sense the voltages switched across the load. These terminals
are also connected to the negative side of the bootstrap capaci­tors and are the negative supply connections for the floating
high-side drive.

GHA/GHB/GHC — High-side, gate-drive outputs for external
NMOS drivers. External series-gate resistors (as close as
possible to the NMOS gate) can be used to control the slew rate
seen at the power-driver gate, thereby controlling the di/dt and
dv/dt of the SA/SB/SC outputs. Each output is designed and
specified to drive a 1000 pF load with a rise time of 100 ns.

CA/CB/CC — High-side connections for the bootstrap capaci­tors, positive supply for high-side gate drive. The bootstrap
capacitor is charged to approximately V
associated output SA/SB/SC terminal is low. When the output
swings high, the voltage on this terminal rises with the output to
provide the boosted gate voltage needed for n-channel power
FETs.

(+5 V). A logic HIGH will disable the

LCAP

when the

CCOUT

continued next page

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3933

THREE-PHASE POWER
MOSFET CONTROLLER

Terminal Descriptions (cont’d)

FAULT — Open-drain output to indicate fault condition; will

go active high for any of the following:

1 – invalid HALL input code,

2 – high-side, gate-source voltage less than 7 V,

3 – bootstrap capacitor not sufficiently charged, or

4 – under-voltage condition detected at V

CCOUT

.

The fault state for gate-source and bootstrap monitors are
cleared at each commutation. If the motor has stalled, then the
fault can only be cleared by toggling the RESET terminal or
power-up sequence.

MODE — A logic input to set current-decay method, internally
pulled up to V

(+5 V). When in slow-decay mode (logic

LCAP

HIGH), only the high-side FET is switched open during a PWM
OFF cycle. The fast-decay mode (logic LOW) switches both
the source and sink FETs.

H1/H2/H3 — Hall-sensor inputs; internally pulled up to V

LCAP

(+5 V). Configured for 120° electrical spacing.

DIR — A logic input to reverse rotation, see commutation logic
table. Internally pulled up to V

LCAP

(+5 V).

BRAKE — A logic input to short out the motor windings for a
braking function. A logic HIGH will turn ON the low-side
FETs, turn OFF the high-side FETs. Internally pulled up to
V

(+5 V). The braking torque applied will depend on the

LCAP

speed.

BRKCAP — Connection for reservoir capacitor. This terminal
is used to provide a positive power supply for the sink-drive
outputs for a power-down condition. This will allow predict­able braking, if desired. A blocking diode to V

CCOUT

is re­quired. A 4.7 µF capacitor will provide 6.5 V gate drive for
300 ms. If a power-down braking option is not needed
(BRKSEL = LOW) then this terminal should be tied to V

CCOUT

BRKSEL — A logic input to enable/disable braking on power­down condition. Internally pulled up to V

(+5 V). If held

LCAP

low, the motor will coast on a power-down condition.

RC — An analog input used to set the fixed off time with an
external resistor (RT) and capacitor (CT). The t

blank

controlled by the value of the external capacitor (see Applica­tions Information). As a rule, the fixed off time should not be
less than 10 µs. The resistor should be in the range of 10 kΩ to
100 kΩ.

SENSE — An analog input to the current-limit comparator.
A voltage representing load current appears on this terminal
during ON time, when it reaches REF voltage, the comparator
trips and load current decays for the fixed off-time interval.
Voltage transients seen at this terminal when the drivers turn
ON are ignored for time t

blank

.

REF — An analog input to the current-limit comparator.
Voltage applied here sets the peak load current.

I

V

CCOUT

= V

peak

— A regulated 12 V output; supply for low-side gate

REF/RS

.

drive and bootstrap capacitor charge circuits. It is good practice
to connect a decoupling capacitor from this terminal to AGND,
as close to the device terminals as possible. The terminal
should be shorted to VBB for 12 V applications.

VBB — The A3933 supply voltage. It is good practice to

connect a decoupling capacitor from this terminal to AGND, as
close to the device terminals as possible. This terminal should
be shorted to V

for 12 V applications.

CCOUT

LCAP — Connection for decoupling capacitor for the internal
5 V reference. This terminal can source no more than 2 mA.

DEAD — An analog input. A resistor between DEAD and
LCAP is selected to adjust turn-off to turn-on time. This delay
is needed to prevent shoot-through in the external power FETs.
The allowable resistor range is 20 kΩ to 430 kΩ, which
converts to deadtime of 210 ns to 2.1 µs, using the following
equation:

.

t

DEAD

= (6.75 x 10

-12

x R

) + (75 x 10-9).

DEAD

AGND — The low-level (analog) reference point for the
A3933.

time is

PWM — Speed control input, internally pulled up to V

LCAP

(+5 V). A logic LOW turns OFF all drivers, a logic HIGH will
turn ON selected drivers as determined by H1/H2/H3 input
logic. Holding the terminal high allows speed/torque control
solely by the current-limit circuit via REF analog voltage
command.

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

PGND — The reference point for all low-side gate drivers.

3933

THREE-PHASE POWER

MOSFET CONTROLLER

Commutation Truth Table

Logic Inputs Driver Outputs

H1 H2 H3 DIR GLA GLB GLC GHA GHB GHC SA SB SC

HLHHLLHHLLHZL
HLL H LLH LHL ZHL
HHL H HLL LHL LHZ
LHL H HLL LLH LZH
LHH H LHL LLH ZLH
LLH H LHL HLL HLZ
HLH L HL L L LH LZH
HLL L LHL LLH ZLH
HHL L LHL HLL HLZ
LHL L L LH HLL HZL
LHHLLLHLHLZHL
LLH L HLL LHL LHZ

Input Logic

MODE PWM RESET Mode Operation

L L L Fast decay PWM chop mode, current decay

L H L Fast decay Peak current limit, selected drivers ON
H L L Slow decay PWM chop mode. current decay
H H L Slow decay Peak current limit, selected drivers ON
X X H Coast All gate drive outputs OFF, clear fault logic

Brake Control

BRAKE BRKSEL Normal Operation Under Voltage or Power Loss Condition

L L Normal run mode Coast, all gate drive outputs OFF

L H Normal run mode Dynamic brake, all sink gate drives ON
H L Dynamic brake, all sink gate drives ON Coast, all gate drive outputs OFF
H H Dynamic brake, all sink gate drives ON Dynamic brake, all sink gate drives ON

L = Low Level, H = High Level, X = Don’t Care, Z = High Impedance

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3933

THREE-PHASE POWER
MOSFET CONTROLLER

Applications Information

Bootstrap Capacitor Selection. The high-side bootstrap

circuit operates on a charge-transfer principle. The gate charge
(Qg) specification of the external power MOSFET must be
taken into consideration. The bootstrap capacitor must be large
enough to turn on the MOSFET without losing significant gate
voltage. If the bootstrap capacitor is too large, it would take too
long to charge up during the off portion of the PWM cycle. The
capacitor value must be selected with both of these constraints
in mind.

1) Minimum bootstrap capacitor value to transfer charge. The
charge on the bootstrap capacitor should be 20x greater than the
gate charge (Qg) of the power MOSFET.
Example: For Qg = 0.025 µC, select

C

= 20 x Qg/10.5 V = 0.047 µF.

boot

Check for maximum Vg drop at turn on: dq = C

x dVg, where

boot

Qg = dq.

dVg = dq/C

2) Calculate minimum PWM “OFF” cycle with C

dt = ro x C

= 0.025 µC/0.047 µF = 532 mV.

boot

x ln(0.036/[Qg/C

boot

+ 0.036])

boot

= 0.047

boot

µF.

where ro = 20 ohms, the equivalent internal series resistance of
the bootstrap capacitor monitor circuit.

The sink-side MOSFET will be held OFF for this minimum
time such that the bootstrap capacitor can be recharged
independently of the PWM input frequency.

The above equation is valid for PWM cycles after the bootstrap
capacitor has been charged once. For the first cycle after a
motor phase commutates from Hi-Z to GHx ON, or during the
first charging cycle at power-up, the circuit will ignore PWM
signals until it has been charged.

The time required to charge up at power up and at commutation
change is approximately:

t = C

x 7 V/0.1 A

boot

Protection Circuitry. The A3933 will protect the external
MOSFETs by shutting down the gate drive if any of the
following conditions are detected:

1) Gate Source Monitor (high side only). The voltage on
the GHx terminals must stay 7 V higher than the source. If this
voltage droops below the threshold, the high side turns OFF,
and the low-side gate will turn ON in an attempt to recharge the

bootstrap capacitor. When the bootstrap capacitor has been
properly charged, the high side is turned back ON. The circuit
will allow three faults of this type within one commutation
cycle before signaling a fault and coast the motor (all gate
outputs go low).

2) Bootstrap Monitor. The bootstrap capacitor is charged
whenever a sink-side MOSFET is ON, Sx output goes low, and
the load current recirculates. This happens constantly during
normal operation. A 60 µs timer is started at the beginning of
this cycle and the capacitor is charged with typically 100 mA.
The bootstrap capacitor voltage is clamped at approximately
87% of V

. If the capacitor is not charged to the clamp

CCOUT

voltage in 60 µs, a fault is signaled and the motor will coast.

3) Undervoltage. The internal V

regulator supplies the

CCOUT

low-side gate driver and the bootstrap charge current. It is
critical to ensure that the voltages are at a proper level before
enabling any of the outputs. The undervoltage circuit is active
during power up and will force a motor coast condition until
V

is greater than approximately 10 V.

CCOUT

4) Hall Invalid. Illegal codes for the HALL inputs (000 or

111) will force a fault and coast the motor.

Faults are cleared at the beginning of each commutation. If a
stalled motor results from a fault, the fault can only be cleared
by toggling the RESET terminal or by a power-up sequence.

Current Control. Internal fixed off-time PWM circuitry is
implemented to limit load current to a desired value. The
external sense resistor combined with the applied analog
voltage to REF terminal will set the peak current level
approximately

I

TRIP

≈ V

REF/RS

.

After the peak level is reached, the sense comparator trips and
the load current will decay for a fixed off time.

An external resistor (RT) and capacitor (CT) are used to set the
fixed off-time period (t
range of 10 µs to 50 µs. Longer values for t

= RT x CT). The t

off

should be in the

off

can result in

off

audible noise problems.

Torque control can be implemented by varying the REF input
voltage as long as the PWM input stays high. If direct control
of the torque/current is desired by PWM input, a voltage can be
applied to the REF input to set an absolute maximum current
limit.

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

MOSFET CONTROLLER

Applications Information (cont’d)

3933

THREE-PHASE POWER

PWM Blank. The capacitor (CT) also serves as the means to
set the blank time duration. After the off time expires, the
selected gates are turned back ON. At this time, large current
transients can occur during the reverse recovery time (trr) of the
intrinsic body diodes of the external MOSFETs. To prevent the
current-sense comparator from thinking the current spikes are a
real overcurrent event, the comparator is blanked:

t

= 1.9 x CT/(1 mA-2/RT)

blank

The user must ensure that CT is large enough to cover the
current-spike duration.

Load Current Recirculation. If MODE has been set for
slow decay, the high-side (source) driver will turn OFF forcing
the current to recirculate through the pair of sink MOSFETs. If
MODE has been selected for fast decay, both the selected high­and low-side gates are turned OFF, which will force the current
to recirculate through one sink MOSFET and the high-side
clamp diode. Synchronous rectification (only on the low side)
allows current to flow through the MOSFET, rather than the
clamp diode, during the decay time. This will minimize power
loss during the off period. It is important to take into account
that, when switching, the intrinsic diodes will conduct during
the adjustable deadtime.

V

BB

DRIVE CURRENT

RECIRCULATION
(SLOW-DECAY MODE)

Braking. The A3933 will dynamically brake by forcing all
sink-side MOSFETs ON. This will effectively short out the
BEMF. During braking, the load current can be approximated
by:

I

= V

BRAKE

BEMF/RL

Power Loss Brake. The BRKCAP and BRKSEL terminals
provide a power-down braking option. By applying a logic
level to input BRKSEL, the system can control if the motor is
dynamically braked or is allowed to coast during an
undervoltage event. The reservoir capacitor on the BRKCAP
terminal provides the power to hold the sink-side gates ON after
supply voltage is lost. A logic high on BRKSEL will brake the
motor, a logic low and it will coast.

Layout. Careful consideration must be given to PCB layout
when designing high-frequency, fast-switching, high-current
circuits.

1) The analog ground (AGND), the power ground (PGND),
and the high-current return of the external MOSFETs (the
negative side of the sense resistor) should return separately to
the negative side of the motor supply filtering capacitor. This
will minimize the effect of switching noise on the device logic
and analog reference.

2) Minimize stray inductances by using short, wide copper
runs at the drain and source terminals of all power MOSFETs.
This includes motor lead connections, the input power buss, and
the common source of the low-side power MOSFETs. This will
minimize voltages induced by fast switching of large load
currents.

3) Kelvin connect the SENSE terminal PC trace to the
positive side of the sense resistor.

R

S

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RECIRCULATION
(FAST-DECAY MODE)

Dwg. EP-006-50

3933

THREE-PHASE POWER
MOSFET CONTROLLER

Dimensions in Inches

(controlling dimensions)

0.013

0.021

0.546

0.476

LONG SIDE

(0.446

0.376

SHORT SIDE)

0.050

BSC

0.015

MIN

0.125

0.140

0.595

0.585

0.553

0.547

0.026

0.032

20

21

29

30

132

0.453

0.447

0.495

0.485

14

13

5

4

Dwg. MA-006-32 in

NOTES: 1. Lead spacing tolerance is non-cumulative.

2. Exact body and lead configuration at vendor’s option within limits shown

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

Dimensions in Millimeters

(for reference only)

3933

THREE-PHASE POWER

MOSFET CONTROLLER

0.33

0.54

13.86

12.10

LONG SIDE

(11.32

9.56

SHORT SIDE)

1.27

BSC

0.38

MIN

3.18

3.55

15.11

14.86

14.04

13.90

0.66

0.82

20

21

29

30

132

11.50

11.36

12.57

12.32

14

13

5

4

Dwg. MA-006-32 mm

NOTES: 1. Lead spacing tolerance is non-cumulative.

2. Exact body and lead configuration at vendor’s option within limits shown

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The products described here are manufactured under one or more U.S.

patents or U.S. patents pending.

Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability
of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.

Allegro products are not authorized for use as critical components in
life-support devices or systems without express written approval.

The information included herein is believed to be accurate and reliable.
However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which
may result from its use.

3933

THREE-PHASE POWER
MOSFET CONTROLLER

MOTOR DRIVERS

Function Output Ratings* Part Number

INTEGRATED CIRCUITS FOR BRUSHLESS DC MOTORS

3-Phase Power MOSFET Controller — 28 V 3933
3-Phase Power MOSFET Controller — 50 V 3932
3-Phase Power MOSFET Controller — 50 V 7600
2-Phase Hall-Effect Sensor/Driver 400 mA 26 V 3626
Bidirectional 3-Phase Back-EMF Controller/Driver ±600 mA 14 V 8906
2-Phase Hall-Effect Sensor/Driver 900 mA 14 V 3625
3-Phase Back-EMF Controller/Driver ±900 mA 14 V 8902–A
3-Phase Controller/Drivers ±2.0 A 45 V 2936 & 2936-120

INTEGRATED BRIDGE DRIVERS FOR DC AND BIPOLAR STEPPER MOTORS

Dual Full Bridge with Protection & Diagnostics ±500 mA 30 V 3976
PWM Current-Controlled Dual Full Bridge ±650 mA 30 V 3966
PWM Current-Controlled Dual Full Bridge ±650 mA 30 V 3968
PWM Current-Controlled Dual Full Bridge ±750 mA 45 V 2916
PWM Current-Controlled Dual Full Bridge ±750 mA 45 V 2919
PWM Current-Controlled Dual Full Bridge ±750 mA 45 V 6219
PWM Current-Controlled Dual Full Bridge ±800 mA 33 V 3964
PWM Current-Controlled Full Bridge ±1.3 A 50 V 3953
PWM Current-Controlled Dual Full Bridge ±1.5 A 45 V 2917
PWM Current-Controlled Dual Full Bridge ±1.5 A 45 V 2918
PWM Current-Controlled Microstepping Full Bridge ±1.5 A 50 V 3955
PWM Current-Controlled Microstepping Full Bridge ±1.5 A 50 V 3957
PWM Current-Controlled Dual DMOS Full Bridge ±1.5 A 50 V 3972
Dual Full-Bridge Driver ±2.0 A 50 V 2998
PWM Current-Controlled Full Bridge ±2.0 A 50 V 3952
DMOS Full Bridge PWM Driver ±2.0 A 50 V 3958
Dual DMOS Full Bridge ±2.5 A 50 V 3971

UNIPOLAR STEPPER MOTOR & OTHER DRIVERS

Voice-Coil Motor Driver ±500 mA 6 V 8932–A
Voice-Coil Motor Driver ±800 mA 16 V 8958
Unipolar Stepper-Motor Quad Drivers 1 A 46 V 7024 & 7029
Unipolar Microstepper-Motor Quad Driver 1.2 A 46 V 7042
Unipolar Stepper-Motor Translator/Driver 1.25 A 50 V 5804
Unipolar Stepper-Motor Quad Driver 1.8 A 50 V 2540
Unipolar Stepper-Motor Quad Driver 1.8 A 50 V 2544
Unipolar Stepper-Motor Quad Driver 3 A 46 V 7026

Unipolar Microstepper-Motor Quad Driver 3 A 46 V 7044

* Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits

or over-current protection voltage limits. Negative current is defined as coming out of (sourcing) the output.

† Complete part number includes additional characters to indicate operating temperature range and package style.

Also, see 3175, 3177, 3235, and 3275 Hall-effect sensors for use with brushless dc motors.

†

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]