The A3241 and A3242 integrated circuits are unipolar Hall-effect switches with
digital outputs. These sensors are suited for operation over extended temperature
ranges, up to +150°C. Superior high-temperature performance is made possible through an Allegro
the residual offset voltage normally caused by device overmolding, temperature
excursions, and thermal stress.
The A3241 and A3242 Hall-effect switches include the following on a single
3
silicon chip: voltage regulator, Hall-voltage generator, small-signal amplifi er,
chopper stabilization, Schmitt trigger, and a short circuit protected open-drain
output. Advanced BiCMOS wafer fabrication processing is used to take advantage
of low-voltage requirements, component matching, very low input-offset errors,
and small component geometries.
The integrated voltage regulator permits operation from 3.6 to 24 V. The unipolar
family members operate with a suffi cient south polarity fi eld only, turning off in
the absence of such a south polarity fi eld.
®
patented dynamic offset cancellation, which reduces
Chopper-Stabilized
132
VCC
GND
VOUT
1
2
3
AB SO LUTE MAX I MUM RAT INGS
Supply Voltage, V
Reverse-Supply Voltage, V
Reverse-Supply Current, I
Output Off Voltage, V
Output Current, I
Magnetic Flux Density, B.........................Unlimited
Operating Temperature
Ambient, T
Ambient, T
Maximum Junction, T
Storage Temperature, T
..........................................28 V
CC
OUT
OUTSINK
, Range E..................–40ºC to 85ºC
A
, Range L................–40ºC to 150ºC
A
........................–18 V
RCC
........................–2 mA
RCC
.................................. 28 V
........... Internally Limited
......................165ºC
J(MAX)
.................. –65ºC to 170ºC
S
The A3241 and A3242 are rated for operation between the ambient temperatures
–40°C and 85°C for the E temperature range, and –40°C to 150°C for the L temperature range. The small geometries of the BiCMOS process allow these devices
to be provided in ultrasmall packages. The package styles available provide magnetically optimized solutions for most applications. Package LH is an SOT23W,
a miniature low-profi le surface-mount package, while package UA is a three-lead
ultramini SIP for through-hole mounting. Each package is available in a lead (Pb)
free version, with 100% matte tin plated leadframes.
Maximum voltage must be adjusted for power dissipation and junction temperature, see Power Derating section.
2
CS = oscilloscope probe capacitance.
3
Maximum current limit is equal to the maximum I
4
Magnetic fl ux density, B, is indicated as a negative value for north-polarity magnetic fi elds, and as a positive value for south-polarity magnetic fi elds.
This so-called algebraic convention supports arithmetic comparison of north and south polarity values, where the relative strength of the fi eld is indicated
by the absolute value of B, and the sign indicates the polarity of the fi eld (for example, a –100 G fi eld and a 100 G fi eld have equivalent strength, but
opposite polarity).
The output of these devices switches low (turns on) when a
magnetic fi eld (south polarity) perpendicular to the Hall sen-
sor exceeds the operate point threshold, BOP. After turn-on, the
output voltage is V
OUT(SAT)
. The output transistor is capable of
sinking current up to the short circuit current limit, IOM, which
is a minimum of 30 mA. When the magnetic fi eld is reduced
below the release point, B
, the device output goes high (turns
RP
off). The difference in the magnetic operate and release points is
the hysteresis, B
, of the device. This built-in hysteresis allows
hys
clean switching of the output even in the presence of external
mechanical vibration and electrical noise.
OP
OP
or
Powering-on the device in the hysteresis region, less than B
and higher than B
, allows an indeterminate output state. The
RP
correct state is attained after the fi rst excursion beyond B
BRP.
(A)
V+
V
Switch to Low
CC
Applications
It is strongly recommended that an external bypass capacitor be
connected (in close proximity to the Hall sensor) between the
supply and ground of the device to reduce both external noise
and noise generated by the chopper stabilization technique. As is
shown in Panel B of fi gure 1, a 0.1μF capacitor is typical.
Extensive applications information on magnets and Hall-effect
sensors is available in:
• Hall-Effect IC Applications Guide, AN27701,
• Hall-Effect Devices: Gluing, Potting, Encapsulating, Lead Welding and Lead Forming, AN27703.1
• Soldering Methods for Allegro’s Products – SMT and Through-Hole, AN26009
All are provided in Allegro Electronic Data Book, AMS-702 and
the Allegro Web site: www.allegromicro.com
(B)
V
S
VCC
R
LOAD
C
CC
V
Switch to High
V
OUT(SAT)
0
B
HYS
B
OP
0
B–
Figure 1: Switching Behavior of Unipolar Switches. In Panel A, on the horizontal axis, the B+ direction indicates increasing south polarity
magnetic fi eld strength, and the B– direction indicates decreasing south polarity fi eld strength (including the case of increasing north
polarity). This behavior can be exhibited when using a circuit such as that shown in panel B.
When using Hall-effect technology, a limiting factor for
switchpoint accuracy is the small signal voltage developed
across the Hall element. This voltage is disproportionally small
relative to the offset that can be produced at the output of the
Hall sensor. This makes it diffi cult to process the signal while
maintaining an accurate, reliable output over the specifi ed oper-
ating temperature and voltage ranges.
Chopper stabilization is a unique approach used to minimize
Hall offset on the chip. The patented Allegro technique, namely
Dynamic Quadrature Offset Cancellation, removes key sources
of the output drift induced by thermal and mechanical stresses.
This offset reduction technique is based on a signal modulationdemodulation process. The undesired offset signal is separated
from the magnetic-fi eld-induced signal in the frequency domain,
through modulation. The subsequent demodulation acts as a
modulation process for the offset, causing the magnetic-fi eld-
induced signal to recover its original spectrum at baseband,
while the dc offset becomes a high-frequency signal. The magnetic-fi eld-induced signal then can pass through a low-pass fi lter,
while the modulated dc offset is suppressed. This confi guration
is illustrated in fi gure 2.
The chopper stabilization technique uses a 200 kHz high-frequency clock. For demodulation process, a sample and hold
technique is used, where the sampling is performed at twice the
chopper frequency (400 kHz). This high-frequency operation
allows a greater sampling rate, which results in higher accuracy
and faster signal-processing capability. This approach desensitizes the chip to the effects of thermal and mechanical stresses,
and produces devices that have extremely stable quiescent Hall
output voltages and precise recoverability after temperature
cycling. This technique is made possible through the use of a
BiCMOS process, which allows the use of low-offset, low-noise
amplifi ers in combination with high-density logic integration and
sample-and-hold circuits.
The repeatability of magnetic-fi eld-induced switching is affected
slightly by a chopper technique. However, the Allegro highfrequency chopping approach minimizes the affect of jitter and
makes it imperceptible in most applications. Applications that
are more likely to be sensitive to such degradation are those
requiring precise sensing of alternating magnetic fi elds; for
example, speed sensing of ring-magnet targets. For such applications, Allegro recommends its digital sensor families with lower
sensitivity to jitter. For more information on those devices,
contact your Allegro sales representative.
The device must be operated below the maximum junction
temperature of the device, T
. Under certain combinations of
J(max)
peak conditions, reliable operation may require derating supplied power or improving the heat dissipation properties of the
application. This section presents a procedure for correlating
factors affecting operating TJ. (Thermal data is also available on
the Allegro MicroSystems Web site.)
The Package Thermal Resistance, R
, is a fi gure of merit sum-
θJA
marizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity,
K, of the printed circuit board, including adjacent devices and
traces. Radiation from the die through the device case, R
relatively small component of R
. Ambient air temperature,
θJA
θJC
, is
TA, and air motion are signifi cant external factors, damped by
overmolding.
The effect of varying power levels (Power Dissipation, P
), can
D
be estimated. The following formulas represent the fundamental
relationships used to estimate TJ, at PD.
PD = VIN × I
ΔT = P
× R
D
IN
(2)
θJA
(1)
Example: Reliability for V
at TA = 150°C, package LH, using a
CC
low-K PCB.
Observe the worst-case ratings for the device, specifi cally:
R
228 °C/W, T
θJA =
I
CC(max) = 5
mA.
Calculate the maximum allowable power level, P
J(max) =
165°C, V
CC(max) =
24 V, and
D(max)
. First,
invert equation 3:
ΔT
max
= T
– TA = 165 °C – 150 °C = 15 °C
J(max)
This provides the allowable increase to TJ resulting from internal
power dissipation. Then, invert equation 2:
P
D(max)
= ΔT
max
÷ R
= 15°C ÷ 228 °C/W = 65.8 mW
θJA
Finally, invert equation 1 with respect to voltage:
V
CC(est)
= P
D(max)
÷ I
= 65.8 mW ÷ 5 mA = 13.2 V
CC(max)
The result indicates that, at TA, the application and device can
dissipate adequate amounts of heat at voltages ≤V
Compare V
able operation between V
R
. If V
θJA
V
is reliable under these conditions.
CC(max)
CC(est)
CC(est)
to V
≥ V
. If V
CC(max)
CC(est)
CC(max)
CC(est)
and V
CC(max)
, then operation between V
≤ V
CC(max)
requires enhanced
.
CC(est)
, then reli-
CC(est)
and
TJ = TA + ΔT (3)
For example, given common conditions such as: T
V
= 12 V, I
CC
PD = VCC × I
ΔT = PD × R
= 1.5 mA, and R
CC
= 12 V × 1.5 mA = 18 mW
CC
= 18 mW × 165 °C/W = 3°C
θJA
θJA
= 165 °C/W, then:
TJ = TA + ΔT = 25°C + 3°C = 28°C
A worst-case estimate, P
able power level (V
at a selected R
The products described herein are manufactured under one
or more of the following U.S. patents: 5,045,920; 5,264,783;
5,442,283; 5,389,889; 5,581,179; 5,517,112; 5,619,137; 5,621,319;
5,650,719; 5,686,894; 5,694,038; 5,729,130; 5,917,320; and other
patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time
to time, such de par tures from the detail spec i fi ca tions as may be
required to permit improvements in the per for mance, reliability,
or manufacturability of its products. Before placing an order, the
user is cautioned to verify that the information being relied upon is
current.
Allegro products are not authorized for use as critical components in life-support devices or sys tems without express written
approval.
The in for ma tion in clud ed herein is believed to be ac cu rate and
reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other
rights of third parties which may result from its use.