A31W65132 Series
Preliminary LCD Controller-Driver
Document Title
LCD Controller-Driver
Revision History
Rev. No. History Issue Date Remark
0.0 Initial issue April 20, 2000 Preliminary
0.1 Error correction: February 19, 2001
Add pad coordinates
Change power supply range:
C3- → C3+
C1+ → C1C1- → C1+
C2- → C2+
C2+ → C2-
2.0V to 5.5V → 2.4V to 5.5V
PRELIMINARY (February, 2001, Version 0.1) AMIC Technology, Inc.
A31W65132 Series
Preliminary LCD Controller-Driver
Features
n Power supply range : 2.4V to 5.5V
6.0V to 16.5V (LCD drive)
n Internal LCD drivers :
132 segment signal drivers
65 commons signal drivers
n Power save current (<1uA)
n On chip 132 x 65 Display Data RAM
n 8 BIT 80/68-Series Parallel interface ,Serial interface
n Build-in RC oscillator or external clock input
The A31W65132 series is a CMOS LCD driver, which has 132 segment, and 65 common graphic display. It has 80/68series 8 bit parallel and serial interface capability for operating with general CPU. The internal 65 x 132 display data RAM
makes the display of both graphics and characters possible. Besides the general LCD driver features, it has on chip LCD
bias divider circuit such that minimize external component required in system application.
n 1:7 / 1:9 Bias Ratio
n 64 level internal contrast control
n 8 level internal resistor ratio set (V5 voltage)
n Build-in temperature compensation circuit
n Internal bias divider circuit
n On chip internal DC/DC converter / External Power supply
n Dual/ Triple/ Quad booster
n Internal icon common Output system for indicators
n TCP package, Gold bumps
PRELIMINARY (February, 2001, Version 0.1) 1 AMIC Technology, Inc
Block Diagram
1. Block Overview
A31W65132 Series
VDD
V1 to V5
C3+
C1C1+
C2+
C2-
VOUT
VCNT
VRS
IRS
HPM
CLS
CL
LCD
Power
Supply
Circuit
Oscillating
Circuit
Display Data
Control
Data
Input/
Output
COMINC1 COM1 to 64 SEG1 to 132
Page
Address
Decode
COMINC2
LCD Driver
Data Latch
Display RAM
8580 bits
Column Address
Decoder
Start
Line
Address
Decoder
Start
Line
Register
& Counter
Line
Control
Start
Line
Register
FRS
FR
DOF
M/S
VSS
LCD
Timing
Circuit
Power on
Reset
D0 to D7
Page
Address
Register
Command
Decoder
Column Address
Register & Counter
MPU interface
For 68-Series & 80-Series
A0 P/S
C68/80 CS2 R/W
E
Status
Register
RES CS1
PRELIMINARY (February, 2001, Version 0.1) 2 AMIC Technology, Inc
Block Diagram
2. LCD Power Supply Circuit Block Diagram
A31W65132 Series
C3+
C1-
C1+
C2+
C2-
CLK
Quad Booster,
Triple Booster &
Double Booster
Reference
Regular
Reference
Voltage
VOUT VCNT
Voltage Regular
Command
Register
IRSVRSHPM
Adjustment
Circuit
Bias
Resister
Voltage
Follower
V5
V4
V3
V2
V1
PRELIMINARY (February, 2001, Version 0.1) 3 AMIC Technology, Inc
Pad Assignment
NC
COMINC2
287 266
1
NC
FRS
FR
CL
DOF
NC
VSS
CS1
CS2
VDD
RES
A0
VSS
WR,R/W
RD, E
VDD
D0
D1
D2
D3
D4
D5
D6, SCL
D7, SI
NC
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
VOUT
VOUT
C3+
C3+
C1-
C1C1+
C1+
C2+
C2+
C2-
C2-
VSS
VSS
VRS
VRS
VDD
VDD
V1
V1
V2
V2
NC
V3
V3
V4
V4
V5
V5
NC
VCNT
VCNT
VDD
VDD
VDD
M/S
CLS
VSS
C68/80
P/S
VDD
HPM
VSS
IRS
VDD
83
NC 106 NC
NC
COM32
COM64
COM63
COM31
COM30
COM62
COM61
COM29
COM28
COM60
COM59
COM27
COM26
COM58
COM57
COM25
COM24
COM56
COM55
COM23
COM22
COM54
COM53
COM21
COM20
COM52
COM51
COM19
COM18
COM50
COM49
COM17
COM16
COM48
COM47
265
COM15
COM14
COM46
COM45
.
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10584
COM13
COM12
NC
NC
COM44
COM43
COM42
COM41
COM40
COM39
COM38
COM37
COM36
COM35
COM34
COM33
SEG132
SEG131
SEG130
SEG129
.
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.
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SEG4
SEG3
SEG2
SEG1
COMINC1
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
NC
A31W65132 Series
Chip Identification Marks
(The identification marks are larger than the actual scaling)
50 50
50
50
Unit : um
50
50
50 50
(The identification marks are made of AI patterns)
. Pad pitch
Segment driver 65um
Comon driver 65um
Control pad 100um
. Gold bump size
Drive 43x85um
Input pin 73x85um
. Gold bump height 18um (Typ.)
PRELIMINARY (February, 2001, Version 0.1) 4 AMIC Technology, Inc
A31W65132 Series
DOF
CS1
RES
W/R
W
RD
HPM
Pad Coordinates
Unit: µm (The origin is the center of the chip)
No. Pin Name X Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
NC -5152.5
FRS -4971.2
FR -4706
CL -4445.8
NC -3999.3
VSS -3899.3
CS2 -3685.7
VDD -3572.7
A0 -3359.7
VSS -3246.7
, R/
, E
VDD -2920.7
D0 -2739.1
D1 -2473.9
D2 -2213.7
D3 -1948.1
D4 -1687.9
D5 -1422.7
D6, SCL -1162.5
D7, SI -896.9
NC -715.6
VDD -615.6
VDD -515.6
VDD -415.6
VDD -315.6
VSS -215.6
VSS -115.6
VSS -15.6
VSS 84.4
VSS 184.4
VSS 284.4
VSS 384.4
NC 484.4
VOUT 584.4
VOUT 684.4
C3+ 784.4
C3+ 884.4
C1- 984.4
C1- 1084.4
C1+ 1184.4
C1+ 1284.4
C2+ 1384.4
C2+ 1484.4
C2- 1584.4
-4180.6
-3785.7
-3459.7
-3133.7
-3033.7
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
No. Pin Name X Y
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
C2- 1684.4
VSS 1784.4
VSS 1884.4
VRS 1984.4
VRS 2084.4
VDD 2184.4
VDD 2284.4
V1 2384.4
V1 2484.4
V2 2584.4
V2 2684.4
NC 2784.4
V3 2884.4
V3 2984.4
V4 3084.4
V4 3184.4
V5 3284.4
V5 3384.4
NC 3484.4
VCNT 3584.4
VCNT 3684.4
VDD 3784.4
VDD 3884.4
VDD 3984.4
M/S 4097.4
CLS 4197.4
VSS 4310.4
C68/80 4423.4
P/S 4523.4
VDD 4636.4
VSS 4836.4
IRS 4936.4
VDD 5036.4
NC 5136.4
NC 5146.5
COM32 5146.5
COM31 5146.5
COM30 5146.5
COM29 5146.5
COM28 5146.5
COM27 5146.5
COM26 5146.5
COM25 5146.5
COM24 5146.5
COM23 5146.5
COM22 5146.5
COM21 5146.5
4736.4
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-726.3
-661.3
-596.3
-531.3
-466.3
401.3
-336.3
-271.3
-206.3
-141.3
-76.3
-11.3
53.7
PRELIMINARY (February, 2001, Version 0.1) 5 AMIC Technology, Inc
A31W65132 Series
Pad Coordinates (continued)
Unit: µm (The origin is the center of the chip)
No. Pin Name X Y
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
COM20 5146.5
COM19 5146.5
COM18 5146.5
COM17 5146.5
COM16 5146.5
COM15 5146.5
COM14 5146.5
COM13 5146.5
COM12 5146.5
NC 5167.5
NC 5102.5
COM11 5037.5
COM10 4972.5
COM9 4907.5
COM8 4842.5
COM7 4777.5
COM6 4712.5
COM5 4647.5
COM4 4582.5
COM3 4517.5
COM2 4452.5
COM1 4387.5
COMINC1 4322.5
SEG1 4257.5
SEG2 4192.5
SEG3 4127.5
SEG4 4062.5
SEG5 3997.5
SEG6 3932.5
SEG7 3867.5
SEG8 3802.5
SEG9 3737.5
SEG10 3672.5
SEG11 3607.5
SEG12 3542.5
SEG13 3477.5
SEG14 3412.5
SEG15 3347.5
SEG16 3282.5
SEG17 3217.5
SEG18 3152.5
SEG19 3087.5
SEG20 3022.5
SEG21 2957.5
SEG22 2892.5
SEG23 2827.5
SEG24 2762.5
SEG25 2697.5
118.7
183.7
248.7
313.7
378.7
443.7
508.7
573.7
638.7
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
No. Pin Name X Y
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
SEG26 2632.5
SEG27 2567.5
SEG28 2502.5
SEG29 2437.5
SEG30 2372.5
SEG31 2307.5
SEG32 2242.5
SEG33 2177.5
SEG34 2112.5
SEG35 2047.5
SEG36 1982.5
SEG37 1917.5
SEG38 1852.5
SEG39 1787.5
SEG40 1722.5
SEG41 1657.5
SEG42 1592.5
SEG43 1527.5
SEG44 1462.5
SEG45 1397.5
SEG46 1332.5
SEG47 1267.5
SEG48 1202.5
SEG49 1137.5
SEG50 1072.5
SEG51 1007.5
SEG52 942.5
SEG53 877.5
SEG54 812.5
SEG55 747.5
SEG56 682.5
SEG57 617.5
SEG58 552.5
SEG59 487.5
SEG60 422.5
SEG61 357.5
SEG62 292.5
SEG63 227.5
SEG64 162.5
SEG65 97.5
SEG66 32.5
SEG67 -32.5
SEG68 -97.5
SEG69 -162.5
SEG70 -227.5
SEG71 -292.5
SEG72 -357.5
SEG73 -422.5
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
PRELIMINARY (February, 2001, Version 0.1) 6 AMIC Technology, Inc
A31W65132 Series
Pad Coordinates (continued)
Unit: µm (The origin is the center of the chip)
No. Pin Name X Y
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
SEG74 -487.5
SEG75 -552.5
SEG76 -617.5
SEG77 -682.5
SEG78 -747.5
SEG79 -812.5
SEG80 -877.5
SEG81 -942.5
SEG82 -1007.5
SEG83 -1072.5
SEG84 -1137.5
SEG85 -1202.5
SEG86 -1267.5
SEG87 -1332.5
SEG88 -1397.5
SEG89 -1462.5
SEG90 -1527.5
SEG91 -1592.5
SEG92 -1657.5
SEG93 -1722.5
SEG94 -1787.5
SEG95 -1852.5
SEG96 -1917.5
SEG97 -1982.5
SEG98 -2047.5
SEG99 -2112.5
SEG100 -2177.5
SEG101 -2242.5
SEG102 -2307.5
SEG103 -2372.5
SEG104 -2437.5
SEG105 -2502.5
SEG106 -2567.5
SEG107 -2632.5
SEG108 -2697.5
SEG109 -2762.5
SEG110 -2827.5
SEG111 -2892.5
SEG112 -2957.5
SEG113 -3022.5
SEG114 -3087.5
SEG115 -3152.5
SEG116 -3217.5
SEG117 -3282.5
SEG118 -3347.5
SEG119 -3412.5
SEG120 -3477.5
SEG121 -3542.5
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
No. Pin Name X Y
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
SEG122 -3607.5
SEG123 -3672.5
SEG124 -3737.5
SEG125 -3802.5
SEG126 -3867.5
SEG127 -3932.5
SEG128 -3997.5
SEG129 -4062.5
SEG130 -4127.5
SEG131 -4192.5
SEG132 -4257.5
COM33 -4322.5
COM34 -4387.5
COM35 -4452.5
COM36 -4517.5
COM37 -4582.5
COM38 -4647.5
COM39 -4712.5
COM40 -4777.5
COM41 -4842.5
COM42 -4907.5
COM43 -4972.5
COM44 -5037.5
NC -5102.5
NC -5167.5
COM45 -5146.5
COM46 -5146.5
COM47 -5146.5
COM48 -5146.5
COM49 -5146.5
COM50 -5146.5
COM51 -5146.5
COM52 -5146.5
COM53 -5146.5
COM54 -5146.5
COM55 -5146.5
COM56 -5146.5
COM57 -5146.5
COM58 -5146.5
COM59 -5146.5
COM60 -5146.5
COM61 -5146.5
COM62 -5146.5
COM63 -5146.5
COM64 -5146.5
COMINC2 -5146.5
NC -5146.5
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
638.7
573.7
508.7
443.7
378.7
313.7
248.7
183.7
118.7
53.7
-11.3
-76.3
-141.3
-206.3
-271.3
-336.3
-401.3
-466.3
-531.3
-596.3
-661.3
-726.3
PRELIMINARY (February, 2001, Version 0.1) 7 AMIC Technology, Inc
Input/Output Pin Function
7, 13,
36,
51,
10, 16,
29,
55,
72,
Oscillator
DOF
DOF
DOF
DOF
Pin No. Symbol Type Description
A31W65132 Series
305075, 80
26547078, 82
52-53 VRS Supply External VREG voltage supply for LCD voltage regulator.
74 CLS Input CLS = High : Internal oscillator is enabled
4 CL In/out
73 M/S Input
VSS Supply GROUND
VDD Supply Power supply pin
CLS = Low : Internal oscillator is disabled
Display clock input
The CL pins must be connected in Master/Slave mode.
M/S = High : Master mode
M/S = Low : Slave mode
M/S CLS Power
H H Enable Enable Output Output Output Output
H L Enable Disable Input Output Output Output
L H Disable Disable Input Input Input Output
L L Disable Disable Input Input Input Output
The signals FR,
M/S CLS CL
H H Output
H L Input
L H Input
L L Input
Supply
Circuit
, CL of slave chips must be supplied from the master chip.
Circuit
CL FR
FRS
3 FR In/out LC alternating current signal pin
M/S = High : Output
M/S = Low : Input
The FR pins must be connected in Master/Slave mode.
5
2 FRS Output The FRS output for the static icon drive and is used in conjunction with the FR
PRELIMINARY (February, 2001, Version 0.1) 8 AMIC Technology, Inc
In/out LCD blanking control pin
M/S = High : Output
M/S = Low : Input
The
pin, one of the static icon electrodes is connected to the FR pin, and the other is
connected to FRS pin.
pins must be connected in Master/Slave mode
Input/Output Pin Function (continued)
HPM
HPM
HPM
This pin is used in master mode. When in slave mode, it can fixed to either High or
CS1
CS1
Pin No. Symbol Type Description
81 IRS
79
Input The IRS is used in V5 voltage adjustment
IRS = High : used the internal resistors
IRS = Low : used the external resistors
This pin is used in master mode. When in slave mode, it can fixed to either High or
Low level
Input
= High : Normal mode power supply
= Low : High power mode power supply
A31W65132 Series
8, 9
CS2
11
12 A0 Input A0=Low: Command input.
14
77 P/S Input Parallel/serial interface select input
76 C68/80 Input Microprocessor interface select input
17-24 D0-7
RES
R/W
(WR)
(RD)
(SI, SCL)
Input
Input Reset pin, Low enable
Input
Input
Input/
Output
Low level
Chip select input. When
A0=High: Display data input and outputs
68-Series R/W=High: Read, R/W=Low : Write
80-Series : Write enable, Active Low
68-Series : Enable clock signal input, Active High 15 E
80-Series : Read enable, Active Low
High : 8-bit parallel interface
Low : Serial interface , display data RAM reading is not supported
High : 68-Series interface is selected
Low : 80-Series interface is selected
8bit bi-directional data bus to be connected to microprocessor’s data bus
P/S = High : 8-bit configuration data bus connection
P/S = Low : Serial interface connection
D6 Serial data input SCL
D7 Serial clock input SI
= Low, CS2 = High, enable the chip select
120-251 SEG1-
SEG132
85-105,
108-118,
252-263,
266-285
119,
286
38-39 VOUT Output Boosting voltage output
40-41 C3+ Input 3rd- step boosting capacitor negative connection
PRELIMINARY (February, 2001, Version 0.1) 9 AMIC Technology, Inc
COM1-
COM64
COMINC1
COMINC2
Output Provide the LCD segment driving signal
Output Provide the LCD common driving signal
Output Provide the icon common driving signal, the same signal is output in master/slave
mode
A31W65132 Series
Input/Output Pin Function (continued)
Pin No. Symbol Type Description
46-47 C2+ Input 2nd-step boosting capacitor negative connection
48-49 C2- Input 2nd-step boosting capacitor positive connection
44-45 C1+ Input 1 st-step boosting capacitor negative connection
42-43 C1- Input 1 st-step boosting capacitor positive connection
68-69 VCNT Input External LCD power regulator voltage control through a resistive voltage divider.
IRS = Low: These can be used, because the internal resistors are disabled.
IRS = High: These can not be used.
56-57
58-59
61-62
63-64
65-66
1, 6, 25,
37, 60, 67,
83-84 ,
106-107,
264-265,
287
V1 Input
V2 Input
V3 Input
V4 Input
V5 Input
NC Open No Connection
LCD driver bias voltage. They can be supplied externally or generated by the
internal bias divider.
1: 7 bias 1: 9 bias
V1 1/7 x V5 1/9 x V5
V2 2/7 x V5 2/9 x V5
V3 5/7 x V5 7/9 x V5
V4 6/7 x V5 8/9 x V5
• Inputs LCD drive bias voltage when using an external LCD power supply circuit.
V5 ≥ V4, V3, V2, V1 > VSS
PRELIMINARY (February, 2001, Version 0.1) 10 AMIC Technology, Inc
Commands Table
W
D0:0 Normal: Column addresses 00 to 83H
correspond to segment outputs 1
D0:1 Reverse: Column addresses 00 to 83H
correspond to segment outputs
A31W65132 Series
Command
A0
E
Set Display ON/OFF 0 1 0 1 0 1 0 1 1 1 0 1 D0:0 Display OFF: Display goes out, regardless
Set Display Start Line
0 1 0 0 1
Page Address Set 0 1 0 1 0 1 1 Page Address
Upper 4 bits of Column
Address Set
Lower 4 bits of the
0 1 0 0 0 0 1
0 1 0 0 0 0 0
Column Address Set
Status Read
0 0 1
Display Data Write 1 1 0
Display Data Read 1 0 1
ADC Select 0 1 0 1 0 1 0 0 0 0
R/
Bit pattern
D7 D6
D5 D4 D3
D2 D1 D0
Comment
of the content of the display
data RAM
D0:1 Display ON: Normal Display
Display start line address
(0-63)
Sets the line address of the display data
RAM output to COM1
Sets the page address of the display data
(0-8)
Upper 4 bits of
Column Address
Lower 4 bits of the
Column Address
Status
Write Data in
Display Data RAM
Read Data from
Display Data RAM
RAM. Page 8 is assigned to the icon display
Sets upper 4 bits of the display data RAM
Column Address
Lower 4 bits of display data RAM column
Address
Status Read
Writes data of D0 to D7 in the display data RAM
Reads data from D0 to D7 from the display data
RAM
0
Reverses upper or lower display data RAM
column address
1
to 132
Display Normal/
0 1 0 1 0 1 0 0 1 1
Reverse
Display All-Lit ON/OFF
Common Output
0 1 0 1 0 1 0 0 1 0
0 1 0 1 1 0 0 0 1 * *
Sequence Select
Read Modify Write
0 1 0 1 1 1 0 0 0 0 0
End 0 1 0 1 1 1 0 1 1 1 0
Icon Only Display 0 1 0 1 1 0 1 1 0
1
0
1
0
1
*
Boosting
Control
Data
132 to 1
D0:0 Normal : “1” makes the display be lit
D0:1 Reverse : “0” makes the display be lit
The icon display is not reversed
D0:0 Normal Display
D0:1 Display All-Lit ON
D3:0 In a normal order COM1 to COM64
D3:1 In a reverse order COM64 to COM1
Increments display data RAM column
address only during writing
Read Modify Write Release.
D2:0 Normal Display (default)
D2:1 Icon Only Display
Boosting control data:
D1 D0:
00
FOSC
01
fOSC/2
10
fOSC/4 (default)
11
fOSC/8
PRELIMINARY (February, 2001, Version 0.1) 11 AMIC Technology, Inc
Commands Table (continued)
W
It does not affect the contents of the display data
After resetting, display starts according to the
ts the display start line register to the
2.Resets the column address counter to
5.Static icon off, static icon display register
7.V5 voltage regulator internal resistor ratio
8.LCD voltage command fine adjustment
Voltage regulator internal resistor (Ra/Rb) ratio,
lay register set command
must set after the static icon display ON
Static Icon Display Register
A31W65132 Series
Command
A0
E
Reset 0 1 0 1 1 1 0 0 0 1 0
Bias Selection
Power Supply Circuit
Operation Control
LCD Voltage Command
LCD Voltage Command
Fine Adjustment Data
V5 Voltage Regulator
Internal Resistor Ratio
Static Icon Display
Command Set
0 1 0 1 0 1 0 0 0 1 0 1 D0 = 0 : 1/9 Bias Selection (default)
0 1 0 0 0 1 0 1
0 1 0 1 0 0 0 0 0 0 1 The LCD Voltage Command Fine Adjustment
* * 0
0 1 0 0 0 1 0 0
0 1 0 1 0 1 0 1 1 0 0
R/
Bit pattern
D7 D6
D5 D4 D3
0
0
.
.
1
1
1
D2 D1 D0
0
.
.
1
0
.
1
Control
mode
0
0
.
1
1
0
0
.
.
1
1
1
Comment
RAM.
reset value:
1.Rese
1st line.
address 0.
3.Resets the page address counter to page 0.
4.Turns OFF the Read Modify Write.
off. D1, D0 = 0, 0
6.Common output sequence in normal order
set mode clear. D2~D0 = 1, 0, 0
data D5~D0 = 1, 0, 0, 0, 0, 0
D0 = 1 : 1/7 Bias Selection
LCD power supply circuit operation mode select
Data must set after the LCD Voltage Command
set
Minimum value
.
Maximum value (Total 64 level)
Small
Large
total 8 level
Static icon display command set :
D0 = 0 Static icon display OFF
D0 = 1 Static icon display ON
(The static icon disp
Set
(Double Byte Command)
Reference Voltage
Temperature
Coefficient Select
Power Save
NOP 0 1 0 1 1 1 0 0 0 1 1 Non operation command
0 1 0 1 1 1 0 0 1 0 1 0
PRELIMINARY (February, 2001, Version 0.1) 12 AMIC Technology, Inc
command set)
*
* * * * * Mode Static icon display register set :
D1 D0 = 0 0 :OFF
0 1 : Blinking , one second intervals
1 0 : Blinking , 0.5 second intervals
1 1 : ON
D0 : 0 0.05%/°C (default)
1
D0 : 1 0.2%/°C
D1 : 0 Internal VREG (default)
D1 : 1 External VREG
Set Display OFF then set Display all-lit ON
command
Operation of LCD Display Driver
1. Powering ON setting sequence
Recommended Command Setting Sequence:
(1) Set Display OFF : In order to prevent unnecessary characters from being displayed during powering ON of
the power .
When the master is turned on, the oscillator circuit is operable immediately. After the
powering on, it will be in All-OFF state.
(2) Set Display All-Lit OFF: Normal display operation.
(3) Set LCD Power Supply operation control
(4) Set Bias Select: 1. Bias selection setting
2. V5 voltage regulator internal resistor ratio setting
3. LCD voltage command and LCD voltage command fine adjustment data setting
(5) Set Reference Voltage Temperature Compensation Coefficient
(6) End Command Input
(7) ADC Select setting
(8) Set Display Normal/Reverse:
D0 : 0 Normal Display data "1" makes the display be lit.
D0 : 1 Reverse Display data "0" makes the display be lit.
(9) Set Display Start Line address: Changing the display start line allows for page change on the display screen
(10) Set Common Output Sequence
(11) Icon Only Display
(12) Static Icon Display select
(13) Display Data Write: After writing the display data, the column address is automatically incremented. To write
the display data in succession after setting the 1st column address to be written by the COLUMN ADDRESS
SETTING command, the column address is not needed to be set each time. The icon display data is valid for
only D0.
Write “L” or data to be displayed in all display data RAM before turning the display ON.
(14) Display ON
A31W65132 Series
as well as vertical smooth scroll.
2. Set Powering OFF, Power Save Mode
Set Powering OFF sequence:
(1) Set Display OFF
(2) Set Display All-Lit ON
(3) Set LCD Power Supply Circuit OFF
Power Save Mode:
The power save mode has two modes, one is sleep mode and the other is standby mode.
The MPU is still able to access the display data RAM when in power save mode.
Combination of Commands State
Display ON Display All-Lit OFF Normal display operation
Display ON Display All-Lit ON All-lit display
Display OFF Display All-Lit OFF AII-OFF
Static Icon Display ON Display OFF Display All-Lit ON Standby mode (Power save)
Static Icon Display OFF Display OFF Display All-Lit ON Sleep mode (Power save)
PRELIMINARY (February, 2001, Version 0.1) 13 AMIC Technology, Inc
A31W65132 Series
DOF
DOF
WR
CS1
CS1
RD WR
CS1
CS1
CS1
CS1
When in sleep mode, the command sleeps the system:
• Internal oscillating circuit and LCD power supply circuit are stopped.
• All LC drive circuit are stopped, the Segment and Common outputs are fixed at VSS level.
When in standby mode:
• Internal oscillating circuit continues to operate and LCD power supply circuits are stopped.
• The duty drive system LC circuits are stopped, the Segment and Common outputs are fixed at VSS level.
• The static icon drive system continues to operate.
When a reset command is set in the standby mode, the LCD system will enter the sleep mode.
When using an external power supply circuit, stop the external power supply circuit and float the LCD power supply
when the power save mode is started. When using an external bias resistor in order to reduce the current of power
save mode, attach a switching transistor which cuts the current flowing through the bias resistor. The LCD blinking
control pin
external power supply.
3. MPU Interface Select
The parallel 68-series, 80-series interface or serial interface can be selected by P/S, C68/80 pin setup:
will output Low signal when the power save mode is start. We can use the
P/S Pin
H
L don't care
C68/80 Pin
L
H
MPU Interface
80-series Interface selected
68-series Interface selected
Serial Interface selected
to stop the
3.1 MPU Parallel 68-Series and 80-Series Interface
The parallel interface consists of 8 bi-directional data pins (D0-D7), R/W (
the operating frequency of display RAM with that of the microprocessor, some pipeline processing is internally
performed which requires the insertion of a dummy read before the first actual display data read.
A31W65132 Pin Name
68-Series MPU Signal
80-Series MPU Signal
3.2 MPU Serial Interface
The serial interface consists of serial clock input SCL, serial data input SI and chip select
serial interface is selected by setting P/S to “L”, the instruction code is the same as for the parallel interface .By
setting
setting CS2 to “L”, it will reset the serial interface circuit and initialized the counter.
Data is input in the order of D7, D6, D5,....D0. The displayed data and commands are written at the rising edge of
the SCL. The A0 is detected every 8 rising edge of SCLK serial clock after the chip select pins is enabled.
D7 (SI) : Serial Data Input
D6 (SCL) : Serial Clock Input
D5 to D0 : Open
A0 : Select the command data or display data
to “L”, CS2 to “H”. the serial interface circuit enters an operating state. And by setting
A0
L
H
Operation
Command write
Display data write
A0 E
A0 E
A0
R/W
R/W
), A0, E(RD), CS In order to match
CS2
CS2
CS2 D0 - D7
D0 - D7
D0 - D7
, CS2, A0. When the
to “H’, or
PRELIMINARY (February, 2001, Version 0.1) 14 AMIC Technology, Inc
A31W65132 Series
CS1
4. Command Execution
When the input at D0-D7 is interpreted as a command and it will be decoded and written to the corresponding command
register. The user can input the commands continuously without confirming the busy flag of status command register
because the command is completely executed within the cycle time (tCYC) according to the timing characteristics of the
command input. But that re-inputting the command within the executed cycle time is inhibited. The busy flag is outputted
to D7 pin with the read instruction, “H” indicates the chip is in busy state.
5. Data Bus Select
When
6. Display Data RAM
The Display Data RAM is made of dual port RAM. The size of the RAM is 64 x 132 + 132 = 8580 bits.
Write “L” or data to be displayed in all display data RAM before turning the display ON.
is held at “H” level or CS2 is held at “L” level, the D0-D7 is in high impedance state.
68/80-Series
shared
A0
1
1
0 1
0 0
68-Series
R/W
1 0
0 1
80-Series
E
0 1
1 0
R/W
1
0
Description
Reads from Display Data RAM
Writes to Display Data RAM
Reads Status
Command Write to internal register
7. Accessing the Display Data RAM From MPU
In order to match the operating frequency of Display Data RAM with that of the MPU, a dummy read is required before the
first actual display data read. When the MPU reads the Display Data RAM, the first dummy read cycle stores the first read
data in the bus holder, and then at the next read cycle the MPU read the first read data from the bus holder.
It does not need a dummy cycle when MPU writes data to the Display Data RAM. When the MPU write data to Display
Data RAM, once the data is stored in the bus holder, then it is written to Display Data RAM before the next data write
cycle.
8. Set Column Address (higher, lower nibble)
This command specifies the column address (higher and lower nibble) of the Display Data RAM. The column address will
be incremented automatically by each data access after it is pre-set by the MPU. The incrementation of column addresses
stops with 83H.
9. Set Page Address (0-8)
This command positions the page address to 0 of 8 possible positions in Display Data RAM. Page 0-7 are the graphic
display area, and the page 8 are the icon display area. The icon display data is valid for only D0.
10. Set display start line (0-63)
The command is used to change the display page or smooth scroll.
With the display start line value equals to 0, D0 of page 0 is mapped to COM1. The display start line values of 0 to 63
are assigned to page 0 to 7.
PRELIMINARY (February, 2001, Version 0.1) 15 AMIC Technology, Inc
A31W65132 Series
11. Status Read
This command shows the status of A31W65132
BUSY : D7 =0 : The A31W65132 is not busy
1 : The A31W65132 is in internal operation or reset state.
ADC : D6 =0 : ADC Reverse : Column addresses 00 to 7FH correspond to segment outputs 132 to 1.
1 : ADC Normal : Column addresses 00 to 7FH correspond to segment outputs 1 to 132.
ON/OFF : D5 =0 : Display ON
1 : Display OFF
RESET : D4 =0 : In normal operation state
1 : Internal reset operation state
PSAVE : D3 =0 : In normal operation state
1 : In Power Save state
ICON : D2 =0 : In normal operation state
1 : In icon only display state
DREV : D1 =0 : Display Normal
1 : Display Reverse
ALON : D0 =0 : Normal display
1 : Display All-Lit ON
12. Common Output sequence select
Output sequence Common driving signal output in normal mode Common driving signal Output in reverse mode
1 COM1 COM64
2 COM2 COM63
3 COM3 COM62
.
.
16 COM16 COM49
17 COM17 COM48
.
.
63 COM63 COM2
64 COM64 COM1
.
.
.
.
.
.
.
.
13. Icon Only Display
D2 = 0 Normal Display
D2 = 1 Icon Only Display
D1 D0 Boosting frequency
0 0 fOSC
0 1
1 0
1 1
When D2=High, regardless of the content of the display data RAM, display icon only and LCD panel compelled to be off.
When reducing the boosting frequency, the gray scale of icon display differs depending on the panel size or the value of
the boosting capacitor.
14. Read Modify Write , END
Read Modify Write
This command puts the chip in read modify write mode. In this mode the column address is saved before entering the
mode, and is incremented by display data write but not by display data read. During the Read Modify Write mode, all
commands are usable except the Column address set command.
End
This command relieves the A31W65132 from read modify write mode. The column address that is saved before entering
read modify write mode will be restored.
fOSC/2
fOSC/4
fOSC/8
PRELIMINARY (February, 2001, Version 0.1) 16 AMIC Technology, Inc
A31W65132 Series
−
DOF
15. RC Oscillator Circuit
The built-in RC oscillator generates the clock for the boosting frequency, and is also used in the display timing. When
using the external clock (CLS = Low or M/S = Low), the external clock is input to CL pin.
16. Reference Voltage Temperature Compensation Coefficient Select
This command is to set one out of 2 different temperature coefficients in order to match various liquid crystal
temperature grades.
1REF2REF
∆VREF =
T2 > T1
17. The Reset Circuit
After reset by the
1. Display off
2. Display normal
3. ADC select normal
4. Power supply circuit operation control D2, D1, D0 = 0, 0, 0
5. Serial interface internal counter and register clear
6. LCD power supply bias rate selection = 1/9
7. All indicator lamps-on OFF (D0 = Low)
8. Power saving clear
9. V5 voltage regulator internal resistors Ra, Rb separation
10. Turn off the Read Modify Write
11. Resets the display start line register to 1st line
12. Resets the column address counter to address 0
13. Resets the page address counter to page0
14. The SEG and COM output conditions: SEG = V2/V3, COM = V1/V4. While
are fixed to High, and the oscillator and display timing generator stop. The VSS level is output from SEG and COM
outputs.
15. Static icon off, and static icon display register = off (D1, D0 = 0, 0)
16. Common output sequence in normal order
17. V5 voltage regulator internal resistor ratio set mode clear D2~D0 = 1, 0, 0
18. LCD voltage command fine adjustment data D5~D0 = 1, 0, 0, 0, 0, 0
19. Reference voltage temperature coefficient select 0.05%/°C
20. Icon Only Display command: Normal display, Boosting control D1, D0 = 1, 0
pin (Low enable), the A31W65132 return to the default status as follows:
RES
12
TT
−
)I(TIV)I(TIV
= Low, the CL, FR, FRS and
RES
18. LCD Power Supply Circuit
The LCD power supply circuit generates the LCD voltage needed for display output, which is controlled by power supply
operation control command. It consists of:
1. Double / triple / quad DC-DC voltage converter
2. Internal resistors and voltage command fine adjustment circuit (64 level) for the V5 voltage regulator
3. LCD bias resistor and voltage follower
D2
H
L
L
L
PRELIMINARY (February, 2001, Version 0.1) 17 AMIC Technology, Inc
D1 D0 Double/Triple/
Quad Circuit
H
L
H
L
H
L
H
H
ON
OFF
OFF
OFF
Voltage Regulator
Circuit
ON
OFF
ON
OFF
LCD Bias Resistor/
Voltage Follower Circuit
ON
OFF
ON
ON
A31W65132 Series
18.1 Double / Tripler / Quad
It is the 2X, 3X , 4X DC-DC voltage converter. Please refer to application notes.
C1
+
+
C1
C1
+
+
C1
4 x step-up voltage circuit 3 x step-up voltage circuit 2 x step-up voltage circuit
VSS
VOUT
C3+
C1-
C1+
C2+
C2-
C1
+
C1
+
+
C1
VSS
VOUT
C3+
C1-
C1+
C2+
C2-
C1
+
C1
+
OPEN
Quad VOUT = 12V
VSS
VOUT
C3+
C1-
C1+
C2+
C2-
Triple VOUT = 9V
Double VOUT = 6V
VDD=3V
VSS
Example of Booster Output
18.2 LCD Voltage Adjustment
There are two methods of adjusting the LCD voltage as follows:
18.2.1 Voltage Regulator
Voltage regulator output V5 is adjusted by internal Ra/Rb resistors ratio or externally attached Ra and Rb.
VREF(V) = (1-α /162) x VREG
Ra + Rb
V5=
Ra
X VREF (V)
VREF
-
+
V5
VCNT
Ra
Rb
VSS
PRELIMINARY (February, 2001, Version 0.1) 18 AMIC Technology, Inc
A31W65132 Series
HPM
Temperature Coefficient VREG
0.05%/°C
0.2%/°C
External VREG input VRS
V5 Voltage regulator Internal Resistor Ratio Register Value and (Ra+Rb)/Ra Ratio (for reference)
Internal Resistance Ratio Register Internal (Ra+Rb)/Ra Ratio
D2 D1 D0 0.05 0.2 VREG External Input
0 0 0 3.0 1.3 1.5
0 0 1 3.5 1.5 2.0
0 1 0 4.0 1.8 2.5
0 1 1 4.5 2.0 3.0
1 0 0 5.0 2.3 3.5
1 0 1 5.5 2.5 4.0
1 1 0 6.0 2.8 4.5
1 1 1 6.4 3.0 5.0
18.2.2 LCD Voltage Command Fine Adjustment control
Software control of 64 voltage levels (α) adjustment of V5 voltage by set 6 bits of the data bus. It can adjust the
LCD contrast.
LCD voltage command is a two-byte command used as a pair with the LCD voltage command and LCD
voltage command fine adjustment control, and both command must be issued on after the other.
2.1Voltage
4.9 Voltage
Ta = 25°°C
18.3 Static Icon Display
This controls the static drive system display. This is used when one of the static indicator LCD electrodes is
connected to the FR terminal, and the other is connected to the FRS terminal.
The Static Icon Display command set ON is a two-byte command used as a pair with the Static Icon Display
command set and Static Icon Display register set.
The Static Icon Display command set OFF is a single byte command.
18.4 LCD Bias voltage
When use built-in LCD bias resistor, Software can control the 1/9, 1/7 bias ratio to match the characteristic of LCD
panel.
18.5 Voltage Follower
The voltage follower buffers the LCD bias voltage created by the built-in bias resistor, and supplies it to the LCD
drive circuit.
18.6 High power mode
When the LCD with large loads, the high power mode power supply (set
LCD display.
= Low) can improve the quality of the
PRELIMINARY (February, 2001, Version 0.1) 19 AMIC Technology, Inc
Interface
1. Parallel Interface
1.1 Display Data Write ( the 80-Series interface)
R/W
MP
A31W65132 Series
n
Internal
Timing
Data
Bus Holder
R/W
Internal Busy Flag
1.2 Display Data Read (the 80-Series interface)
R/W
MP
E
Data
R/W
N
n
Address set
address N
n+1
X
n+1
Dummy
read
n+2 n+3
n n+1
Data read
address N
n+3n+2
Data read
address N+1
E
Internal
Timing
Column address
Bus Holder
Internal Busy Flag
N N+1 N+2
n+2n+1nX
PRELIMINARY (February, 2001, Version 0.1) 20 AMIC Technology, Inc
A31W65132 Series
2 Serial Interface
Serial Interface Display Data Write Timing
CS1
CS2
SI (D7)
SCL (D6)
A0
Notes:
1. The user can not reading from A31W65132 when in serial interface mode.
2. A0=High, the data is display data, A0=Low, the data is command data.
The A0 signal is sampled every 8th rising edge of SCL clock, when the chip becomes active in serial interface mode.
3. The counter and the shift register are reset to the default value when the chip is not active.
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2
1 2 3 4 5 6 7 8 9 10 11 12 13 14
PRELIMINARY (February, 2001, Version 0.1) 21 AMIC Technology, Inc
A31W65132 Series
Display Data RAM vs Address
Page
Address
D0
D1
D2
0, 0, 0, 0
0, 0, 0, 1
0, 0, 1, 0
0, 0, 1, 1
0, 1, 0, 0
0, 1, 0, 1
0, 1, 1, 0
0, 1, 1, 1
1, 0, 0, 0
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
00 01 02 03 04 05 06 07
Column
Address
83 82 81 80 7F 7E 7D 7C
Page0
Page1
Page2
Page3
Page4
Page5
Page6
Page7
Page8
..............
..............
3F 40 82 83
......
.... .... ......
01 00
Line
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
ADC
D0=
"0"
ADC
D0=
"1"
An example of common output
executing display start from
the line address 30H.
Display
Start
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COMICN
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
SEG Pin
1 2 3 4 5 6 7 8...............
.... .... ......
131 132
PRELIMINARY (February, 2001, Version 0.1) 22 AMIC Technology, Inc
A31W65132 Series
LCD Drive Output Waveform (Waveform B)
The following is an example of how the common and segment drivers may be connected to a LCD panel.
1 2
6564636261
VDD
VSSFR
V5
V4
V3
V2
V1
VSS
V5
V4
V3
V2
V1
VSS
CL
COM1
COM2
16564 2 3 4 5 1 2 3 4 5
6564636261
V5
V4
SEG1
SEG2
COM1
- SEG1
COM1
- SEG2
V3
V2
V1
VSS
V5
V4
V3
V2
V1
VSS
V5
V4
V3
V2
V1
VSS
-V1
-V2
-V3
-V4
-V5
V5
V4
V3
V2
V1
VSS
-V1
-V2
-V3
-V4
-V5
PRELIMINARY (February, 2001, Version 0.1) 23 AMIC Technology, Inc
Examples of External Bias Resistor Connection vs LCD Drive Waveform
γ
≤
1/7 or 1/9 Bias
SEG Waveform COM Waveform
M M M M
V5
Ra1
V4
Ra1
Ra2
Ra1
Ra1
V3
V2
V1
VSS
Bias
=
A31W65132 Series
12 Ra Ra γ=
0
Ra1
Ra1+ Ra1+ Ra2 +Ra1 +Ra1
1
=
γ+
4
PRELIMINARY (February, 2001, Version 0.1) 24 AMIC Technology, Inc
A31W65132 Series
Absolute Maximum Ratings
VSS = 0.0V
Parameter Symbol Ratings Unit
Supply voltage VDD -0.4 to +7.0 V
LCD drive voltage 1 V5, VOUT -0.4 to +18 V
LCD drive voltage 2 V1, V2, V3, V4 -0.4 to V5 V
Input voltage VIN -0.4 to VDD+0.4 V
Output voltage VOUT -0.4 to VDD+0.4 V
Operating temperature range Topr -40 to +85
Chip -55 to +125 Storage temperature
range
Note 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and the functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Note 2 Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note 3 When connecting a bias resistor externally, set the LCD power supply voltage so that the state is changed to V5 ≥VDD.
TAB
Tstg
-55 to +100
°C
°C
PRELIMINARY (February, 2001, Version 0.1) 25 AMIC Technology, Inc
VDD
VDD
DC Characteristics
Item Symbol Condition
Operating
Voltage (1)
Operating
Voltage (2)
High-level Input
Voltage
Low-level Input
Voltage
High-level Output
Voltage
Low-level Output
Voltage
Input leakage
Current
Output leakage
Current
Liquid Crystal Driver
ON Resistance
Static Consumption
Current
Output Leakage
Current
Input Terminal
Capacitance
Oscillator
Frequency
Supply Step-up
Output Voltage
Circuit
Voltage
Regulator Circuit
Operating
Voltage
Voltage Follower
Internal Power
Circuit Operating
Voltage
Base Voltage VREG0
Recommended
Voltage
Possible
Operating
Voltage
Possible
Operating
Voltage
Possible
Operating
Voltage
Possible
Operating
Voltage
Internal
Oscillator
External
Input
A31W65132 Series
Unless otherwise specified, VSS = 0 V, VDD = 3.0 V ± 10%, Ta = -40 to 85°C
Rating
Min. Typ. Max.
VDD
V5
V1, V2
V3, V4
(Relative to VSS)
(Relative to VSS)
(Relative to VSS)
VIHC
VILC
VOHC
IOH = -0.5 mA
VOLC
ILI
IOL = 0.5 mA
VIN = VDD or VSS -1.0
ILO
RON
Ta = 25°C
(Relative To VSS)
ISSQ
I5Q
CIN
fOSC
V5 = 18.0 V
(Relative To VSS)
Ta = 25°C f = 1 MHz
Ta = 25°C
fCL
VOUT (Absolute value referenced to
V5 = 14.0 V
V5 = 8.0 V
2.4
-
4.5
0
0.6 × V5
0.8 ×
VSS
0.8 ×
VSS
-3.0
-
-
-
-
-
18
18
- -
-
-
-
-
-
-
-
-
-
-
-
2.0
3.2
0.01
0.01
5.5
-
16
0.4 × V5
V5
VDD
0.2 × VDD
VDD
0.2 × VDD
1.0
3.0
3.5
5.4
5
15
5.0 8.0 pF
22
22
26
26
16.5 V VOUT
Units
KΩ
KΩ
KHz
KHz
VSS)
VOUT (Absolute value referenced to
6
-
16.5 V VOUT
VSS)
V5 (Absolute value referenced to
4.5
-
16 V V5*9
VSS)
VREG1
Ta = 25°C
(Relative to VSS)
0.05%/°C
0.2%/°C
2.04
4.65
2.10
4.9
2.16
5.15
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
V
V
Applicable
Pin
1
VDD*
VDD*1
V5
V1, V2
V3, V4
*3
*3
*4
*4
*5
*5
SEGn
COMn*7
VSS
V5
*8
CL
*10
*10
PRELIMINARY (February, 2001, Version 0.1) 26 AMIC Technology, Inc
A31W65132 Series
up voltage.
up voltage.
DC Characteristics (continued)
. Dynamic Consumption Current (1), During Display, with the Internal Power Supply OFF
Current consumed by the total ICs when an external power supply is used
. Dynamic Consumption Current (2), During Display, with the Internal Power Supply ON
Ta = 25°C
Item Symbol
A31W65132
Sleep mode IDDS1
Standby mode IDDS2
IDD (1)
IDD (2)
VDD=5.0 V, V5=11.0 V - 18 30
VDD=3.0 V, V5=11.0 V - 16 27
VDD=5.0 V, V5=11.0 V - 23 38
VDD=3.0 V, V5=11.0 V - 21 35
V5 =11.0 V
V5 =11.0 V
V5 =11.0 V
VDD=3.0V, Quad step-up voltage.
V5 =11.0 V
Condition
Normal Mode
High-Power Mode - 114 190
Normal Mode
High-Power Mode - 138 230
Normal Mode
High-Power Mode - 127 212
Normal Mode
High-Power Mode - 153 255
-
-
Rating
Min. Typ. Max.
67 112 VDD=5.0V, Triple step-
-
81 135 VDD=3.0V, Quad step-up voltage.
-
81 135 VDD=5.0V, Triple step-
-
96 160
-
- 0.01 5
- 4 8
Units Notes
µA
µA
µA
µA
*11
*12
*12
*13
(Consumption Current at Time of Power Saver Mode, VSS=0V, VDD=3.0V±10%)
. The Relationship between Oscillator Frequency fOSC, Display Clock Frequency fCL and the Liquid Crystal Frame Rate
Frequency fFR
Item fCL fFR
When the internal oscillator circuit is used
A31W65132
When the internal oscillator circuit is not used External input
(fFR is the liquid crystal alternating current period, and not the FR signal period.)
fOSC
4
fOSC
65 x 4
PRELIMINARY (February, 2001, Version 0.1) 27 AMIC Technology, Inc
A31W65132 Series
WR
CS1
HPM
CS1
HPM
DOF
Notes:
1. While a broad range of operating voltages is guaranteed, performance cannot be guaranteed if there are sudden
fluctuations to the voltage while the MPU is being accessed.
2. This applies when the external power supply is being used.
3. The A0, D0 to D5, D6 (SCL), D7 (SI), RD (E),
IRS, and
4. The D0 to D7, FR, FRS,
5. The A0, RD (E), WR (R/W),
6. Applies when the D0 to D5, D6 (SCL), D7 (SI), CL, FR, and
7. These are the resistance values for when a 0.1 V voltage is applied between the output terminal SEGn or COMn and the
various power supply terminals (V1, V2, V3, and V4). These are specified for the operating voltage (3) range.
RON = 0.1 V/D I (Where D I is the current that flows when 0.1 V is applied while the power supply is ON.)
8. See the relationship between the oscillator frequency and the frame rate frequency.
9. The V5 voltage regulator circuit regulates within the operating voltage range of the voltage follower.
10. This is the internal voltage reference supply for the V5 voltage regulator circuit. In the A31W65132, the temperature
range can come in three types as VREG options: (1) approximately 0.05%/°C
11., 12. It indicates the current consumed on ICs alone when the internal oscillator circuit and display are turned on.
The A31W65132 is 1/9 biased.
Does not include the current due to the LCD panel capacity and wiring capacity.
Applicable only when there is no access from the MPU.
12. It is the value on a model having the VREG option temperature gradient is 0.05%/°C when the V5 voltage
regulator internal resistor is used.
13. When consumption current in Power Saver Mode is measured, the A0, RD (E), WR (R/W), D0~D7 terminals must be
fixed in H or L.
terminals.
DOF
, and CL terminals.
, CS2, CLS, M/S, C68/80, P/S,
(2) 0.2%/°C
(3) external input.
(R/W),
, CS2, CLS, CL, FR, M/S, C68/80, P/S,
, IRS, and
RES
terminals are in a high impedance state.
terminals.
DOF, RES
,
PRELIMINARY (February, 2001, Version 0.1) 28 AMIC Technology, Inc
Timing Characteristics
WR
RD
WR
RD
RD
System Bus Read/Write Characteristics 1 (for the 8080 Series MPU)
A0
A31W65132 Series
tAW8
CS
(CS2="1")
tCYC8
tCCR, tCCLW
WR, RD
tDS8
D0 to D7
(Write)
tACC8
D0 to D7
(Read)
Item Signal Symbol Condition
Address hold time
Address setup time
System cycle time A0 tCYC8 166 - ns
Control L pulse width (WR)
Control L pulse width (RD)
Control H pulse width (WR)
Control H pulse width (RD)
Data setup time D0 to D7 tDS8 30 - ns
Address hold time tDH8 10 - ns
access time
Output disable time tOH8 5 50 ns
A0 tAH8
tAW8
tACC8 CL = 100pF - 70 ns
tcclw 30 - ns
tCCLR 70 - ns
tCCHW 30 - ns
tCCHR 30 - ns
tAH8
tCCHR, tCCHW
tDH8
tOH8
(VDD = 4.5V to 5.5V Ta=-40 to 85°C)
Min. Max.
0
0
Rating
-
-
Units
ns
ns
PRELIMINARY (February, 2001, Version 0.1) 29 AMIC Technology, Inc
A31W65132 Series
WR
RD
WR
RD
RD
WR
RD
WR
RD
RD
CS1
(VDD = 2.7V to 4.5V Ta=-40 to 85°C)
Item Signal Symbol Condition
Address hold time
Address setup time
System cycle time A0 tCYC8 300 - ns
Control L pulse width (WR)
Control L pulse width (RD)
Control H pulse width (WR)
Control H pulse width (RD)
Data setup time D0 to D7 tDS8 40 - ns
Address hold time tDH8 15 - ns
access time
Output disable time tOH8 10 100 ns
Item Signal Symbol Condition
Address hold time
Address setup time
System cycle time A0 tCYC8 1000 - ns
Control L pulse width (WR)
Control L pulse width (RD)
Control H pulse width (WR)
Control H pulse width (RD)
Data setup time D0 to D7 tDS8 80 - ns
Address hold time tDH8 30 - ns
access time
Output disable time tOH8 10 200 ns
Notes:
1. The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr + tf) ≤ (tCYC8 - tCCLW - tCCHW) for (tr + tf) ≤ (tCYC8 - tCCLR - tCCHR) are specified.
2. All timing is specified using 20% and 80% of VDD as the reference.
3. tCCLW and tCCLR are specified as the overlap between
A0 tAH8
tAW8
tACC8 CL = 100pF - 140 ns
A0 tAH8
tACC8 CL = 100pF - 280 ns
tCCLW 60 - ns
tCCLR 120 - ns
tCCHW 60 - ns
tCCHR 60 - ns
tAW8
tCCLW 120 - ns
tCCLR 240 - ns
tCCHW 120 - ns
tCCHR 120 - ns
being “L” (CS2 = “H”) and WR and RD being at the “L” level.
0
(VDD = 2.4V to 2.7V Ta=-40 to 85°C)
0
Rating
Min. Max.
-
0
Rating
Min. Max.
0
-
-
-
Units
ns
ns
Units
ns
ns
PRELIMINARY (February, 2001, Version 0.1) 30 AMIC Technology, Inc
Timing Characteristics (continued)
System Bus Read/Write Characteristics 2 (for the 6800 Series MPU)
A0
R/W
tAW6
CS1
(CS2="1")
tCYC6
tEWHR, tEWHW
A31W65132 Series
tAH6
E
tDS6
D0 to D7
(Write)
tACC6
D0 to D7
(Read)
tEWLR, tEWLW
tDH6
tOH6
(VDD = 4.5V to 5.5V Ta=-40 to 85°C)
Item Signal Symbol Condition
Address hold time
Address setup time
A0 tAH6
tAW6
0
Rating
Min. Max.
-
0
-
Units
ns
ns
System cycle time A0 tCYC6 166 - ns
Data setup time D0 to D7 tDS6 30 - ns
Data hold time tDH6 10 - ns
Access time tACC6 CL = 100pF - 70 ns
Output disable time tOH6 10 50 ns
Enable H pulse time Read
Write
Enable L pulse time Read
Write
E tEWHR
tEWHW
E tEWLR
tEWLW
70
30
30
30
-
-
-
-
ns
ns
ns
ns
PRELIMINARY (February, 2001, Version 0.1) 31 AMIC Technology, Inc
A31W65132 Series
CS1
(VDD = 2.7V to 4.5V Ta=-40 to 85°C)
Item Signal Symbol Condition
Address hold time
Address setup time
System cycle time A0 tCYC6 300 - ns
Data setup time D0 to D7 tDS6 40 - ns
Data hold time tDH6 15 - ns
Access time tACC6 CL = 100pF - 140 ns
Output disable time tOH6 10 100 ns
Enable H pulse time Read
Write
Enable L pulse time Read
Write
Item Signal Symbol Condition
Address hold time
Address setup time
System cycle time A0 tCYC6 1000 - ns
Data setup time D0 to D7 tDS6 80 - ns
Data hold time tDH6 30 - ns
Access time tACC6 CL = 100pF - 280 ns
Output disable time tOH6 10 280 ns
Enable H pulse time Read
Write
Enable L pulse time Read
Write
Notes:
1. The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr + tf) ≤ (tCYC6 - tEWLW - tEWHW) for (tr + tf) ≤ (tCYC6 - tEWLR - tEWHR) are specified.
2. All timing is specified using 20% and 80% of VDD as the reference.
3. tEWLW and tEWLR are specified as the overlap between
A0 tAH6
tAW6
E tEWHR
tEWHW
E tEWLR
tEWLW
A0 tAH6
tAW6
E tEWHR
tEWHW
E tEWLR
tEWLW
being “L” (CS2 = “H”) and E.
0
120
60
(VDD = 2.4V to 2.7V Ta=-40 to 85°C)
0
240
120
Rating
Min. Max.
-
0
60
60
Rating
Min. Max.
0
120
120
-
-
-
-
-
-
-
-
-
-
-
Units
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
PRELIMINARY (February, 2001, Version 0.1) 32 AMIC Technology, Inc
A31W65132 Series
t
t
The Serial Interface
CS1
(CS2="1")
A0
SCL
SI
CSS
tSAS tSAH
tSCYC
tSLW
trtf
tSDHtSDS
CSH
tSHW
(VDD = 4.5V to 5.5V Ta=-40 to 85°C)
Item Signal Symbol Condition
Serial Clock Period
SCL "H" pulse width
SCL "L" pulse width
SCL tSCYC
tSHW
tSLW
200
Rating
Min. Max.
75
75
-
-
Units
ns
ns
ns
Access setup time A0 tSAS 50 - ns
Address hold time tSAH 100 - ns
Data setup time SI tSDS 50 - ns
Data hold time tSDH 50 - ns
CS-SCL time CS tCSS
tCSH
100
100
-
-
ns
ns
PRELIMINARY (February, 2001, Version 0.1) 33 AMIC Technology, Inc
A31W65132 Series
(VDD = 2.7V to 4.5V Ta=-40 to 85°C)
Item Signal Symbol Condition
Serial Clock Period
SCL "H" pulse width
SCL "L" pulse width
Access setup time A0 tSAS 150 - ns
Address hold time tSAH 150 - ns
Data setup time SI tSDS 100 - ns
Data hold time tSDH 100 - ns
CS-SCL time CS tCSS
Item Signal Symbol Condition
Serial Clock Period
SCL "H" pulse width
SCL "L" pulse width
Access setup time A0 tSAS 250 - ns
Address hold time tSAH 250 - ns
Data setup time SI tSDS 150 - ns
Data hold time tSDH 150 - ns
CS-SCL time CS tCSS
Notes:
1. The input signal rise and fall time (tr, tf) are specified at 15ns or less.
2. All timing is specified using 20% and 80% of VDD as the standard.
SCL tSCYC
tSHW
tSLW
tCSH
SCL tSCYC
tSHW
tSLW
tCSH
250
150
(VDD = 2.4V to 2.7V Ta=-40 to 85°C)
400
250
Rating
Min. Max.
100
100
150
Rating
Min. Max.
150
150
250
-
-
-
-
-
-
-
-
-
Units
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
PRELIMINARY (February, 2001, Version 0.1) 34 AMIC Technology, Inc
A31W65132 Series
Display Control Output Timing
CL
(OUT)
tDFR
FR
(VDD = 4.5V to 5.5V Ta=-40 to 85°C)
Item Signal Symbol Condition
FR delay time FR tDFR CL = 50 pF - 10 40 ns
Item Signal Symbol Condition
FR delay time FR tDFR CL = 50 pF - 20 80 ns
Item Signal Symbol Condition
FR delay time FR tDFR CL = 50 pF - 50 200 ns
Notes:
1. Valid only when the master mode is selected.
2. All timing is based on 20% and 80% of VDD.
Min. Typ. Max.
(VDD = 2.7V to 4.5V Ta=-40 to 85°C)
Min. Typ. Max.
(VDD = 2.4V to 2.7V Ta=-40 to 85°C)
Min. Typ. Max.
Rating
Rating
Rating
Units
Units
Units
PRELIMINARY (February, 2001, Version 0.1) 35 AMIC Technology, Inc
Reset Timing
RES
A31W65132 Series
tRW
tR
Internal
status
Item Signal Symbol Condition
Reset time tR - - 0.5
Reset "L" pulse width
Item Signal Symbol Condition
Reset time tR - - 1
Reset "L" pulse width
Item Signal Symbol Condition
Reset time tR - - 1.5
Reset "L" pulse width
Note: All timing is specified with 20% and 80% of VDD as the standard.
RES
RES
RES
tRW 0.5 - -
tRW 1 - -
tRW 1.5 - -
During reset Reset complete
(VDD = 4.5V to 5.5V Ta=-40 to 85°C)
Rating
Min. Typ. Max.
(VDD = 2.7V to 4.5V Ta=-40 to 85°C)
Rating
Min. Typ. Max.
(VDD = 2.4V to 4.5V Ta=-40 to 85°C)
Rating
Min. Typ. Max.
Units
µs
µs
Units
µs
µs
Units
µs
µs
PRELIMINARY (February, 2001, Version 0.1) 36 AMIC Technology, Inc
Examples of Applications of LCD Power Supply
1. When used all of the step-up circuit, voltage regulating circuit and V/F circuit
A31W65132 Series
. When the voltage regulator internal resistor
is used.
(Example 4x step-up)
VDD
IRS M/S
VSS
VSS
C1
C1
C1
C1
VOUT
C3+
C1-
C1+
C2+
C2-
V5
VCNT
VSS
VSS
C2
C2
C2
C2
C2
V1
V2
V3
V4
V5
. When the voltage regulator internal resistor
is not used.
(Example 4x step-up)
VDD
IRS M/S
VSS
R3
R2
R1
C2
C2
C2
C2
C2
C1
C1
C1
C1
VOUT
C3+
C1-
C1+
C2+
C2-
V5
VCNT
VSS
V1
V2
V3
V4
V5
VSS
VSS
2. When the voltage regulator circuit and V/F circuit alone used
. When the V5 voltage regulator internal resistor
is not used.
VDD
. When the V5 voltage regulator internal resistor
is used.
VDD
IRS M/S
VSS
VSS
External
power
supply
VOUT
C3+
C1-
C1+
VSS
C2+
C2-
VSS
R3
R2
R1
C2
C2
C2
C2
C2
V5
VCNT
VSS
VSS
V1
V2
V3
V4
V5
External
power
supply
C2
C2
C2
C2
C2
IRS M/S
VSS
VOUT
C3+
C1C1+
C2+
C2-
V5
VCNT
VSS
V1
V2
V3
V4
V5
PRELIMINARY (February, 2001, Version 0.1) 37 AMIC Technology, Inc
Examples of Applications of LCD Power Supply (continued)
Ω
Ω
A31W65132 Series
3. When the V/F circuit alone is used
VDD
IRS M/S
VSS
VSS
External
power
supply
VOUT
C3+
C1-
C1+
C2+
C2-
V5
VCNT
VSS
C2
C2
C2
C2
C2
VSS
V1
V2
V3
V4
V5
5. When the built-in power circuit is used to drive a
liquid crystal panel heavily loaded with AC or DC,
it is recommended to connect an external resistor
to stabilize potentials of V1, V2, V3 and V4 which
are output from the built-in voltage follower.
VSS
VSS, V0
4. When the built-in power is not used
VSS
IRS M/S
VSS
VOUT
C3+
C1C1+
C2+
C2-
V5
VCNT
VSS
VSS
V1
External
power
supply
V2
V3
V4
V5
Example of shared reference settings
When V5 can vary between 8 and 12V
Item Set value Units
C1
C2
1.0 to 4.7
0.01 to 1.0
VDD
uF
uF
R4
R4
C2
V1
V2
V3
V4
R4R4
V5
Reference set value R4: 100K ~ 1M
It is recommended to set an optimum
resistance value R4 taking the liquid crystal
display and the drive waveform.
Notes:
1. Because the VR terminal input impedance is high, use short leads and shielded lines.
2. C1 and C2 are determined by the size of the LCD being driven. Select a value that will stabilize the liquid crystal drive voltage.
Example of the Process by which to Determine the Settings:
• Turn the voltage regulator circuit and voltage follower circuit ON and supply a voltage to VOUT from the outside.
• Determine C2 by displaying a LCD pattern with a heavy load (such as horizontal stripes) and selecting a C2 that
stabilizes the liquid crystal drive voltages (V1 to V5). Note that all C2 capacitors must have the same capacitance value.
• Next turn all the power supplies ON and determine C1.
PRELIMINARY (February, 2001, Version 0.1) 38 AMIC Technology, Inc
A31W65132 Series
Connections Between LCD Drivers (reference examples)
The liquid crystal display area can be enlarged with ease through the use of multiple A31W65132 series chips. Use a same
equipment type.
1. A31W65132 (master) ↔↔ A31W65132 (slave)
VDD
M/S
M/S
FR
CL
Master
A31W65132
The liquid crystal display area can be enlarged with ease through the use of multiple A31W65132 series chips. Use a same
equipment type, in the composition of these chips.
1. Single-chip Structure
DOF
Output Input
FR
CL
DOF
Slave
A31W65132
VSS
132 X 65 Dots
SEG
A31W65132 Master
COMCOM
2. Double-chip Structure, # 1
264 X 65 Dots
SEGCOM SEG COM
A31W65132 SlaveA31W65132 Master
PRELIMINARY (February, 2001, Version 0.1) 39 AMIC Technology, Inc
Ordering Information
Part No. Package
A31W65132 Series
A31W65132C
A31W65132T
COG
TCP
PRELIMINARY (February, 2001, Version 0.1) 40 AMIC Technology, Inc
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