Datasheet A29L800UV, A29L800UV-70, A29L800UM, A29L800UM-70, A29L800UG-90U Datasheet (AMICC)

A29L800 Series

1M X 8 Bit / 512K X 16 Bit CMOS 3.0 Volt-only,

Preliminary Boot Sector Flash Memory

Features

n Single power supply operation

- Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications

n Access times:

- 70/90 (max.)

n Current:

- 9 mA typical active read current

- 20 mA typical program/erase current

- 200 nA typical CMOS standby

- 200 nA Automatic Sleep Mode current

n Flexible sector architecture

- 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX15 sectors

- 8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX15 sectors

- Any combination of sectors can be erased

- Supports full chip erase

- Sector protection:

A hardware method of protecting sectors to prevent
any inadvertent program or erase operations within
that sector. Temporary Sector Unprotect feature
allows code changes in previously locked sectors

n Extended operating temperature range: -45°C ~ +85°C

for -U series

n Unlock Bypass Program Command

- Reduces overall programming time when issuing
multiple program command sequence

n Top or bottom boot block configurations available
n Embedded Algorithms

- Embedded Erase algorithm will automatically erase
the entire chip or any combination of designated
sectors and verify the erased sectors

- Embedded Program algorithm automatically writes
and verifies data at specified addresses

n Typical 100,000 program/erase cycles per sector
n 20-year data retention at 125°C

- Reliable operation for the life of the system

n Compatible with JEDEC-standards

- Pinout and software compatible with single-power­supply Flash memory standard

- Superior inadvertent write protection

n

n Ready /

- Provides a hardware method of detecting completion

n Erase Suspend/Erase Resume

n Hardware reset pin (

n Package options

Polling and toggle bits

Data

- Provides a software method of detecting completion
of program or erase operations

pin (RY / BY)

BUSY

of program or erase operations (not available on 44­pin SOP)

- Suspends a sector erase operation to read data from,

or program data to, a non-erasing sector, then
resumes the erase operation

RESET

- Hardware method to reset the device to reading array
data

- 44-pin SOP or 48-pin TSOP (I) or 48-ball TFBGA

)

PRELIMINARY (September, 2002, Version 0.2) 1 AMIC Technology, Inc.

A29L800 Series

General Description

The A29L800 is an 8Mbit, 3.0 volt-only Flash memory
organized as 1,048,576 bytes of 8 bits or 524,288 words of
16 bits each. The 8 bits of data appear on I/O0 - I/O7; the 16
bits of data appear on I/O0~I/O15. The A29L800 is offered in
48-ball TFBGA, 44-pin SOP and 48-Pin TSOP packages.
This device is designed to be programmed in-system with the
standard system 3.0 volt VCC supply. Additional 12.0 volt
VPP is not required for in-system write or erase operations.
However, the A29L800 can also be programmed in standard
EPROM programmers.
The A29L800 has the first toggle bit, I/O6, which indicates
whether an Embedded Program or Erase is in progress, or it
is in the Erase Suspend. Besides the I/O6 toggle bit, the
A29L800 has a second toggle bit, I/O2, to indicate whether
the addressed sector is being selected for erase. The
A29L800 also offers the ability to program in the Erase
Suspend mode. The standard A29L800 offers access times
of 70 and 90ns, allowing high-speed microprocessors to
operate without wait states. To eliminate bus contention the

device has separate chip enable (CE), write enable (WE)
and output enable (OE) controls.

The device requires only a single 3.0 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
The A29L800 is entirely software command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register contents
serve as input to an internal state-machine that controls the
erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and
erase operations. Reading data out of the device is similar to
reading from other Flash or EPROM devices.

Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the
program pulse widths and verifies proper program margin.

Device erasure occurs by executing the proper erase
command sequence. This initiates the Embedded Erase
algorithm - an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper erase margin. The Unlock Bypass mode
facilitates faster programming times by requiring only two
write cycles to program data instead of four.

The host system can detect whether a program or erase
operation is complete by observing the RY / BY pin, or by
reading the I/O7 (

After a program or erase cycle has been completed, the
device is ready to read array data or accept another
command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data
contents of other sectors. The A29L800 is fully erased when
shipped from the factory.
The hardware sector protection feature disables operations
for both program and erase in any combination of the
sectors of memory. This can be achieved via programming
equipment.

The Erase Suspend/Erase Resume feature enables the user
to put erase on hold for any period of time to read data from,
or program data to, any other sector that is not selected for
erasure. True background erase can thus be achieved.

The hardware
progress and resets the internal state machine to reading
array data. The
circuitry. A system reset would thus also reset the device,

enabling the system microprocessor to read the boot-up
firmware from the Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of time,
the device enters the automatic sleep mode. The system can
also place the device into the standby mode. Power
consumption is greatly reduced in both these modes.

Polling) and I/O6 (toggle) status bits.

Data

RESET

RESET

pin terminates any operation in

pin may be tied to the system reset

PRELIMINARY (September, 2002, Version 0.2) 2 AMIC Technology, Inc.

A29L800 Series

Pin Configurations

n SOP n TSOP (I)

A18
A17

A7
A6
A5
A4
A3
A2
A1
A0

CE

VSS

OE

I/O0

I/O1
I/O9
I/O2

I/O10

I/O3

I/O11

1
2

3
4
5
6
7
8
9
10
11
12
13
14
15
16 29
17
18
19
20
21
22

RY/BY

44
43
42
41
40
39
38
37
36
35
34
33

A29L800

32
31
30

28
27
26
25
24
23

RESET
WE

A8
A9

A10
A11
A12
A13
A14

A15
A16

BYTE
VSS

I/O15 (A-1)
I/O7
I/O14I/O8
I/O6
I/O13
I/O5
I/O12
I/O4
VCC

1
2

A14

3

A13

4

A12

5

A11

6

A10

7

A9

8

A8

9

NC

10

NC

11

WE

RESET

12
13

NC

14

NC

15

RY/BY

16

A18

17

A17

18

A7

19

A6

20

A5

21

A4

22

A3

23

A2

24 25

A1

n TFBGA

TFBGA

Top View, Balls Facing Down

A29L800V

48

A16A15

47

BYTE

46

VSS

45

I/O15 (A-1)

44

I/O7

43

I/O14

42

I/O6

41

I/O13

40

I/O5

39

I/O12

38

I/O4

37

VCC

36

I/O11

35

I/O3

34

I/O10

33 I/O2

32 I/O9
31

I/O1

30

I/O8

29

I/O0

28

OE

27

VSS

26

CE
A0

A6 B6 C6 D6 E6 F6

G6

H6

A13 A12 A14 A15 A16 BYTE I/O15(A-1) VSS

A5 B5 C5 D5 E5 F5

G5

H5

A9 A8 A10 A11 I/O7 I/O14 I/O13 I/O6

A4 B4 C4 D4 E4 F4

G4

H4

WE RESET NC NC I/O5 I/O12 VCC I/O4

A3 B3 C3 D3 E3 F3

G3

H3

RY/BY NC A18 NC I/O2 I/O10 I/O11 I/O3

A2 B2 C2 D2 E2 F2

G2

H2

A7 A17 A6 A5 I/O0 I/O8 I/O9 I/O1

A1 B1 C1 D1 E1 F1

G1

H1

A3 A4 A2 A1 A0 CE OE VSS

PRELIMINARY (September, 2002, Version 0.2) 3 AMIC Technology, Inc.

A29L800 Series

WE

BYTE

Block Diagram

VCC

VSS

RESET

BYTE

A0-A18

WE

CE
OE

RY/BY

State

Control

Command

Register

VCC Detector

PGM Voltage

Generator

Timer

Sector Switches

Erase Voltage

Generator

STB

Chip Enable

Output Enable

Logic

Y-Decoder

X-decoder

Address Latch

STB

I/O0 - I/O

15

Input/Output

Buffers

Data Latch

Y-Gating

Cell Matrix

(A-1)

Pin Descriptions

A0 - A18 Address Inputs

I/O0 - I/O14 Data Inputs/Outputs

I/O15 (A-1)

RESET

Pin No. Description

I/O15

Data Input/Output, Word Mode

A-1 LSB Address Input, Byte Mode

CE

OE

RY/BY

Chip Enable
Write Enable
Output Enable
Hardware Reset
Selects Byte Mode or Word Mode

Ready/

BUSY

- Output

VSS Ground

VCC Power Supply

NC Pin not connected internally

PRELIMINARY (September, 2002, Version 0.2) 4 AMIC Technology, Inc.

A29L800 Series

CE

WE

BYTE

BYTE

BYTE

BYTE

Absolute Maximum Ratings*

Storage Temperature Plastic Packages . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0°C to + 70°C

. . . . . . . . . . . . . . . . . . . . . . for -U series: -45°C to +85°C

Ambient Temperature with Power Applied . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to + 70°C

. . . . . . . . . . . . . . . . . . . . . . for -U series: -45°C to +85°C

Voltage with Respect to Ground

VCC (Note 1) . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.0V

A9, OE &

All other pins (Note 1) . . . . . . . . . . . . -0.5V to VCC + 0.5V

Output Short Circuit Current (Note 3) . . . . . . . . . 200mA

RESET

(Note 2) . . . . . . . . . . . . -0.5 to +12.5V

Notes:

1. Minimum DC voltage on input or I/O pins is -0.5V. During
voltage transitions, input or I/O pins may undershoot
VSS to -2.0V for periods of up to 20ns. Maximum DC
voltage on input and I/O pins is VCC +0.5V. During
voltage transitions, input or I/O pins may overshoot to
VCC +2.0V for periods up to 20ns.

2. Minimum DC input voltage on A9,OEand

-0.5V. During voltage transitions, A9,OEand
may overshoot VSS to -2.0V for periods of up to 20ns.

Maximum DC input voltage on A9 is +12.5V which may
overshoot to 14.0V for periods up to 20ns.

3. No more than one output is shorted at a time. Duration
of the short circuit should not be greater than one
second.

RESET

is

RESET

*Comments

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended
periods may affect device reliability.

Operating Ranges

Commercial (C) Devices

Ambient Temperature (TA) . . . . . . . . . . . . . . 0°C to +70°C

Extended Range Devices

Ambient Temperature (TA) . . . . . . . . . . . . -45°C to +85°C

VCC Supply Voltages

VCC for all devices . . . . . . . . . . . . . . . . . . +2.7V to +3.6V

Operating ranges define those limits between which the
functionally of the device is guaranteed.

Device Bus Operations

This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location. The
register is composed of latches that store the commands,
along with the address and data information needed to

Table 1. A29L800 Device Bus Operations

Read L L H H AIN DOUT DOUT
Write L H L H AIN DIN DIN
CMOS Standby
Output Disable L H H H X High-Z High-Z High-Z
Hardware Reset X X X L X High-Z High-Z High-Z
Sector Protect
(See Note 2)
Sector Unprotect
(See Note 2)
Temporary Sector
Unprotect
Legend:

L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5V, X = Don't Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Notes:

1. Addresses are A18:A0 in word mode (

2. See the “Sector Protection/Unprotection” section and Temporary Sector Unprotect for more information.

VCC ± 0.3 V

L H L VID
L H L VID
X X X VID AIN DIN DIN X

OE

X X

RESET

VCC ± 0.3 V

=VIH), A18: A

execute the command. The contents of the register serve
as inputs to the internal state machine. The state machine
outputs dictate the function of the device. The appropriate
device bus operations table lists the inputs and control
levels required, and the resulting output. The following
subsections describe each of these operations in further
detail.

A0 – A18

(Note 1)

X High-Z High-Z High-Z

Sector Address,

A6=L, A1=H, A0=L

Sector Address,

A6=H, A1=H, A0=L

in byte mode (

-1

I/O0 - I/O7

DIN X X
DIN X X

=VIL).

I/O8 - I/O15 Operation

=VIH

I/O8~I/O4=High-Z

I/O15=A-1

=VIL

PRELIMINARY (September, 2002, Version 0.2) 5 AMIC Technology, Inc.

A29L800 Series

BYTE

BYTE

BYTE

BYTE

WE

BYTE

Word/Byte Configuration

The
operate in the byte or word configuration. If the

is set at logic ”1”, the device is in word configuration, I/O15­I/O0 are active and controlled by CE and OE.

If the
configuration, and only I/O0-I/O7 are active and controlled

by CE and OE. I/O8-I/O14 are tri-stated, and I/O15 pin is
used as an input for the LSB(A-1) address function.

pin determines whether the I/O pins I/O15-I/O0

pin

pin is set at logic “0”, the device is in byte

Requirements for Reading Array Data

To read array data from the outputs, the system must drive
the CEand OE pins to VIL. CE is the power control and

selects the device. OE is the output control and gates
array data to the output pins. WE should remain at VIH all
the time during read operation. The

whether the device outputs array data in words and bytes.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content
occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid addresses on
the device address inputs produce valid data on the device
data outputs. The device remains enabled for read access
until the command register contents are altered.
See "Reading Array Data" for more information. Refer to the
AC Read Operations table for timing specifications and to
the Read Operations Timings diagram for the timing
waveforms, lCC1 in the DC Characteristics table represents
the active current specification for reading array data.

pin determines

Writing Commands/Command Sequences

To write a command or command sequence (which
includes programming data to the device and erasing

sectors of memory), the system must drive
VIL, and OE to VIH. For program operations, the

determines whether the device accepts program data in
bytes or words, Refer to “Word/Byte Configuration” for more
information. The device features an Unlock Bypass mode to
facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required to
program a word or byte, instead of four. The “
Word / Byte Program Command Sequence” section has
details on programming data to the device using both
standard and Unlock Bypass command sequence. An
erase operation can erase one sector, multiple sectors, or
the entire device. The Sector Address Tables indicate the
address range that each sector occupies. A "sector
address" consists of the address inputs required to uniquely

and CE to

pin

select a sector. See the "Command Definitions" section for
details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can
then read autoselect codes from the internal register (which
is separate from the memory array) on I/O7 - I/O0. Standard
read cycle timings apply in this mode. Refer to the
"Autoselect Mode" and "Autoselect Command Sequence"
sections for more information.
ICC2 in the DC Characteristics table represents the active
current specification for the write mode. The "AC
Characteristics" section contains timing specification tables
and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may
check the status of the operation by reading the status bits
on I/O7 - I/O0. Standard read cycle timings and ICC read
specifications apply. Refer to "Write Operation Status" for
more information, and to each AC Characteristics section
for timing diagrams.

Standby Mode

When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs are

placed in the high impedance state, independent of the OE
input.

The device enters the CMOS standby mode when the CE
&

RESET

is a more restricted voltage range than VIH.) If CEand

RESET

device will be in the standby mode, but the standby current
will be greater. The device requires the standard access
time (tCE) before it is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
ICC3 and ICC4 in the DC Characteristics tables represent the
standby current specification.

pins are both held at VCC ± 0.3V. (Note that this

are held at VIH, but not within VCC ± 0.3V, the

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for tACC +30ns. The

automatic sleep mode is independent of the CE,WEand

control signals. Standard address access timings

OE

provide new data when addresses are changed. While in
sleep mode, output data is latched and always available to
the system. ICC4 in the DC Characteristics table represents
the automatic sleep mode current specification.

PRELIMINARY (September, 2002, Version 0.2) 6 AMIC Technology, Inc.

A29L800 Series

BY

Output Disable Mode

When the OE input is at VIH, output from the device is
disabled. The output pins are placed in the high impedance

state.

RESET

The
the device to reading array data. When the system drives
the
immediately terminates any operation in progress, tristates

all data output pins, and ignores all read/write attempts for
the duration of the
the internal state machine to reading array data. The

operation that was interrupted should be reinitiated once
the device is ready to accept another command sequence,
to ensure data integrity.

Current is reduced for the duration of the
When
CMOS standby current (ICC4 ). If

not within VSS ± 0.3V, the standby current will be greater.

: Hardware Reset Pin

RESET

RESET

pin provides a hardware method of resetting

pin low for at least a period of tRP, the device

RESET

is held at VSS ± 0.3V, the device draws

RESET

pulse. The device also resets

pulse.

RESET

RESET

is held at VIL but

The

RESET

system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.

If

RESET

the RY/BYpin remains a “0” (busy) until the internal reset
operation is complete, which requires a time tREADY (during
Embedded Algorithms). The system can thus monitor

RY/
complete. If

operation is not executing (RY/BY pin is “1”), the reset
operation is completed within a time of tREADY (not during
Embedded Algorithms). The system can read data tRH after

the

RESET

Refer to the AC Characteristics tables for
parameters and diagram.

pin may be tied to the system reset circuitry. A

is asserted during a program or erase operation,

to determine whether the reset operation is

RESET

pin return to VIH.

is asserted when a program or erase

RESET

PRELIMINARY (September, 2002, Version 0.2) 7 AMIC Technology, Inc.

A29L800 Series

Table 2. A29L800 Top Boot Block Sector Address Table

Sector Size

Sector A18 A17 A16 A15 A14 A13 A12

SA0 0 0 0 0 X X X 64/32 00000h - 0FFFFh 00000h - 07FFFh
SA1 0 0 0 1 X X X 64/32 10000h - 1FFFFh 08000h - 0FFFFh
SA2 0 0 1 0 X X X 64/32 20000h - 2FFFFh 10000h - 17FFFh
SA3 0 0 1 1 X X X 64/32 30000h - 3FFFFh 18000h - 1FFFFh
SA4 0 1 0 0 X X X 64/32 40000h - 4FFFFh 20000h - 27FFFh
SA5 0 1 0 1 X X X 64/32 50000h - 5FFFFh 28000h - 2FFFFh
SA6 0 1 1 0 X X X 64/32 60000h - 6FFFFh 30000h - 37FFFh
SA7 0 1 1 1 X X X 64/32 70000h - 7FFFFh 38000h - 3FFFFh
SA8 1 0 0 0 X X X 64/32 80000h - 8FFFFh 40000h - 47FFFh
SA9 1 0 0 1 X X X 64/32 90000h - 9FFFFh 48000h - 4FFFFh

SA10 1 0 1 0 X X X 64/32 A0000h - AFFFFh 50000h - 57FFFh
SA11 1 0 1 1 X X X 64/32 B0000h - BFFFFh 58000h - 5FFFFh
SA12 1 1 0 0 X X X 64/32 C0000h - CFFFFh 60000h - 67FFFh
SA13 1 1 0 1 X X X 64/32 D0000h - DFFFFh 68000h - 6FFFFh
SA14 1 1 1 0 X X X 64/32 E0000h - EFFFFh 70000h - 77FFFh
SA15 1 1 1 1 0 X X 32/16 F0000h - F7FFFh 78000h - 7BFFFh
SA16 1 1 1 1 1 0 0 8/4 F8000h - F9FFFh 7C000h - 7CFFFh
SA17 1 1 1 1 1 0 1 8/4 FA000h - FBFFFh 7D000h - 7DFFFh
SA18 1 1 1 1 1 1 X 16/8 FC000h - FFFFFh 7E000h - 7FFFFh

Note:
Address range is A18 : A-1 in byte mode and A18 : A0 in word mode. See “Word/Byte Configuration” section.

(Kbytes/
Kwords)

Address Range (in hexadecimal)

Byte Mode

(x 8)

Word Mode

(x16)

PRELIMINARY (September, 2002, Version 0.2) 8 AMIC Technology, Inc.

A29L800 Series

Table 3. A29L800 Bottom Boot Block Sector Address Table

Sector Size

Sector A18 A17 A16 A15 A14 A13 A12

SA0 0 0 0 0 0 0 X 16/8 00000h - 03FFFh 00000 - 01FFF
SA1 0 0 0 0 0 1 0 8/4 04000h - 05FFFh 02000 - 02FFF
SA2 0 0 0 0 0 1 1 8/4 06000h - 07FFFh 03000 - 03FFF
SA3 0 0 0 0 1 X X 32/16 08000h - 0FFFFh 04000 - 07FFF
SA4 0 0 0 1 X X X 64/32 10000h - 1FFFFh 08000 - 0FFFF
SA5 0 0 1 0 X X X 64/32 20000h – 2FFFFh 10000 - 17FFF
SA6 0 0 1 1 X X X 64/32 30000h - 3FFFFh 18000 - 1FFFF
SA7 0 1 0 0 X X X 64/32 40000h - 4FFFFh 20000 - 27FFF
SA8 0 1 0 1 X X X 64/32 50000h - 5FFFFh 28000 - 2FFFF

SA9 0 1 1 0 X X X 64/32 60000h - 6FFFFh 30000 - 37FFF
SA10 0 1 1 1 X X X 64/32 70000h - 7FFFFh 38000 - 3FFFF
SA11 1 0 0 0 X X X 64/32 80000h - 8FFFFh 40000 - 47FFF
SA12 1 0 0 1 X X X 64/32 90000h - 9FFFFh 48000 - 4FFFF
SA13 1 0 1 0 X X X 64/32 A0000h - AFFFFh 50000 - 57FFF
SA14 1 0 1 1 X X X 64/32 B0000h - BFFFFh 58000 - 5FFFF
SA15 1 1 0 0 X X X 64/32 C0000h - CFFFFh 60000 - 67FFF
SA16 1 1 0 1 X X X 64/32 D0000h - DFFFFh 68000 - 6FFFF
SA17 1 1 1 0 X X X 64/32 E0000h - EFFFFh 70000 - 77FFF
SA18 1 1 1 1 X X X 64/32 F0000h - FFFFFh 78000 - 7FFFF

(Kbytes/
Kwords)

Address Range (in hexadecimal)

Byte Mode

(x 8)

Word Mode

(x16)

Note:
Address range is A18 : A-1 in byte mode and A18 : A0 in word mode. See “Word/Byte Configuration” section.

PRELIMINARY (September, 2002, Version 0.2) 9 AMIC Technology, Inc.

A29L800 Series

CE

WE

Autoselect Mode

The autoselect mode provides manufacturer and device
identification, and sector protection verification, through
identifier codes output on I/O7 - I/O0. This mode is primarily
intended for programming equipment to automatically
match a device to be programmed with its corresponding
programming algorithm. However, the autoselect codes
can also be accessed in-system through the command
register.
When using programming equipment, the autoselect mode
requires VID (11.5V to 12.5 V) on address pin A9. Address
pins A6, A1, and A0 must be as shown in Autoselect
Codes (High Voltage Method) table. In addition, when

verifying sector protection, the sector address must appear
on the appropriate highest order address bits. Refer to the
corresponding Sector Address Tables. The Command
Definitions table shows the remaining address bits that are
don't care. When all necessary bits have been set as
required, the programming equipment may then read the
corresponding identifier code on I/O7 - I/O0.To access the
autoselect codes in-system, the host system can issue the
autoselect command via the command register, as shown
in the Command Definitions table. This method does not
require VID. See "Command Definitions" for details on
using the autoselect mode.

Table 4. A29L800 Autoselect Codes (High Voltage Method)

Description Mode

Manufacturer ID: AMIC L L H X X VID X L X L L X 37h

Word B3h 1Ah Device ID:
A29L800
(Top Boot Block)

A29L800
(Bottom Boot Block)

Continuation ID L L H X X VID X L X H H X 7Fh

Byte

Word B3h 9Bh Device ID:

Byte

L L H X X VID X L X L H

L L H X X VID X L X L H

OE

A18

A11

to

A12

A9 A8

to

A10

to

A7

A6 A5

to

A2

A1 A0 I/O8

to

I/O15

X 1Ah

X 9Bh

I/O7

to

I/O0

Sector Protection Verification L L H SA X VID X L X H L

L=Logic Low= VIL, H=Logic High=VIH, SA=Sector Address, X=Don’t Care.
Note: The autoselect codes may also be accessed in-system via command sequences.

X

X

01h

(protected)

00h

(unprotected)

PRELIMINARY (September, 2002, Version 0.2) 10 AMIC Technology, Inc.

A29L800 Series

WE

WE

WE

WE

Sector Protection/Unprotection

The hardware sector protection feature disables both
program and erase operations in any sector. The hardware
sector unprotection feature re-enables both program and
erase operations in previously protected sectors.
It is possible to determine whether a sector is protected or
unprotected. See “Autoselect Mode” for details.
Sector protection / unprotection can be implemented via two
methods. The primary method requires VID on the

RESET

pin only, and can be implemented either in-system or

via programming equipment. Figure 2 shows the algorithm
and the Sector Protect / Unprotect Timing Diagram illustrates
the timing waveforms for this feature. This method uses
standard microprocessor bus cycle timing. For sector
unprotect, all unprotected sectors must first be protected
prior to the first sector unprotect write cycle. The alternate
method must be implemented using programming
equipment. The procedure requires a high voltage (VID) on
address pin A9 and the control pins.
The device is shipped with all sectors unprotected.
It is possible to determine whether a sector is protected or
unprotected. See "Autoselect Mode" for details.

Hardware Data Protection

The requirement of command unlocking sequence for
programming or erasing provides data protection against
inadvertent writes (refer to the Command Definitions table).
In addition, the following hardware data protection measures
prevent accidental erasure or programming, which might
otherwise be caused by spurious system level signals during
VCC power-up transitions, or from system noise. The device is
powered up to read array data to avoid accidentally writing
data to the array.

Write Pulse "Glitch" Protection

Noise pulses of less than 5ns (typical) on OE, CE or WE
do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE=VIL,

= VIH or

CE

must be a logical zero while OE is a logical one.

= VIH. To initiate a write cycle, CE and

Temporary Sector Unprotect

This feature allows temporary unprotection of previous
protected sectors to change data in-system. The Sector

Unprotect mode is activated by setting the

RESET

During this mode, formerly protected sectors can be
programmed or erased by selecting the sector addresses.

Once VID is removed from the

RESET

pin, all the previously

protected sectors are protected again. Figure 1 shows the
algorithm, and the Temporary Sector Unprotect diagram
shows the timing waveforms, for this feature.

START

RESET = VID

(Note 1)

Perform Erase or

Program Operations

RESET = VIH

Temporary Sector

Unprotect

Completed (Note 2)

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once again.

Figure 1. Temporary Sector Unprotect Operation

pin to VID.

Power-Up Write Inhibit

If

= CE = VIL and OE = VIH during power up, the

device does not accept commands on the rising edge of

. The internal state machine is automatically reset to

reading array data on the initial power-up.

PRELIMINARY (September, 2002, Version 0.2) 11 AMIC Technology, Inc.

A29L800 Series

Temporary Sector

Unprotect Mode

Increment

PLSCNT

No

PLSCNT

=25?

Yes

Device failed

START

PLSCNT=1

RESET=V

Wait 1 us

No

First Write

Cycle=60h?

Set up sector

address

Sector Protect
Write 60h to sector
address with A6=0,

A1=1, A0=0

Wait 150 us

Verify Sector

Protect: Write 40h

to sector address
with A6=0, A1=1,

Read from

sector address

with A6=0,

A1=1, A0=0

No

Data=01h?

Protect another

sector?

Remove V

from RESET

A0=0

Yes

No

Yes

START

Protect all sectors:

The indicated portion of

the sector protect

algorithm must be

ID

Reset

PLSCNT=1

Yes

ID

performed for all

unprotected sectors prior

to issuing the first sector

unprotect address

Increment

PLSCNT

No

PLSCNT=

1000?

Yes

Device failed

PLSCNT=1

RESET=V

Wait 1 us

No

First Write

Cycle=60h?

All sectors
protected?

Set up first sector

address

Sector Unprotect:
Write 60h to sector
address with A6=1,

A1=1, A0=0

Wait 15 ms

Verify Sector

Unprotect : Write

40h to sector

address with A6=1,

A1=1, A0=0

Read from sector
address with A6=1,

A1=1, A0=0

No

Data=00h?

Last sector

verified?

Yes

Yes

Yes

ID

No

Temporary Sector

Unprotect Mode

Set up

next sector

address

No

Sector Protect

Algorithm

Write reset

command

Sector Protect

complete

Sector Unprotect

Algorithm

Sector Unprotect

Yes

Remove V
from RESET

Write reset

Command

complete

ID

Figure 2. In-System Sector Protect/Unprotect Algorithms

PRELIMINARY (September, 2002, Version 0.2) 12 AMIC Technology, Inc.

A29L800 Series

WE

BYTE

Command Definitions

Writing specific address and data commands or sequences
into the command register initiates device operations. The
Command Definitions table defines the valid register
command sequences. Writing incorrect address and data
values or writing them in the improper sequence resets the
device to reading array data.

All addresses are latched on the falling edge of WE or CE,
whichever happens later. All data is latched on the rising edge

of
appropriate timing diagrams in the "AC Characteristics"

section.

or

, whichever happens first. Refer to the

CE

Reading Array Data

The device is automatically set to reading array data after
device power-up. No commands are required to retrieve data.
The device is also ready to read array data after completing
an Embedded Program or Embedded Erase algorithm. After
the device accepts an Erase Suspend command, the device
enters the Erase Suspend mode. The system can read array
data using the standard read timings, except that if it reads at
an address within erase-suspended sectors, the device
outputs status data. After completing a programming
operation in the Erase Suspend mode, the system may once
again read array data with the same exception. See "Erase
Suspend/Erase Resume Commands" for more information on
this mode.
The system must issue the reset command to re-enable the
device for reading array data if I/O5 goes high, or while in the
autoselect mode. See the "Reset Command" section, next.
See also "Requirements for Reading Array Data" in the
"Device Bus Operations" section for more information. The
Read Operations table provides the read parameters, and
Read Operation Timings diagram shows the timing diagram.

Reset Command

Writing the reset command to the device resets the device to
reading array data. Address bits are don't care for this
command. The reset command may be written between the
sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array data.
Once erasure begins, however, the device ignores reset
commands until the operation is complete.
The reset command may be written between the sequence
cycles in a program command sequence before programming
begins. This resets the device to reading array data (also
applies to programming in Erase Suspend mode). Once
programming begins, however, the device ignores reset
commands until the operation is complete.
The reset command may be written between the sequence
cycles in an autoselect command sequence. Once in the
autoselect mode, the reset command must be written to
return to reading array data (also applies to autoselect during
Erase Suspend).
If I/O5 goes high during a program or erase operation, writing
the reset command returns the device to reading array data
(also applies during Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host system to
access the manufacturer and devices codes, and determine
whether or not a sector is protected. The Command Definitions
table shows the address and data requirements. This method
is an alternative to that shown in the Autoselect Codes (High
Voltage Method) table, which is intended for PROM
programmers and requires VID on address bit A9.
The autoselect command sequence is initiated by writing two
unlock cycles, followed by the autoselect command. The
device then enters the autoselect mode, and the system may
read at any address any number of times, without initiating
another command sequence.
A read cycle at address XX00h retrieves the manufacturer
code and another read cycle at XX03h retrieves the
continuation code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address (SA)
and the address 02h in returns 01h if that sector is protected,
or 00h if it is unprotected. Refer to the Sector Address tables
for valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.

Word/Byte Program Command Sequence

The system may program the device by word or byte,
depending on the state of the

four-bus-cycle operation. The program command sequence is
initiated by writing two unlock write cycles, followed by the
program set-up command. The program address and data are
written next, which in turn initiate the Embedded Program
algorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verify the
programmed cell margin. Table 5 shows the address and data
requirements for the byte program command sequence.
When the Embedded Program algorithm is complete, the
device then returns to reading array data and addresses are
longer latched. The system can determine the status of the

program operation by using I/O7, I/O6, or RY/BY. See “White
Operation Status” for information on these status bits.
Any commands written to the device during the Embedded
Program Algorithm are ignored. Note that a hardware reset
immediately terminates the programming operation. The Byte
Program command sequence should be reinitiated once the
device has reset to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across sector
boundaries. A bit cannot be programmed from a “0” back to a
“1”. Attempting to do so may halt the operation and set I/O5 to

“1”, or cause the
operation was successful. However, a succeeding read will

show that the data is still “0”. Only erase operations can
convert a “0” to a “1”.

Polling algorithm to indicate the

Data

pin. Programming is a

PRELIMINARY (September, 2002, Version 0.2) 13 AMIC Technology, Inc.

A29L800 Series

START

Write Program

Command
Sequence

Embedded

Program

algorithm in

progress

Data Poll

from System

Verify Data ?

No

Yes

Increment Address

Last Address ?

Programming

Yes

Completed

Note : See the appropriate Command Definitions table for
program command sequence.

Figure 3. Program Operation

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to program
bytes or words to the device faster than using the standard
program command sequence. The unlock bypass command
sequence is initiated by first writing two unlock cycles. This is
followed by a third write cycle containing the unlock bypass
command, 20h. The device then enters the unlock bypass
mode. A two-cycle unlock bypass program command
sequence is all that is required to program in this mode. The
first cycle in this sequence contains the unlock bypass
program command, A0h; the second cycle contains the
program address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial two
unlock cycles required in the standard program command
sequence, resulting in faster total programming time. Table 5
shows the requirements for the command sequence.

During the unlock bypass mode, only the Unlock Bypass
Program and Unlock Bypass Reset commands are valid. To
exit the unlock bypass mode, the system must issue the two­cycle unlock bypass reset command sequence. The first cycle
must contain the data 90h; the second cycle the data 00h.
Addresses are don’t care for both cycle. The device returns to
reading array data.
Figure 3 illustrates the algorithm for the program operation.
See the Erase/Program Operations in “AC Characteristics” for
parameters, and to Program Operation Timings for timing
diagrams.

Chip Erase Command Sequence

Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which in
turn invokes the Embedded Erase algorithm. The device does
not require the system to preprogram prior to erase. The
Embedded Erase algorithm automatically preprograms and
verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any
controls or timings during these operations. The Command
Definitions table shows the address and data requirements for
the chip erase command sequence.
Any commands written to the chip during the Embedded
Erase algorithm are ignored. The system can determine the
status of the erase operation by using I/O7, I/O6, or I/O2. See
"Write Operation Status" for information on these status bits.
When the Embedded Erase algorithm is complete, the device
returns to reading array data and addresses are no longer
latched.
Figure 4 illustrates the algorithm for the erase operation. See
the Erase/Program Operations tables in "AC Characteristics"
for parameters, and to the Chip/Sector Erase Operation
Timings for timing waveforms.

Sector Erase Command Sequence

Sector erase is a six-bus-cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the address of the sector to be
erased, and the sector erase command. The Command
Definitions table shows the address and data requirements for
the sector erase command sequence.
The device does not require the system to preprogram the
memory prior to erase. The Embedded Erase algorithm
automatically programs and verifies the sector for an all zero
data pattern prior to electrical erase. The system is not
required to provide any controls or timings during these
operations.
After the command sequence is written, a sector erase time­out of 50µs begins. During the time-out period, additional
sector addresses and sector erase commands may be written.
Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector
to all sectors. The time between these additional cycles must
be less than 50µs, otherwise the last address and command
might not be accepted, and erasure may begin. It is
recommended that processor interrupts be disabled during
this time to ensure all commands are accepted. The interrupts

PRELIMINARY (September, 2002, Version 0.2) 14 AMIC Technology, Inc.

A29L800 Series

WE

can be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase commands
can be assumed to be less than 50µs, the system need not
monitor I/O3. Any command other than Sector Erase or Erase
Suspend during the time-out period resets the device to
reading array data. The system must rewrite the command
sequence and any additional sector addresses and
commands.
The system can monitor I/O3 to determine if the sector erase
timer has timed out. (See the " I/O3: Sector Erase Timer"
section.) The time-out begins from the rising edge of the final

pulse in the command sequence.
Once the sector erase operation has begun, only the Erase
Suspend command is valid. All other commands are ignored.
When the Embedded Erase algorithm is complete, the device
returns to reading array data and addresses are no longer
latched. The system can determine the status of the erase
operation by using I/O7, I/O6, or I/O2. Refer to "Write
Operation Status" for information on these status bits.
4 illustrates the algorithm for the erase operation. Refer to the
Erase/Program Operations tables in the "AC Characteristics"
section for parameters, and to the Sector Erase Operations
Timing diagram for timing waveforms.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to interrupt
a sector erase operation and then read data from, or program
data to, any sector not selected for erasure. This command is
valid only during the sector erase operation, including the
50µs time-out period during the sector erase command
sequence. The Erase Suspend command is ignored if written
during the chip erase operation or Embedded Program
algorithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the time-out
period and suspends the erase operation. Addresses are
"don't cares" when writing the Erase Suspend command.
When the Erase Suspend command is written during a sector
erase operation, the device requires a maximum of 20µs to
suspend the erase operation. However, when the Erase
Suspend command is written during the sector erase time­out, the device immediately terminates the time-out period
and suspends the erase operation.
After the erase operation has been suspended, the system
can read array data from or program data to any sector not
selected for erasure. (The device "erase suspends" all sectors
selected for erasure.) Normal read and write timings and
command definitions apply. Reading at any address within
erase-suspended sectors produces status data on I/O7 - I/O0.
The system can use I/O7, or I/O6 and I/O2 together, to
determine if a sector is actively erasing or is erase­suspended. See "Write Operation Status" for information on
these status bits.
After an erase-suspended program operation is complete, the
system can once again read array data within non-suspended
sectors. The system can determine the status of the program
operation using the I/O7 or I/O6 status bits, just as in the
standard program operation. See "Write Operation Status" for
more information.

The system may also write the autoselect command
sequence when the device is in the Erase Suspend mode.
The device allows reading autoselect codes even at
addresses within erasing sectors, since the codes are not
stored in the memory array. When the device exits the
autoselect mode, the device reverts to the Erase Suspend
mode, and is ready for another valid operation. See
"Autoselect Command Sequence" for more information.
The system must write the Erase Resume command (address
bits are "don't care") to exit the erase suspend mode and
continue the sector erase operation. Further writes of the
Resume command are ignored. Another Erase Suspend
command can be written after the device has resumed
erasing.

START

Write Erase

Command

Sequence

No

Data Poll

from System

Data = FFh ?

Embedded
Erase
algorithm in
progress

Yes

Erasure Completed

Note :

1. See the appropriate Command Definitions table for erase
command sequences.

2. See "I/O3 : Sector Erase Timer" for more information.

Figure 4. Erase Operation

PRELIMINARY (September, 2002, Version 0.2) 15 AMIC Technology, Inc.

A29L800 Series

WE

Table 5. A29L800 Command Definitions

Command

Sequence

(Note 1)

Read (Note 6) 1 RA RD
Reset (Note 7) 1 XXX F0

Manufacturer ID

Device ID,
Top Boot Block

Device ID,
Bottom Boot Block

Continuation ID

Autoselect (Note 8)

Sector Protect Verify

(Note 9)

Program

Unlock Bypass
Unlock Bypass Program (Note 10) 2 XXX A0 PA PD

Unlock Bypass Reset (Note 11) 2 XXX 90 XXX 00

Chip Erase

Sector Erase
Erase Suspend (Note 12) 1 XXX B0

Erase Resume (Note 13) 1 XXX 30

Word

Byte

Word

Byte

Word

Byte

Word
Byte

Word

Byte
Word

Byte

Word

Byte

Word

Byte

Word

Byte

First Second Third Fourth Fifth Sixth

Cycles

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

555 2AA

4

4

4

4

4

4

3

6

6

AA

AAA
555

AA

AAA
555 2AA 555 X01

AA

AAA
555

AA

AAA
555

AA

AAA

555 2AA

AA

AAA
555 2AA 555

AA

AAA

555 2AA

AA

AAA
555
AAA

AA

555
2AA

555

555
2AA
555
2AA

555

555

555

555
2AA
555

55

55

55

55

55

55

55

Bus Cycles (Notes 2 - 5)

555

90 X00 37

555 X01

90

90

555

90

555

90

555

A0 PA PD

20

555

80

555

80

55

55

AAA

AAA

AAA

AAA

AAA

AAA

AAA

AAA

AAA

B31A

1A

X02

B39B

9B

X02

X03
X06

(SA)

X02

(SA)

X04

555 2AA

AAA
555 2AA
AAA

7F

XX00
XX01

00
01

AA

555

AA

555

555

55

AAA

55 SA 30

10

Legend:
X = Don't care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the

whichever happens later.

PD = Data to be programmed at location PA. Data latches on the rising edge of WE or CE pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A18 - A12 select a unique sector.

PRELIMINARY (September, 2002, Version 0.2) 16 AMIC Technology, Inc.

or CE pulse,

A29L800 Series

Note:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all bus cycles are write operation.

4. Data bits I/O15~I/O8 are don’t care for unlock and command cycles.

5. Address bits A18 - A11 are don't cares for unlock and command cycles, unless SA or PA required.

6. No unlock or command cycles required when reading array data.

7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if I/O5 goes high
(while the device is providing status data).

8. The fourth cycle of the autoselect command sequence is a read cycle.

9. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more
information.

10. The Unlock Bypass command is required prior to the Unlock Bypass Program command.

11. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass
mode.

12. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.

13. The Erase Resume command is valid only during the Erase Suspend mode.

PRELIMINARY (September, 2002, Version 0.2) 17 AMIC Technology, Inc.

A29L800 Series

BY

BY

WE

Write Operation Status

Several bits, I/O2, I/O3, I/O5, I/O6, I/O7, RY/

are provided

in the A29L800 to determine the status of a write operation.
Table 6 and the following subsections describe the

functions of these status bits. I/O7, I/O6 and RY/

each

offer a method for determining whether a program or erase
operation is complete or in progress. These three bits are
discussed first.

I/O7:

The

Polling

Data

Polling bit, I/O7, indicates to the host system

Data

whether an Embedded Algorithm is in progress or
completed, or whether the device is in Erase Suspend.

Polling is valid after the rising edge of the final

Data

pulse in the program or erase command sequence.
During the Embedded Program algorithm, the device
outputs on I/O7 the complement of the datum programmed
to I/O7. This I/O7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to
I/O7. The system must provide the program address to read
valid status information on I/O7. If a program address falls

within a protected sector,

Polling on I/O7 is active for

Data

approximately 2µs, then the device returns to reading array
data.

During the Embedded Erase algorithm,

Data

Polling

produces a "0" on I/O7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase

Suspend mode,

Polling produces a "1" on I/O7.This is

Data

analogous to the complement/true datum output described
for the Embedded Program algorithm: the erase function
changes all the bits in a sector to "1"; prior to this, the
device outputs the "complement," or "0." The system must
provide an address within any of the sectors selected for
erasure to read valid status information on I/O7.
After an erase command sequence is written, if all sectors

selected for erasing are protected,

Polling on I/O7 is

Data

active for approximately 100µs, then the device returns to
reading array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
protected.
When the system detects I/O7 has changed from the
complement to true data, it can read valid data at I/O7 - I/O0
on the following read cycles. This is because I/O7 may
change asynchronously with I/O0 - I/O6 while Output Enable

(OE) is asserted low. The

Polling Timings (During

Data

Embedded Algorithms) in the "AC Characteristics" section
illustrates this. Table 6 shows the outputs for

on I/O7. Figure 5 shows the

Polling algorithm.

Data

Data

Polling

START

Read I/O7-I/O0

Address = VA

Yes

I/O7 = Data ?

No

No

Note :

1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.

2. I/O7 should be rechecked even if I/O5 = "1" because
I/O7 may change simultaneously with I/O5.

I/O5 = 1?

Yes

Read I/O7 - I/O0

Address = VA

I/O7 = Data ?

No

FAIL

Yes

PASS

Figure 5. Data Polling Algorithm

PRELIMINARY (September, 2002, Version 0.2) 18 AMIC Technology, Inc.

A29L800 Series

BY

WE

WE

WE

RY/

The RY/BY is a dedicated, open-drain output pin that
indicates whether an Embedded algorithm is in progress or

complete. The RY/BY status is valid after the rising edge of
the final
RY/BY is an open-drain output, several RY/BY pins can be

tied together in parallel with a pull-up resistor to VCC. (The
RY/BY pin is not available on the 44-pin SOP package)

If the output is low (Busy), the device is actively erasing or
programming. (This includes programming in the Erase
Suspend mode.) If the output is high (Ready), the device is
ready to read array data (including during the Erase
Suspend mode), or is in the standby mode.

Table 6 shows the outputs for RY/BY. Refer to “
Timings”, “Timing Waveforms for Program Operation” and

“Timing Waveforms for Chip/Sector Erase Operation” for
more information.

: Read/

Busy

pulse in the command sequence. Since

RESET

I/O6: Toggle Bit I

Toggle Bit I on I/O6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address, and is valid after

the rising edge of the final
sequence (prior to the program or erase operation), and
during the sector erase time-out.
During an Embedded Program or Erase algorithm operation,
successive read cycles to any address cause I/O6 to toggle.

(The system may use either OE or CE to control the read
cycles.) When the operation is complete, I/O6 stops toggling.

After an erase command sequence is written, if all sectors
selected for erasing are protected, I/O6 toggles for
approximately 100µs, then returns to reading array data. If
not all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use I/O6 and I/O2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), I/O6 toggles. When the
device enters the Erase Suspend mode, I/O6 stops toggling.
However, the system must also use I/O2 to determine which
sectors are erasing or erase-suspended. Alternatively, the

system can use I/O7 (see the subsection on " I/O7 :
Polling").

If a program address falls within a protected sector, I/O6
toggles for approximately 2µs after the program command
sequence is written, then returns to reading array data.
I/O6 also toggles during the erase-suspend-program mode,
and stops toggling once the Embedded Program algorithm
is complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on I/O6. Refer to Figure 6 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the "AC
Characteristics" section for the timing diagram. The I/O2 vs.
I/O6 figure shows the differences between I/O2 and I/O6 in
graphical form. See also the subsection on " I/O2: Toggle Bit
II".

pulse in the command

Data

I/O2: Toggle Bit II

The "Toggle Bit II" on I/O2, when used with I/O6, indicates
whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that
sector is erase-suspended. Toggle Bit II is valid after the

rising edge of the final
sequence.
I/O2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The

system may use either
cycles.) But I/O2 cannot distinguish whether the sector is

actively erasing or is erase-suspended. I/O6, by comparison,
indicates whether the device is actively erasing, or is in
Erase Suspend, but cannot distinguish which sectors are
selected for erasure. Thus, both status bits are required for
sector and mode information. Refer to Table 6 to compare
outputs for I/O2 and I/O6.
Figure 6 shows the toggle bit algorithm in flowchart form,
and the section " I/O2: Toggle Bit II" explains the algorithm.
See also the " I/O6: Toggle Bit I" subsection. Refer to the
Toggle Bit Timings figure for the toggle bit timing diagram.
The I/O2 vs. I/O6 figure shows the differences between I/O2
and I/O6 in graphical form.

OE

pulse in the command

or CE to control the read

Reading Toggle Bits I/O6, I/O2

Refer to Figure 6 for the following discussion. Whenever the
system initially begins reading toggle bit status, it must read
I/O7 - I/O0 at least twice in a row to determine whether a
toggle bit is toggling. Typically, a system would note and
store the value of the toggle bit after the first read. After the
second read, the system would compare the new value of
the toggle bit with the first. If the toggle bit is not toggling,
the device has completed the program or erase operation.
The system can read array data on I/O7 - I/O0 on the
following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system
also should note whether the value of I/O5 is high (see the
section on I/O5). If it is, the system should then determine
again whether the toggle bit is toggling, since the toggle bit
may have stopped toggling just as I/O5 went high. If the
toggle bit is no longer toggling, the device has successfully
completed the program or erase operation. If it is still
toggling, the device did not complete the operation
successfully, and the system must write the reset command
to return to reading array data.
The remaining scenario is that the system initially
determines that the toggle bit is toggling and I/O5 has not
gone high. The system may continue to monitor the toggle
bit and I/O5 through successive read cycles, determining the
status as described in the previous paragraph. Alternatively,
it may choose to perform other system tasks. In this case,
the system must start at the beginning of the algorithm when
it returns to determine the status of the operation (top of
Figure 6).

PRELIMINARY (September, 2002, Version 0.2) 19 AMIC Technology, Inc.

A29L800 Series

I/O5: Exceeded Timing Limits

I/O5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under these
conditions I/O5 produces a "1." This is a failure condition
that indicates the program or erase cycle was not
successfully completed.
The I/O5 failure condition may appear if the system tries to
program a "1 "to a location that is previously programmed to
"0." Only an erase operation can change a "0" back to a "1."
Under this condition, the device halts the operation, and
when the operation has exceeded the timing limits, I/O5
produces a "1."
Under both these conditions, the system must issue the
reset command to return the device to reading array data.

START

Read I/O7-I/O0

Read I/O7-I/O0

(Note 1)

I/O3: Sector Erase Timer

After writing a sector erase command sequence, the
system may read I/O3 to determine whether or not an erase
operation has begun. (The sector erase timer does not
apply to the chip erase command.) If additional sectors are
selected for erasure, the entire time-out also applies after
each additional sector erase command. When the time-out
is complete, I/O3 switches from "0" to "1." The system may
ignore I/O3 if the system can guarantee that the time
between additional sector erase commands will always be
less than 50µs. See also the "Sector Erase Command
Sequence" section.
After the sector erase command sequence is written, the

system should read the status on I/O7 (

Data

Polling) or

I/O6 (Toggle Bit I) to ensure the device has accepted the
command sequence, and then read I/O3. If I/O3 is "1", the
internally controlled erase cycle has begun; all further
commands (other than Erase Suspend) are ignored until
the erase operation is complete. If I/O3 is "0", the device will
accept additional sector erase commands. To ensure the
command has been accepted, the system software should
check the status of I/O3 prior to and following each
subsequent sector erase command. If I/O3 is high on the
second status check, the last command might not have
been accepted. Table 6 shows the outputs for I/O3.

No

Toggle Bit

= Toggle ?

Yes

I/O5 = 1?

Yes

Read I/O7 - I/O0

Twice

Toggle Bit

= Toggle ?

Yes

Program/Erase

Operation Not

Commplete, Write

Reset Command

No

(Notes 1,2)

No

Program/Erase

Operation Complete

Notes :

1. Read toggle bit twice to determine whether or not it is
toggling. See text.

2. Recheck toggle bit because it may stop toggling as I/O5
changes to "1". See text.

Figure 6. Toggle Bit Algorithm

PRELIMINARY (September, 2002, Version 0.2) 20 AMIC Technology, Inc.

A29L800 Series

Table 6. Write Operation Status

Operation

I/O7 I/O6 I/O5 I/O3 I/O2

RY/BY

(Note 1) (Note 2) (Note 1)

Standard
Mode

Erase
Suspend
Mode

Embedded Program Algorithm

7I/O

Toggle 0 N/A No toggle 0

Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0
Reading within Erase

Suspended Sector
Reading within Non-Erase

Suspended Sector
Erase-Suspend-Program

1 No toggle 0 N/A Toggle 1

Data Data Data Data Data 1

7I/O

Toggle 0 N/A N/A 0

Notes:

1. I/O7 and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further

details.

2. I/O5 switches to “1” when an Embedded Program or Embedded Erase operation has exceeded the maximum timing

limits. See “I/O5: Exceeded Timing Limits” for more information.

Maximum Negative Input Overshoot

20ns 20ns

+0.8V

-0.5V

-2.0V

Maximum Positive Input Overshoot

VCC+2.0V

VCC+0.5V

2.0V

20ns

20ns

20ns20ns

PRELIMINARY (September, 2002, Version 0.2) 21 AMIC Technology, Inc.

A29L800 Series

VCC Standby Current During Reset

DC Characteristics

CMOS Compatible (TA=0°°C to 70°°C or -45°°C to +85°°C)

Parameter

Symbol

ILI Input Load Current

ILIT A9 Input Load Current VCC = VCC Max, A9 =12.5V 35
ILO Output Leakage Current

ICC1

ICC2
ICC3

ICC4

ICC5

VIL Input Low Level

VIH Input High Level
VID

VOL Output Low Voltage
VOH1
VOH2

Notes:

1. The ICC current listed is typically less than 2 mA/MHz, withOEat VIH. Typical VCC is 3.0V.

2. Maximum ICC specifications are tested with VCC = VCC max.

3. ICC active while Embedded Algorithm (program or erase) is in progress.

4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30ns. Typical sleep mode
current is 200nA.

5. Not 100% tested.

Parameter Description

VCC Active Read Current

(Notes 1, 2)

VCC Active Write (Program/Erase)
Current (Notes 2, 3, 4)

VCC Standby Current (Note 2)

(Note 2)
Automatic Sleep Mode

(Note 2, 4, 5)

Voltage for Autoselect and

Temporary Unprotect Sector

Output High Voltage

Test Description

VIN = VSS to VCC. VCC = VCC Max

VOUT = VSS to VCC. VCC = VCC Max

= VIL, OE = VIH

CE

Byte Mode

= VIL, OE = VIH

CE

Word Mode

= VIL, OE =VIH

CE

= VIH,

CE

RESET

VIH = VCC ± 0.3V; VIL = VSS ± 0.3V

VCC = 3.3 V

IOL = 4.0mA, VCC = VCC Min
IOH = -2.0 mA, VCC = VCC Min
IOH = -100 µA, VCC = VCC Min

RESET

= VSS ± 0.3V

= VCC ± 0.3V

5 MHz
1 MHz

5 MHz
1 MHz

Min.

0.2 5

-0.5

0.7 x VCC

11.5

0.85 x VCC
VCC - 0.4

Typ.

20

0.2

0.2 5

Max. Unit

±1.0 µA

±1.0

9 16
2 4
9

2

VCC + 0.3 V

12.5

0.45

µA
µA

16

4

30 mA

5

0.8

mA

µA
µA

µA

V

V
V

V
V

PRELIMINARY (September, 2002, Version 0.2) 22 AMIC Technology, Inc.

A29L800 Series

DC Characteristics (continued)

Zero Power Flash

25

20

15

10

Supply Current in mA

5

0

0 500 1000 1500 2000 2500 3000 3500 4000

Time in ns

Note: Addresses are switching at 1MHz

10

8

6

4

Supply Current in mA

2

0

1 2 3 4 5

ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)

3.6V

2.7V

Frequency in MHz

C25T :Note °=

Typical ICC1 vs. Frequency

PRELIMINARY (September, 2002, Version 0.2) 23 AMIC Technology, Inc.

A29L800 Series

AC Characteristics

Read Only Operations (TA=0°°C to 70°°C or -45°°C to +85°°C)

Parameter Symbols Speed

JEDEC

tAVAV tRC
tAVQV tACC

tELQV tCE
tGLQV tOE

Std

Read Cycle Time (Note 1)

Address to Output Delay

Chip Enable to Output Delay
Output Enable to Output Delay

tOEH

tEHQZ tDF

Output Enable Hold
Time (Note 1)

Chip Enable to Output High Z
(Notes 1)

tGHQZ

tDF

Output Enable to Output High Z

(Notes 1)

tAXQX tOH

Output Hold Time from Addresses, CEor

, Whichever Occurs First (Note 1)

OE

Description Test Setup

Read

Toggle and

Polling

Data

CE

OE
OE

= VIL
= VIL

= VIL

Min.
Max.

Max.
Max.
Min.

Min. 10 10

Max. 25 30

Min. 0 0 ns

-70

70
70

70
30

0

25 30

Notes:

1. Not 100% tested.

2. See Test Conditions and Test Setup for test specifications.

-90

90
90

90
35

0

Unit

ns
ns

ns

ns
ns

ns

ns

ns

Timing Waveforms for Read Only Operation

tRC

Addresses Addresses Stable

tACC

CE

tOE

tCE

OE

WE

Output

RESET

RY/BY

tOEH

High-Z

0V

Output Valid

tDF

tOH

High-Z

PRELIMINARY (September, 2002, Version 0.2) 24 AMIC Technology, Inc.

A29L800 Series

AC Characteristics
Hardware Reset (

Parameter

JEDEC Std

Note: Not 100% tested.

RESET

tREADY

tREADY

Timings

tRP
tRH
tRB

tRPD

RESET

RESET

Algorithms) to Read or Write (See Note)

RESET

Algorithms) to Read or Write (See Note)

RESET
RESET

RY/BY Recovery Time

RESET

RY/BY

CE, OE

) (TA=0°°C to 70°°C or -45°°C to +85°°C)

Description Test Setup All Speed Options Unit

Pin Low (During Embedded

Pin Low (Not During Embedded

Pulse Width
High Time Before Read (See Note)

Low to Standby Mode

Max 20

Max 500 ns

Min 500 ns
Min 50 ns
Min 0 ns

Min 20

µs

µs

RESET

RY/BY

CE, OE

RESET

tRH

tRP

tReady

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

tReady

~

~

~

~

~

~

tRP

tRB

PRELIMINARY (September, 2002, Version 0.2) 25 AMIC Technology, Inc.

A29L800 Series

Temporary Sector Unprotect (TA=0°°C to 70°°C or -45°°C to +85°°C)

Parameter

JEDEC Std

Note: Not 100% tested.

Temporary Sector Unprotect Timing Diagram

RESET

tVIDR VID Rise and Fall Time (See Note) Min 500 ns

Setup Time for Temporary Sector

CE

WE

RY/BY

RESET

tRSP

Unprotect

12V

0 or 3V

tVIDR tVIDR

Description All Speed Options Unit

Program or Erase Command Sequence

tRSP

~

~
~

~

~

~
~

~

Min 4

µs

0 or 3V

PRELIMINARY (September, 2002, Version 0.2) 26 AMIC Technology, Inc.

A29L800 Series

BYTE

BYTE

BYTE

BYTE

BYTE

BYTE

AC Characteristics

Word/Byte Configuration (

Parameter

JEDEC Std

tELFL/tELFH

tFLQZ

tHQV

CE

Timings for Read Operations

CE

OE

BYTE

BYTE

Switching

from word to

byte mode

I/O0-I/O14

I/O15 (A-1)

BYTE

) (TA=0°°C to 70°°C or -45°°C to +85°°C)

Description

to

Switching Low or High
Switching Low to Output High-Z
Switching High to Output Active

t

ELFL

t

t

ELFH

FLQZ

Data Output

(I/O0-I/O14)

I/O

15

Output

All Speed Options

Unit

-70 -90

Max 5 ns
Max 25 30 ns

Min 70 90 ns

Data Output

(I/O0-I/O7)

Address Input

Data Output

(I/O0-I/O7)

BYTE

I/O0-I/O14

Switching

from byte to

word mode

I/O15 (A-1)

Address Input

t

FHQV

Timings for Write Operations

CE

WE

BYTE

tSET

(tAS)

Note:

Refer to the Erase/Program Operations table for tAS and tAH specifications.

Data Output

(I/O0-I/O14)

I/O

15

Output

The falling edge of the last WE signal

tHOLD(tAH)

PRELIMINARY (September, 2002, Version 0.2) 27 AMIC Technology, Inc.

A29L800 Series

WE

AC Characteristics

Erase and Program Operations (TA=0°°C to 70°°C or -45°°C to +85°°C)

Parameter Speed

JEDEC

tAVAV
tAVWL tAS
tWLAX tAH
tDVWH tDS
tWHDX tDH

tGHWL tGHWL

tELWL tCS
tWHEH

tWLWH tWP
tWHWL

tWHWH1 tWHWH1

Std

tWC

tOES

tCH

tWPH

Write Cycle Time (Note 1)

Address Setup Time
Address Hold Time
Data Setup Time

Data Hold Time
Output Enable Setup Time
Read Recover Time Before Write

(OE high to

Setup Time

CE

Hold Time

CE

Write Pulse Width
Write Pulse Width High

Byte Programming Operation
(Note 2)

low)

Description

-70

Min.
Min.
Min.
Min.
Min.
Min.

Min.

Min.
Min.
Min.
Min.

Byte Typ. 5

Word Typ. 7

70

45
35

35

0

0
0

0

0
0

30

-90

90

45
45

35

Unit

ns
ns
ns
ns
ns
ns

ns

ns
ns
ns
ns

µs

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ. 0.7 sec

Notes:

1. Not 100% tested.

2. See the "Erase and Programming Performance" section for more information.

tvcs

tRB

tBUSY

VCC Set Up Time (Note 1)

Recovery Time from RY/BY
Program/Erase Valid to RY/BY Delay

Min.

Min
Min

50

0

90

µs
ns
ns

PRELIMINARY (September, 2002, Version 0.2) 28 AMIC Technology, Inc.

A29L800 Series

Timing Waveforms for Program Operation

Addresses

CE

OE

WE

Data

RY/BY

VCC

tVCS

Program Command Sequence (last two cycles)

tWC

555h

tCH

tWP

tCS

tDS

A0h PD

tAS

PA

tAH

tWPH

tDH

~
~

~

~

~

~

tBUSY

~
~

Read Status Data (last two cycles)

~

PA

~
~

~

tWHWH1

~

~

Status

~
~

PA

DOUT

tRB

Note :

1. PA = program addrss, PD = program data, Dout is the true data at the program address.

2. Illustration shows device in word mode.

PRELIMINARY (September, 2002, Version 0.2) 29 AMIC Technology, Inc.

A29L800 Series

Timing Waveforms for Chip/Sector Erase Operation

Addresses

CE

OE

WE

Data

RY/BY

VCC

tVCS

Erase Command Sequence (last two cycles)

tWC

2AAh

tCH

tWP

tCS

tDS

55h 30h

tAS

SA

555h for chip erase

tWPH

tDH

10h for chip erase

tAH

~

~

~

~

~

~

~

~

~

~

~

~

tBUSY

~

~

~

~

tWHWH2

Read Status Data

VA

In

Progress

VA

Complete

tRB

Note :

1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operaion Ststus").

2. Illustratin shows device in word mode.

PRELIMINARY (September, 2002, Version 0.2) 30 AMIC Technology, Inc.

A29L800 Series

Timing Waveforms for

Addresses

CE

tCH

OE

tOEH

WE

I/O7

I/O0 - I/O6

High-Z

Polling (During Embedded Algorithms)

Data

tRC

tACC

tCE

tOE

tDF

tOH

Complement

Status Data

~

~

VAVA VA

~

~

~

~

~

~

~

~

Complement True

~

~

Status Data True

~

~

Valid Data

High-Z

High-Z

Valid Data

tBUSY

RY/BY

~

~

Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data
read cycle.

PRELIMINARY (September, 2002, Version 0.2) 31 AMIC Technology, Inc.

A29L800 Series

Timing Waveforms for Toggle Bit (During Embedded Algorithms)

Addresses

CE

OE

WE

I/O6 , I/O2

RY/BY

tCH

tOEH

High-Z

tBUSY

tACC

tCE

tRC

VAVA VA

tOE

tDF

tOH

Valid Status

(first read) (second read) (stop togging)

Valid Status Valid Status Valid Data

~

~

VA

~

~

~

~

~

~

~

~

~

~

~

~

Note: VA = Valid Address; not required for I/O6. Illustration shows first two status cycle after command sequence, last status

read cycle, and array data read cycle.

PRELIMINARY (September, 2002, Version 0.2) 32 AMIC Technology, Inc.

A29L800 Series

Timing Waveforms for Sector Protect/Unprotect

VID

RESET

SA, A6,

A1, A0

Data

CE

WE

OE

Note : For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0

VIH

~

~

Valid* Valid* Valid*

~

Sector Protect/Unprotect Verify

60h 60h 40h Status

1us

Sector Protect:150us

Sector Unprotect:15ms

~

~

~

~

~

PRELIMINARY (September, 2002, Version 0.2) 33 AMIC Technology, Inc.

A29L800 Series

WE

WE

Timing Waveforms for I/O2 vs. I/O6

Enter

Embedded

Erasing

WE

Erase

Erase

Suspend

~

~

~

~

Erase Suspend

Read

Enter Erase

Suspend Program

~

~

Erase
Suspend
Program

Resume

~

~

Erase Suspend

Read

Erase

Erase

~

~

Erase

Complete

I/O6

I/O2

Note : Both I/O6 and I/O2 toggle with OE or CE. See the text on I/O6 and I/O2 in the section "Write Operation Status" for
more information.

~

~

~

~

I/O2 and I/O6 toggle with OE and CE

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

~

AC Characteristics

Erase and Program Operations

Alternate CE Controlled Writes (TA=0°C to 70°C or -45°C to +85°C)

Parameter

JEDEC Std

tAVAV tWC Write Cycle Time (Note 1) Min. 70 90 ns
tAVEL tAS Address Setup Time Min. 0 ns
tELAX tAH Address Hold Time Min. 45 45 ns
tDVEH tDS Data Setup Time Min. 35 45 ns
tEHDX tDH Data Hold Time Min. 0 ns

tOES Output Enable Setup Time Min. 0 ns

tGHEL tGHEL

tWLEL tWS
tEHWH tWH

tELEH tCP
tEHEL tCPH

tWHWH1 tWHWH1

Read Recover Time Before Write
(OE High to WE Low)

Setup Time
Hold Time

Pulse Width

CE

Pulse Width High

CE

Programming Operation
(Note 2)

Description Speed Unit

Min. 0 ns

Min. 0 ns
Min. 0 ns
Min. 35 35 ns

Min. 30 ns

Byte Typ. 5

Word Typ. 7

-70 -90

µs

tWHWH2 tWHWH2

Notes:

3. Not 100% tested.

4. See the "Erase and Programming Performance" section for more information.

PRELIMINARY (September, 2002, Version 0.2) 34 AMIC Technology, Inc.

Sector Erase Operation (Note 2) Typ. 0.7

sec

A29L800 Series

Timing Waveforms for Alternate CE Controlled Write Operation

555 for program

2AA for erase

Addresses

WE

OE

CE

tWS

PA for program
SA for sector erase
555 for chip erase

tAStWC

tWH

tCP

tCPH

tDS

tDH

tAH

tBUSY

Data Polling

~

~

~

~

~

~

~

~

WHWH1 or 2

t

~

~

PA

~

Data

tRH

RESET

RY/BY

Note :

1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O7 = Complement of Data Input, D

2. Figure indicates the last two bus cycles of the command sequence.

A0 for program
55 for erase

PD for program
30 for sector erase
10 for chip erase

~

~

~

~

~

I/O7

OUT

D

OUT

= Array Data.

Erase and Programming Performance

Parameter Typ. (Note 1) Max. (Note 2) Unit Comments

Sector Erase Time 1.0 8 sec
Chip Erase Time 35 sec
Byte Programming Time 35 300
Word Programming Time 12 500

Chip Programming Time
(Note 3)

Byte Mode 11 33 sec

Word Mode 7.2 21.6 sec

µs
µs

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0V VCC, 10,000 cycles. Additionally,
programming typically assumes checkerboard pattern.

2. Under worst case conditions of 90°C, VCC = 2.7V, 100,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only
then does the device set I/O5 = 1. See the section on I/O5 for further information.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See
Table 5 for further information on command definitions.

6. The device has a guaranteed minimum erase and program cycle endurance of 10,000 cycles.

Excludes 00h programming
prior to erasure

Excludes system-level
overhead (Note 5)

PRELIMINARY (September, 2002, Version 0.2) 35 AMIC Technology, Inc.

A29L800 Series

Latch-up Characteristics

Description Min. Max.

Input Voltage with respect to VSS on all I/O pins

-1.0V VCC+1.0V
VCC Current
Input voltage with respect to VSS on all pins except I/O pins

(including A9, OEand

Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at time.

RESET

)

TSOP and SOP Pin Capacitance

Parameter Symbol Parameter Description

CIN Input Capacitance

COUT

CIN2 Control Pin Capacitance

Notes:

1. Sampled, not 100% tested.

2. Test conditions TA = 25°C, f = 1.0MHz

Output Capacitance

Test Setup

VOUT=0

Data Retention

Parameter

Minimum Pattern Data Retention Time

Test Conditions

150°C
125°C

VIN=0

VIN=0

-100 mA

-1.0V

Typ.

6

8.5

7.5

Min

10
20 Years

+100 mA

12.5V

Max.

7.5 pF
12

9

Unit

Years

Unit

pF
pF

PRELIMINARY (September, 2002, Version 0.2) 36 AMIC Technology, Inc.

A29L800 Series

Test Conditions

Test Specifications

Test Condition -70 -90 Unit

Output Load 1 TTL gate
Output Load Capacitance, CL(including jig capacitance) 30 100 pF
Input Rise and Fall Times 5 5 ns
Input Pulse Levels 0.0 - 3.0 0.0 - 3.0 V
Input timing measurement reference levels 1.5 1.5 V
Output timing measurement reference levels 1.5 1.5 V

Test Setup

3.3 V

2.7 K

Ω

Device

Under

Test

CL

6.2 K

Ω

Diodes = IN3064 or Equivalent

PRELIMINARY (September, 2002, Version 0.2) 37 AMIC Technology, Inc.

A29L800 Series

Ordering Information
Top Boot Sector Flash

Part No. Access Time

(ns)

A29L800TM-70 44Pin SOP
A29L800TV-70 48Pin TSOP
A29L800TG-70
A29L800TM-90 44Pin SOP
A29L800TV-90 48Pin TSOP
A29L800TV-90U 48Pin TSOP
A29L800TG-90 48-ball TFBGA
A29L800TG-90U

70 9 20 0.2

90 9 20 0.2

Active Read

Current

Typ. (mA)

Program/Erase

Current

Typ. (mA)

Standby

Current

Typ. (µA)

Package

48-ball TFBGA

48-ball TFBGA

Bottom Boot Sector Flash

Part No. Access Time

(ns)

A29L800UM-70 44Pin SOP

Active Read

Current

Typ. (mA)

Program/Erase

Current

Typ. (mA)

Standby

Current

Typ. (µA)

Package

A29L800UV-70 48Pin TSOP
A29L800UG-70
A29L800UM-90 44Pin SOP
A29L800UV-90 48Pin TSOP
A29L800UV-90U 48Pin TSOP
A29L800UG-90 48-ball TFBGA
A29L800UG-90U

70 9 20 0.2

48-ball TFBGA

90 9 20 0.2

48-ball TFBGA

PRELIMINARY (September, 2002, Version 0.2) 38 AMIC Technology, Inc.

A29L800 Series

Package Information
SOP 44L Outline Dimensions unit: inches/mm

44

23

E

HE

Gauge Plane

θ

0.010"

1

22

b

L

Detail F

D

C

A

A2

S

Seating Plane

y

D

e

A1

See Detail F

L1

Symbol

A - - 0.118 - - 3.00
A1 0.004 - - 0.10 - ­A2 0.103 0.106 0.109 2.62 2.69 2.77

b 0.013 0.016 0.020 0.33 0.40 0.50
C 0.007 0.008 0.010 0.18 0.20 0.25
D - 1.122 1.130 - 28.50 28.70
E 0.490 0.496 0.500 12.45 12.60 12.70

e

HE 0.620 0.631 0.643 15.75 16.03 16.33

L 0.024 0.032 0.040 0.61 0.80 1.02

L1 - 0.0675 - - 1.71 -

S - - 0.045 - - 1.14

y - - 0.004 - - 0.10

θ 0°

Dimensions in inches Dimensions in mm

Min Nom Max Min Nom Max

- 0.050 - - 1.27 -

-

8° 0°

-

8°

Notes:

1. The maximum value of dimension D includes end flash.

2. Dimension E does not include resin fins.

3. Dimension S includes end flash.

PRELIMINARY (September, 2002, Version 0.2) 39 AMIC Technology, Inc.

A29L800 Series

Package Information
TSOP 48L (Type I) Outline Dimensions unit: inches/mm

D

D1

1

24 25

Detail "A"

48

c

E

0.25

A

A1

A2

y

D

b

e

S

θ

L

Detail "A"

Symbol

A - - 0.047 - - 1.20

A1 0.002 - 0.006 0.05 - 0.15
A2 0.037 0.039 0.042 0.94 1.00 1.06

b 0.007 0.009 0.011 0.18 0.22 0.27

c 0.004 - 0.008 0.12 - 0.20
D 0.779 0.787 0.795 19.80 20.00 20.20

D1 0.720 0.724 0.728 18.30 18.40 18.50

E - 0.472 0.476 - 12.00 12.10

e 0.020 BASIC 0.50 BASIC

L 0.016 0.020 0.024 0.40 0.50 0.60
S 0.011 Typ. 0.28 Typ.

y - - 0.004 - - 0.10

θ

Dimensions in inches Dimensions in mm

Min Nom Max Min Nom Max

0° - 8° 0° - 8°

Notes:

1. The maximum value of dimension D includes end flash.

2. Dimension E does not include resin fins.

3. Dimension S includes end flash.

PRELIMINARY (September, 2002, Version 0.2) 40 AMIC Technology, Inc.

A29L800 Series

Package Information

48LD CSP (6 x 8 mm) Outline Dimensions unit: mm

(48TFBGA)

TOP VIEW

BOTTOM VIEW

b

H
G

F

E
D
C

B

A

C

0.10 C

1 2 3 4 5 6

Ball*A1 CORNER

SIDE VIEW

SEATING PLANE

A1

H
G
F
E
D
C
B
A

e

D1

D

A

e

E

E1

Symbol

A - - 1.20

A1 0.20 0.25 0.30

b 0.30 - 0.40

D 5.90 6.00 6.10

D1 4.00 BSC

e - 0.80 -

E 7.90 8.00 8.10

E1 5.60 BSC

Dimensions in mm

Min.

Nom. Max.

PRELIMINARY (September, 2002, Version 0.2) 41 AMIC Technology, Inc.