Datasheet A29L400A Datasheet (AMIC)

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Page 1

A29L400A Series

512K X 8 Bit / 256K X 16 Bit CMOS 3.0 Volt-only,

Preliminary Boot Sector Flash Memory

Document Title 512K X 8 Bit / 256K X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory

Revision History

Rev. No.

History Issue Date Remark

0.0 Initial issue July 24, 2005 Preliminary

PRELIMINARY (July, 2005, Version 0.0)

AMIC Technology, Corp.

Page 2

A29L400A Series

512K X 8 Bit / 256K X 16 Bit CMOS 3.0 Volt-only,

Preliminary Boot Sector Flash Memory

Features

 Single power supply operation

- Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications

- Regulated voltage range: 3.0 to 3.6 volt read and write operations for compatibility with high performance 3.3 volt microprocessors

 Access times:

- 70/90 (max.)

 Current:

- 4 mA typical active read current

- 20 mA typical program/erase current

- 200 nA typical CMOS standby

- 200 nA Automatic Sleep Mode current

 Flexible sector architecture

- 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX7 sectors

- 8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX7 sectors

- Any combination of sectors can be erased

- Supports full chip erase

- Sector protection:

A hardware method of protecting sectors to prevent any inadvertent program or erase operations within that sector. Temporary Sector Unprotect feature allows code changes in previously locked sectors

 Extended operating temperature range: -40°C ~ +85°C

for –U series

 Unlock Bypass Program Command

- Reduces overall programming time when issuing multiple program command sequence

 Top or bottom boot block configurations available

 Embedded Algorithms

- Embedded Erase algorithm will automatically erase the entire chip or any combination of designated sectors and verify the erased sectors

- Embedded Program algorithm automatically writes and verifies data at specified addresses

 Typical 100,000 program/erase cycles per sector  20-year data retention at 125°C

- Reliable operation for the life of the system

 Compatible with JEDEC-standards

- Pinout and software compatible with single-powersupply Flash memory standard

- Superior inadvertent write protection



 Ready /

- Provides a hard ware method of detecting completion of

 Erase Suspend/Erase Resume

 Hardware reset pin (

 Package options

Polling and toggle bits

Data

- Provides a software method of detecting completion of program or erase operations

pin (RY / BY)

BUSY

program or erase operations

- Suspends a sector erase operation to read data from,

or program data to, a non-erasing sector, then resumes the erase operation

RESET

- Hard ware method to reset the device to reading array data

- 44-pin SOP or 48-pin TSOP (I) or 48-ball TFBGA

)

PRELIMINARY (July, 2005, Version 0.0) 1

AMIC Technology, Corp.

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A29L400A Series

General Description

The A29L400A is an 4Mbit, 3.0 volt-only Flash memory organized as 524,288 bytes of 8 bits or 262,144 words of 16 bits each. The 8 bits of data appear on I/O0 - I/O7; the 16 bits of data appear on I/O

0~I/O15. The A29L400A is offered in 48-

ball TFBGA, 44-pin SOP and 48-Pin TSOP packages. This device is designed to be programmed in-system with the standard system 3.0 volt VCC supply. Additional 12.0 volt VPP is not required for in-system write or erase operations. However, the A29L400A can also be programmed in standard EPROM programmers. The A29L400A has the first toggle bit, I/O

6, which indicates

whether an Embedded Program or Erase is in progress, or it is in the Erase Suspend. Besides the I/O6 toggle bit, the A29L400A has a second toggle bit, I/O

2, to indicate whether

the addressed sector is being selected for erase. The A29L400A also offers the ability to program in the Erase Suspend mode. The standard A29L400A offers access times of 70 and 90ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention the

device has separate chip enable ( and output enable (

) controls.

), write enable (WE)

The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The A29L400A is entirely software command set compatibl e with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is simila r to reading from other Flash or EPROM devices.

Device programming occurs by writing the proper program command sequence. This initiates the Embedded Program algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper program margin.

Device erasure occurs by executing the proper erase command sequence. This initiates the Embedded Erase algorithm - an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper erase margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four.

The host system can detect whether a program or erase operation is complete by observing the RY / reading the I/O7 (

Polling) and I/O6 (toggle) status bits.

Data

pin, or by

After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The A29L400A is fully erased when shipp ed from the factory. The hardware sector protection feature disables operations for both program and erase in any combination of the sectors of memory. This can be achieved via programming equipment.

The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any other sector that is not selected for erasure. True background erase can thus be achieved.

The hardware

RESET

pin terminates any operation in progress and resets the internal state machine to reading array data. The

RESET

pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up

firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. T he system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.

PRELIMINARY (July, 2005, Version 0.0) 2

AMIC Technology, Corp.

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A29L400A Series

Pin Configurations

SOP  TSOP (I)



RY/BY

A17

VSS

I/O

I/O I/O9 I/O2

I/O10

I/O3

I/O11

A7 A6 A5 A4 A3 A2 A1 A0 CE

1 2

3 4 5 6 7 8 9 10 11 12

A29L400A

13 14 15 16 29 17 18 19 20 21

RESET

44 43

WE A8

A10

A11

A12

A13

A14

A15

35 34

A16

BYTE

VSS

I/O15 (A-1)

I/O7 I/O14I/O8

I/O6 I/O13

27 26

I/O5 I/O12

25 24

I/O4

VCC

A14

A13

A12

A11

A10

8 9

10 11

RESET

RY/BY

14 15

A17

24 25

 TFBGA

TFBGA

Top View, Balls Facing Down

A29L400AV

A16A15

BYTE

VSS

I/O15(A-1)

I/O7

I/O14

I/O6

I/O13

I/O5

I/O12

I/O

VCC

I/O11

I/O3

I/O10

33 I/O

32 I/O9 31

I/O1

I/O8

I/O0

VSS

CE A0

A6 B6 C6 D6 E6 F6

A13 A12 A14 A15 A16 BYTE I/O15(A-1) VSS

A5 B5 C5 D5 E5 F5

A9 A8 A10 A11 I/O

7 I/O14 I/O13 I/O6

A4 B4 C4 D4 E4 F4

WE RESET NC NC I/O5 I/O12 VCC I/O4

A3 B3 C3 D3 E3 F3

RY/BY NC NC NC I/O2 I/O10 I/O11 I/O3

A2 B2 C2 D2 E2 F2

A7 A17 A6 A5 I/O0 I/O8 I/O9 I/O1

A1 B1 C1 D1 E1 F1

A3 A4 A2 A1 A0 CE OE VSS

PRELIMINARY (July, 2005, Version 0.0) 3 AMIC Technology, Corp.

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A29L400A Series

Block Diagram

VCC

VSS

RESET

BYTE

A0-A17

CE OE

RY/BY

State

Control

Command

VCC Detector

PGM Voltage

Generator

Timer

Sector Switches

Erase Voltage

Generator

STB

Chip Enable

Output Enable

Logic

Y-Decoder

X-decoder

Address Latch

STB

- I/O

I/O

Input/Output

Buffers

Data Latch

Y-Gating

Cell Matrix

(A-1)

Pin Descriptions

A0 - A17 Address Inputs

I/O0 - I/O14 Data Inputs/Outputs

I/O15 (A-1)

RESET

Pin No. Description

I/O15

Data Input/Output, Word Mode

A-1 LSB Address Input, Byte Mode

BYTE

RY/BY

Chip Enable Write Enable Output Enable Hardware Reset Selects Byte Mode or Word Mode

Ready/

BUSY

- Output

VSS Ground VCC Power Supply

NC Pin not connected internally

PRELIMINARY (July, 2005, Version 0.0) 4 AMIC Technology, Corp.

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A29L400A Series

Absolute Maximum Ratings*

Storage Temperature Plastic Packages. . . .-65°C to + 150°C

Ambient Temperature with Power Applied.. -55°C to + 125°C Voltage with Respect to Ground

VCC (Note 1) . . . . . . . . . . . . . . . . . . . . . ……. -0.5V to +4.0V

A9,

RESET

(Note 2) . . . . . . . . . . . ….. -0.5 to +12.5V

All other pins (Note 1) . . . . . . . . . . . . …-0.5V to VCC + 0.5V

Output Short Circuit Current (Note 3) . . …. . . . . . . 200mA

Notes:

1. Minimum DC voltage on input or I/O pins is -0.5V. During

voltage transitions, input or I/O pins may undershoot VSS to -2.0V for periods of up to 20ns. Maximum DC voltage on input and I/O pins is VCC +0.5V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0V for periods up to 20ns.

2. Minimum DC input voltage on A9,

0.5V. During voltage transitions, A9,

and

RESET

and

is -

RESET

may overshoot VSS to -2.0V for periods of up to 20ns. Maximum DC input voltage on A9 is +12.5V which may overshoot to 14.0V for periods up to 20ns.

3. No more than one output is shorted at a time. Duration of

the short circuit should not be greater than one second.

Device Bus Operations

This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the

*Comments

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of these specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.

Operating Ranges

Commercial (C) Devices

Ambient Temperature (T

A) . . . . . . . . . . . . . . . . 0°C to +70°C

Extended Range Devices

Ambient Temperature (T

A) . . . . . . . . . . . . . . . -40°C to +85°C

VCC Supply Voltages

VCC for all devices . . . . . . . . . . . . . . .. . . . . . +2.7V to +3.6V

Operating ranges define those limits between which the functionally of the device is guaranteed.

command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The appropriate device bus operations table lists the inputs and control levels required, and the resulting output. The following subsections describe each of these operations in further detail.

Table 1. A29L400A Device Bus Operations

RESET

A0 – A17

(Note 1)

I/O0 - I/O7

BYTE

Read L L H H AIN DOUT DOUT I/O8~I/O4=High-Z

Write L H L H AIN DIN DIN High-Z CMOS Standby

VCC ± 0.3 V

X X

VCC ± 0.3 V

X High-Z High-Z High-Z Output Disable L H H H X High-Z High-Z High-Z Hardware Reset X X X L X High-Z High-Z High-Z Sector Protect

(See Note 2) Sector Unprotect

(See Note 2) Temporary Sector

L H L V

X X X V

ID AIN DIN DIN X

Sector Address,

A6=L, A1=H, A0=L

Sector Address,

A6=H, A1=H, A0=L

IN X X

Unprotect

Legend: L = Logic Low = V

IL, H = Logic High = VIH, VID = 12.0 ± 0.5V, X = Don't Care, DIN = Data In, D OUT = Data Out, AIN = Address In

Notes:

1. Addresses are A17:A0 in word mode (

BYTE

=VIH), A17: A

in byte mode (

-1

BYTE

=VIL).

2. See the “Sector Protection/Unprotection” section and Temporary Sector Unprotect for more information.

I/O8 - I/O15 Operation

=VIH

BYTE

I/O

15=A-1

=VIL

PRELIMINARY (July, 2005, Version 0.0) 5 AMIC Technology, Corp.

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A29L400A Series

Word/Byte Configuration

CC2 in the DC Characteristics table represents the active

current specification for the write mode. The "AC

The operate in the byte or word configuration. If the

set at logic ”1”, the device is in word configuration, I/O are active and controlled by

pin determines whether the I/O pins I/O15-I/O0

BYTE

and OE.

BYTE

pin is

15-I/O0

Characteristics" section contains timing specification tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may If the configuration, and only I/O

and OE. I/O8-I/O14 are tri-stated, and I/O15 pin is used

pin is set at logic “0”, the device is in byte

BYTE

0-I/O7 are active and controlled by

as an input for the LSB(A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the selects the device.

data to the output pins. during read operation. The

and OE pins to VIL. CE is the power control and

is the output control and gates array

should remain at VIH all the time

pin determines whether

BYTE

the device outputs array data in words and bytes. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See "Reading Array Data" for more information. Refer to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for the timing waveforms,

CC1 in the DC Characteristics table represents the active

l current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which include s programming data to the device and erasing sectors of

memory), the system must drive

to VIH. For program operations, the

determines whether the device accepts program data in bytes or words, Refer to “Word/Byte Configuration” for more information. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “ Word / Byte Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequence. An erase operation can erase one sector, multiple sectors, or the entire device. The Sector Address Tables indicate the address range that each sector occupies. A "sector address" consists of the address inputs required to uniquely select a sector. See the "Command Definitions" section for details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on I/O read cycle timings apply in this mode. Refer to the "Autoselect Mode" and "Autoselect Command Sequence" sections for more information.

and CE to VIL, and

BYTE

7 - I/O0. Standard

check the status of the operation by reading the status bits

on I/O7 - I/O0. Standard read cycle timings and ICC read

specifications apply. Refer to "Write Operation Status" for

more information, and to each AC Characteristics section for

timing diagrams.

Standby Mode

When the system is not reading or writing to the device, it

can place the device in the standby mode. In this mode,

current consumption is greatly reduced, and the outputs are

placed in the high impedance state, independent of the

input.

The device enters the CMOS standby mode when the CE &

RESET

more restricted voltage range than V

are held at V

pins are both held at VCC ± 0.3V. (Note that this is a

IH.) If

IH, but not within VCC ± 0.3V, the device will be

and

RESET

in the standby mode, but the standby current will be greater.

The device requires the standard access time (tCE) before it

is ready to read data.

If the device is deselected during erasure or programming,

the device draws active current until the operation is

completed.

CC3 and ICC4 in the DC Characteristics tables represent the

standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC +30ns. T he automatic

sleep mode is independent of the

,WEand OE control

signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC4 in the DC Characteristics table represents the automatic sleep mode current specification.

Output Disable Mode

When the OE input is at VIH, output from the device is

disabled. The output pins are placed in the high im pedance

state.

RESET

The

the device to reading array data. When the system drives the

RESET

immediately terminates any operation in progress, tristates

all data output pins, and ignores all read/write attempts for

the duration of the

internal state machine to reading array data. The operation

that was interrupted should be reinitiated once the device is

ready to accept another command sequence, to ensure data

integrity.

Current is reduced for the duration of the

When

: Hardware Reset Pin

RESET

pin provides a hardware method of resetting

pin low for at least a period of tRP, the device

pulse. The device also resets the

RESET

pulse.

RESET

is held at VSS ± 0.3V, the device draws

PRELIMINARY (July, 2005, Version 0.0) 6 AMIC Technology, Corp.

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A29L400A Series

CMOS standby current (ICC4 ). If within VSS ± 0.3V, the standby current will be greater. The

RESET

system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.

RESET

the RY/ operation is complete, which requires a time t Embedded Algorithms). The system can thus monitor

pin may be tied to the system reset circuitry. A

is asserted during a program or erase operation,

pin remains a “0” (busy) until the internal reset

RESET

is held at VIL but not

READY (during

RY/

complete. If

operation is not executing (RY/BY pin is “1”), the reset

operation is completed within a time of t

Embedded Algorithms). The system can read data t

the

Refer to the AC Characteristics tables for

parameters and diagram.

to determine whether the reset operation is

is asserted when a program or erase

READY (not during

RESET

pin return to VIH.

Table 2. A29L400A Top Boot Block Sector Address Table

Sector Size

(Kbytes/Kwords)

SA0 0 0 0 X X X 64/32 00000h - 0FFFFh 00000h - 07FFFh SA1 0 0 1 X X X 64/32 10000h - 1FFFFh 08000h - 0FFFFh SA2 0 1 0 X X X 64/32 20000h - 2FFFFh 10000h - 17FFFh SA3 0 1 1 X X X 64/32 30000h - 3FFFFh 18000h - 1FFFFh SA4 1 0 0 X X X 64/32 40000h - 4FFFFh 20000h - 27FFFh SA5 1 0 1 X X X 64/32 50000h - 5FFFFh 28000h - 2FFFFh SA6 1 1 0 X X X 64/32 60000h - 6FFFFh 30000h - 37FFFh SA7 1 1 1 0 X X 32/16 70000h - 77FFFh 38000h - 3BFFFh SA8 1 1 1 1 0 0 8/4 78000h - 79FFFh 3C000h - 3CFFFh SA9 1 1 1 1 0 1 8/4 7A000h - 7BFFFh 3D000h - 3DFFFh

SA10 1 1 1 1 1 X 16/8 7C000h - 7FFFFh 3E000h - 3FFFFh

Address Range (in hexadecimal) Sector A17 A16 A15 A14 A13 A12

(x8)

Address Range

(x16)

Address Range

RH after

RESET

Table 3. A29L400A Bottom Boot Block Sector Address Table

Sector Size

(Kbytes/Kwords)

Address Range

SA0 0 0 0 0 0 X 16/8 00000h - 03FFFh 00000h - 01FFFh SA1 0 0 0 0 1 0 8/4 04000h - 05FFFh 02000h - 02FFFh SA2 0 0 0 0 1 1 8/4 06000h - 07FFFh 03000h - 03FFFh SA3 0 0 0 1 X X 32/16 08000h - 0FFFFh 04000h - 07FFFh SA4 0 0 1 X X X 64/32 10000h - 1FFFFh 08000h - 0FFFFh SA5 0 1 0 X X X 64/32 20000h - 2FFFFh 10000h - 17FFFh SA6 0 1 1 X X X 64/32 30000h - 3FFFFh 18000h - 1FFFFh SA7 1 0 0 X X X 64/32 40000h - 4FFFFh 20000h - 27FFFh SA8 1 0 1 X X X 64/32 50000h - 5FFFFh 28000h - 2FFFFh SA9 1 1 0 X X X 64/32 60000h - 6FFFFh 30000h - 37FFFh

SA10 1 1 1 X X X 64/32 70000h - 7FFFFh 38000h - 3FFFFh

(x8)

Address Range Sector A17 A16 A15 A14 A13 A12

(x16)

Address Range

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A29L400A Series

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on I/O7 - I/O0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires V

ID (11.5V to 12.5 V) on address pin A9. Address

pins A6, A1, and A0 must be as shown in Autoselect Co de s ( Hig h V ol ta ge M et ho d) ta ble . I n addition, when

verifying sector protection, the sector address must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows the remaining address bits that are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on I/O

7 - I/O0.To access the

autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require VID. See "Command Definitions" for details on using the autoselect mode.

Table 4. A29L400A Autoselect Codes (High Voltage Method)

Description Mode

I/O

A17

A11

A12

A9 A8

A10

A6 A5

A1 A0 I/O

I/O

Manufacturer ID: AMIC L L H X X VID X L X L L X 37h

Word B3h 34h Device ID: A29L400A (Top Boot Block)

Byte

L L H X X V

ID XLXL H

X 34h

Word B3h B5h Device ID: A29L400A (Bottom Boot

Byte

L L H X X V

ID XLXL H

X B5h

Block) Continuation ID L L H X X VID XLXHH X 7Fh

01h

(protected)

00h

(unprotected)

Sector Protection Verification

L L H SA X VID XLXHL

L=Logic Low= VIL, H=Logic High=VIH, SA=Sector Address, X=Don’t Care. Note: The autoselect codes may also be accessed in-system via command sequences.

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A29L400A Series

Sector Protection/Unprotection

The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. It is possible to determine whether a sector is protected or unprotected. See “Autoselect Mode” for details. Sector protection / unprotection can be implemented via two methods. The primary method requires VID on the

RESET

pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithm and the Sector Protect / Unprotect Timing Diagram illustrates the timing waveforms for this feature. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. The alternate method must be implemented using programming equipment. The procedure requires a high voltage (V

ID) on

address pin A9 and the control pins. The device is shipped with all sectors unprotected. It is possible to determine whether a sector is protected or unprotected. See "Autoselect Mode" for details.

Hardware Data Protection

The requirement of command unlocking sequence for programming or erasing provides data protection against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up transitions, or from system noise. The device is powered up to read array data to avoid accidentally writing data to the array.

Temporary Sector Unprotect

This feature allows temporary unprotection of previous protected sectors to change data in-system. The Sector

Unprotect mode is activated by setting the

RESET

During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses.

Once V

ID is removed from the

RESET

pin, all the previously protected sectors are protected again. Figure 1 shows the algorithm, and the Temporary Sector Unprotect diagram

shows the timing waveforms, for this feature.

START

RESET = VID

(Note 1)

Perform Erase or

Program Operations

RESET = VIH

pin to VID.

Write Pulse "Glitch" Protection

Noise pulses of less than 5ns (typical) on OE, CE or WE do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE=VIL,

= VIH or WE = VIH. To initiate a write cycle, CE and

must be a logical zero while OE is a logical one.

Power-Up Write Inhibit

= CE = VIL and OE = VIH during power up, the

device does not accept commands on the rising edge of

. The internal state machine is automatically reset to

reading array data on the initial power-up.

Temporary Sector

Unprotect

Completed (N ote 2)

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once again.

Figure 1. Temporary Sector Unprotect Operation

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A29L400A Series

Temporary Sector

Unprotect Mode

Increment

PLSCNT

START

PLSCNT=1

RESET=VID

Wait 1 us

First Write

Cycle=60h?

Set up sector

address

Sector Protect

Write 60h to sector

address with A6=0,

A1=1, A0=0

Wait 150 us

Verify Sector

Protect: Wr ite 40h

to sector address with A6=0, A1=1,

A0=0

Read from

sector address

with A6=0,

A1=1, A0=0

Yes

Reset

PLSCNT=1

Protect all sectors:

The indicated portion of

the sector protect

algorithm must be

performed for all

unprotected sectors prior

to issuing the first sector

unprotect address

Increment

PLSCNT

START

PLSCNT=1

RESET=VID

Wait 1 us

First Write

Cycle=60h?

All sectors protected?

Set up first sector

address

Sector Unprotect: Write 60h to sector address with A6=1,

A1=1, A0=0

Wait 500 ms

Verify Sector

Unprotect : Write

40h to sector

address with A6=1,

A1=1, A0=0

Yes

Temporary Sector

Unprotect Mode

PLSCNT

=25?

Yes

Device failed

Sector Protect

Algorithm

Data=01h?

Yes

Protect another

sector?

Remove VID

from RESET

Write reset

command

Sector Protect

complete

Yes

PLSCNT=

1000?

Yes

Device failed

Sector Unprotect

Algorithm

Figure 2. In-System Sector Protect/Unprotect Algorithms

Read from sector address with A6=1,

A1=1, A0=0

Data=00h?

Last sector

verified?

Remove VID from RESET

Write reset Command

Sector Unprotect

complete

Set up

next sector

address

Yes

PRELIMINARY (July, 2005, Version 0.0) 10 AMIC Technology, Corp.

Page 12

A29L400A Series

Command Definitions

Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data.

All addresses are latched on the falling edge of whichever happens later. All data is latched on the rising

edge of appropriate timing diagrams in the "AC Characteristics" section.

or CE, whichever happens first. Refer to the

or CE,

Reading Array Data

The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See "Erase Suspend/Erase Resume Commands" for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if I/O5 goes high, or while in the autoselect mode. See the "Reset Command" section, next. See also "Requirements for Reading Array Data" in the "Device Bus Operations" section for more information. The Read Operations table provides the read parameters, and Read Operation Timings diagram shows the timing diagram.

Reset Command

Writing the reset command to the device resets the device to reading array data. Address bits are don't care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If I/O5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. The Command Definitions table shows the address and data requirements. This method is an alternative to that shown in the Autoselect Codes (High Voltage Method) table, which is intended for PROM programmers and requires VID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code and another read cycle at XX03h retrieves the continuation code. A read cycle at address XX01h returns the device code. A read cycle containing a sector address (SA) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. Refer to the Sector Address tables for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data.

Word/Byte Program Command Sequence

The system may program the device by word or byte, depending on the state of the

four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verify the programmed cell margin. Table 5 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are longer latched. The system can determine the status of the

program operation by using I/O Operation Status” for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. T he Byte Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set I/O5

to “1”, or cause the operation was successful. However, a succeeding read will show that the data is still “0”. Only erase operations can

convert a “0” to a “1”.

Polling algorithm to indicate the

Data

pin. Programming is a

BYTE

7, I/O6, or RY/

. See “Write

PRELIMINARY (July, 2005, Version 0.0) 11 AMIC Technology, Corp.

Page 13

A29L400A Series

START

Write Program

Command

Sequence

Embedded

Program

algorithm in

progress

Data Poll

from System

Verify Data ?

Yes

Increment Address

Last Address ?

Yes

Programming

Completed

Note : See the appropriate Command Definitions table for program command sequence.

Figure 3. Program Operation

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 5 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the twocycle unlock bypass reset command sequence. The first

cycle must contain the data 90h; the second cycle the data 00h. Addresses are don’t care for both cycle. The device returns to reading array data. Figure 3 illustrates the algorithm for the program operation. See the Erase/Program Operations in “AC Characteristics” for parameters, and to Program Operation Timings for timing diagrams.

Chip Erase Command Sequence

Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The Command Definitions table shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Embedded Erase algorithm are ignored. The system can determine the status of the erase operation by using I/O7, I/O6, or I/O2. See "Write Operation Status" for information on these status bits. When the Embedded Erase algorithm is complete, the devic e returns to reading array data and addresses are no longer latched. Figure 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in "AC Characteristics" for parameters, and to the Chip/Sector Erase Operation Timings for timing waveforms.

Sector Erase Command Sequence

Sector erase is a six-bus-cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. The Command Definitions table shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase timeout of 50µs begins. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50µs, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50µs, the system need not monitor I/O Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must

3. Any command other than

PRELIMINARY (July, 2005, Version 0.0) 12 AMIC Technology, Corp.

Page 14

A29L400A Series

rewrite the command sequence and any additional sector addresses and commands. The system can monitor I/O3 to determine if the sector erase timer has timed out. (See the " I/O

3: Sector Erase Timer"

section.) The time-out begins from the rising edge of the final

pulse in the command sequence.

Once the sector erase operation has begun, only the Eras e Suspend command is valid. All other commands are ignored. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using I/O7, I/O6, or I/O2. Refer to "Write Operation Status" for information on these status bits. 4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the "AC Characteristics" section for parameters, and to the Sector Erase Operations Timing diagram for timing waveforms.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are "don't cares" when writing the Erase Suspend command. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors produces status data on I/O

- I/O0. The system can use I/O7, or I/O6 and I/O2 together, to determine if a sector is actively erasing or is erasesuspended. See "Write Operation Status" for information on these status bits.

After an erase-suspended program operation is complete, the system can once again read array data within nonsuspended sectors. The system can determine the status of the program operation using the I/O

7 or I/O6 status bits, just

as in the standard program operation. See "Write Operation Status" for more information. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See "Autoselect Command Sequence" for more information. The system must write the Erase Resume command (address bits are "don't care") to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing.

START

Write Erase

Command Sequence

Data Poll

from System

Embedded Erase algorithm in progress

Data = FFh ?

Yes

Erasure Completed

Note :

1. See the appropriate Command Definitions table for erase command sequences.

2. See "I/O

: Sector Erase Timer" for more information.

Figure 4. Erase Operation

PRELIMINARY (July, 2005, Version 0.0) 13 AMIC Technology, Corp.

Page 15

A29L400A Series

Table 5. A29L400A Command Definitions

Command Sequence

(Note 1)

Read (Note 6) 1 RA RD Reset (Note 7) 1 XXX F0

Manufacturer ID

Device ID, Top Boot Block

Device ID, Bottom Boot Block

Continuation ID

Autoselect (Note 8)

Sector Protect Verify

(Note 9)

Program

Unlock Bypass Unlock Bypass Program (Note 10) 2 XXX A0 PA PD

Unlock Bypass Reset (Note 11) 2 XXX 90 XXX 00 Chip Erase

Sector Erase Erase Suspend (Note 12) 1 XXX B0

Erase Resume (Note 13) 1 XXX 30

Legend: X = Don't care RA = Address of the memory location to be read. RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE or CE pulse,

whichever happens later.

PD = Data to be programmed at location PA. Data la tches on th e rising edge o f SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A17 - A12 select a unique sector. Note:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all bus cycles are write operation.

4. Data bits I/O15~I/O8 are don’t care for unlock and comma nd cycles.

5. Address bits A17 - A11 are don't cares for unlock and command cycles, unless SA or PA required.

6. No unlock or command cycles required when reading array data.

7. The Reset command is required to return to reading arra y data when device is in the autoselect mode, or if I/O (while the device is providing status data).

8. The fourth cycle of the autoselect command sequence is a read cycle.

9. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more information.

10. The Unlock Bypass command is required pri or to the Unlock Bypass Program command.

11. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode.

12. The system may read and program in non-erasing secto rs, o r ente r the au to select mode , w hen in the Era se Suspend mode.

13. The Erase Resume command is valid only during the Erase Suspend mode.

Word 555 2AA 555

Byte

Word

Byte

Word

Byte

Word Byte

Word

Byte

Word

Byte

Word 555 2AA 555

Byte

Word

Byte

Word

Byte

First Second Third Fourth Fifth Sixth

Cycles

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

AAA 555

AAA 555 2AA 555 X01 AAA

555 AAA 555

AAA

555 AAA

AAA

555 2AA AAA 555 2AA AAA

555 2AA

555

555 2AA 555 2AA

555

2AA 555

555

Bus Cycles (Notes 2 - 5)

AAA

90 X00 37

555

A0 PA PD

555

or CE pulse, whichever happens first.

B334

X01

X02

X03 X06

(SA) X02

(SA)

X04

555 AAA 555 AAA

B3B5

XX00 XX01

00 01

2AA

555 2AA 555

55 SA 30

555

AAA

5 goes high

PRELIMINARY (July, 2005, Version 0.0) 14 AMIC Technology, Corp.

Page 16

A29L400A Series

Write Operation Status

Several bits, I/O2, I/O3, I/O5, I/O6, I/O7, RY/

are provided in

the A29L400A to determine the status of a write operation. Table 6 and the following subsections describe the functions

of these status bits. I/O

7, I/O6 and RY/BY each offer a

method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first.

I/O7:

The

Polling

Data

Polling bit, I/O7, indicates to the host system

Data

whether an Embedded Algorithm is in progress or completed, or whether the device is in Erase Suspend.

Data

Polling is

valid after the rising edge of the final WE pulse in the program or erase command sequence. During the Embedded Program algorithm, the device outputs

7 the complement of the datum programmed to I/O7.

on I/O This I/O

7 status also applies to programming during Erase

Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to I/O7. The system must provide the program address to read valid status information on I/O7. If a program address falls within a

protected sector,

Polling on I/O7 is active for

Data

approximately 2µs, then the device returns to reading array data.

During the Embedded Erase algorithm,

Data

Polling

produces a "0" on I/O7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode,

Polling produces a "1" on I/O7.This is analogous to the

Data

complement/true datum output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to "1"; prior to this, the device outputs the "complement," or "0." The system must provide an address within any of the sectors selected for erasure to read valid status information on I/O

After an erase command sequence is written, if all sectors selected for erasing are protected,

Polling on I/O7 is

Data

active for approximately 100µs, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. When the system detects I/O complement to true data, it can read valid data at I/O on the following read cycles. This is because I/O change asynchronously with I/O

) is asserted low. The

(

7 has changed from the

7 - I/O0

7 may

0 - I/O6 while Output Enable

Polling Timings (During

Data

Embedded Algorithms) in the "AC Characteristics" section illustrates this. Table 6 shows the outputs for

on I/O

7. Figure 5 shows the

Polling algorithm.

Data

Polling

START

Read I/O7-I/O

Address = VA

I/O7 = Data ?

Note :

1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address.

2. I/O

should be rechecked even if I/O5 = "1" because

I/O

may change simultaneously with I/O5.

I/O5 = 1?

Read I/O7 - I/O

Address = VA

I/O7 = Data ?

FAIL

Yes

PASS

Figure 5. Data Polling Algorithm

PRELIMINARY (July, 2005, Version 0.0) 15 AMIC Technology, Corp.

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A29L400A Series

RY/

The RY/

: Read/

is a dedicated, open-drain output pin that

Busy

indicates whether an Embedded algorithm is in progress or complete. The RY/ the final RY/

is an open-drain output, several RY/BY pins can be

status is valid after the rising edge of

pulse in the command sequence. Since

tied together in parallel with a pull-up resistor to VCC. (The RY/

pin is not available on the 44-pin SOP package)

If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode.

Table 6 shows the outputs for RY/

. Refer to “

RESET

Timings”, “Timing Waveforms for Program Operation” and “Timing Waveforms for Chip/Sector Erase Operation” for more information.

I/O6: Toggle Bit I

Toggle Bit I on I/O6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge

of the final WE pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause I/O6 to toggle.

(The system may use either OE or CE to control the read cycles.) When the operation is complete, I/O6 stops toggling. After an erase command sequence is written, if all sectors

selected for erasing are protected, I/O6 toggles for approximately 100µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use I/O whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), I/O device enters the Erase Suspend mode, I/O However, the system must also use I/O sectors are erasing or erase-suspended. Alternatively, the

system can use I/O Polling"). If a program address falls within a protected sector, I/O toggles for approximately 2µs after the program command sequence is written, then returns to reading array data. I/O

6 also toggles during the erase-suspend-program mode,

and stops toggling once the Embedded Program algorithm is complete. The Write Operation Status table shows the outputs for Toggle Bit I on I/O6. Refer to Figure 6 for the toggle bit algorithm, and to the Toggle Bit Timings figure in the "AC Characteristics" section for the timing diagram. The I/O

6 figure shows the differences between I/O2 and I/O6 in

I/O graphical form. See also the subsection on " I/O II".

6 and I/O2 together to determine

6 toggles. When the

6 stops toggling.

2 to determine which

7 (see the subsection on " I/O7 :

2: Toggle Bit

Data

2 vs.

I/O2: Toggle Bit II

The "Toggle Bit II" on I/O2, when used with I/O6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the

rising edge of the final

pulse in the command

sequence.

2 toggles when the system reads at addresses within

I/O those sectors that have been selected for erasure. (The

system may use either cycles.) But I/O

2 cannot distinguish whether the sector is

actively erasing or is erase-suspended. I/O

to control the read

6, by comparison,

indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 6 to compare outputs for I/O

2 and I/O6.

Figure 6 shows the toggle bit algorithm in flowchart form, and the section " I/O2: Toggle Bit II" explains the algorithm. See also the " I/O

6: Toggle Bit I" subsection. Refer to the

Toggle Bit Timings figure for the toggle bit timing diagram. The I/O2 vs. I/O6 figure shows the differences between I/O2 and I/O

6 in graphical form.

Reading Toggle Bits I/O6, I/O2

Refer to Figure 6 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read I/O7 - I/O0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on I/O7 - I/O0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of I/O5 is high (see the section on I/O again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as I/O5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and I/O gone high. The system may continue to monitor the toggle bit and I/O5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 6).

5). If it is, the system should then determine

5 has not

PRELIMINARY (July, 2005, Version 0.0) 16 AMIC Technology, Corp.

Page 18

A29L400A Series

I/O5: Exceeded Timing Limits

I/O5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions I/O5 produces a "1." This is a failure condition that indicates the program or erase cycle was not successfully completed. The I/O

5 failure condition may appear if the system tries to

program a "1 "to a location that is previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, I/O5 produces a "1." Under both these conditions, the system must issue the reset command to return the device to reading array data.

I/O3: Sector Erase Timer

After writing a sector erase command sequence, the system may read I/O operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out is complete, I/O ignore I/O between additional sector erase commands will always be less than 50µs. See also the "Sector Erase Command Sequence" section. After the sector erase command sequence is written, the

system should read the status on I/O7 ( (Toggle Bit I) to ensure the device has accepted the

command sequence, and then read I/O internally controlled erase cycle has begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If I/O accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of I/O subsequent sector erase command. If I/O second status check, the last command might not have been accepted. Table 6 shows the outputs for I/O

3 to determine whether or not an erase

3 switches from "0" to "1." The system may

3 if the system can guarantee that the time

Polling) or I/O6

Data

3. If I/O3 is "1", the

3 is "0", the device will

3 prior to and following each

3 is high on the

START

Read I/O7-I/O

Toggle Bit

= Toggle ?

I/O5 = 1?

Read I/O7 - I/O

Twice

Toggle Bit

= Toggle ?

Program/Erase

Operation Not

Commplete, Write

Reset Command

Yes

(Note 1)

(Notes 1,2)

Operation Complete

Program/Erase

Notes :

1. Read toggle bit twice to determine whether or not it is toggling. See text.

2. Recheck toggle bit because it may stop toggling as I/O changes to "1". See text.

Figure 6. Toggle Bit Algorithm

PRELIMINARY (July, 2005, Version 0.0) 17 AMIC Technology, Corp.

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A29L400A Series

Table 6. Write Operation Status

Operation

I/O7 I/O6 I/O5 I/O3 I/O2

(Note 1) (Note 2) (Note 1)

Standard Mode

Erase Suspend Mode

Embedded Program Algorithm

7I/O

Toggle 0 N/A No toggle 0

Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0 Reading within Erase

Suspended Sector Reading within Non-Erase

Suspended Sector Erase-Suspend-Program

1 No toggle 0 N/A Toggle 1

Data Data Data Data Data 1

7I/O

Toggle 0 N/A N/A 0

Notes:

1. I/O

7 and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

2. I/O

5 switches to “1” when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “I/O5: Exceeded Timing Limits” for more information.

Maximum Negative Input Overshoot

20ns 20ns

+0.8V

-0.5V

RY/BY

-2.0V

Maximum Positive Input Overshoot

VCC+2.0V

VCC+0.5V

2.0V

20ns

20ns20ns

PRELIMINARY (July, 2005, Version 0.0) 18 AMIC Technology, Corp.

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A29L400A Series

DC Characteristics

CMOS Compatible (TA=0°C to 70°C or -40°C to +85°C)

Parameter

Parameter Description Test Description Min. Typ. Max. Unit

Symbol

ILI Input Load Current VIN = VSS to VCC. VCC = VCC Max

±1.0 µA ILIT A9 Input Load Current VCC = VCC Max, A9 =12.5V 35 ILO Output Leakage Current VOUT = VSS to VCC. VCC = VCC Max

ICC1 VCC Active Read Current

(Notes 1, 2)

ICC2 VCC Active Write (Program/Erase)

= VIL, OE = VIH

Byte Mode

= VIL, OE = VIH

Word Mode

= VIL, OE =VIH

5 MHz 4 10 1 MHz 2 4

20 30 mA

±1.0 µA

Current (Notes 2, 3, 4)

ICC3 VCC Standby Current (Note 2) ICC4

VCC Standby Current During Reset (Note 2)

ICC5

Automatic Sleep Mode

= VIH,

RESET

IH = VCC ± 0.3V; VIL = VSS ± 0.3V

RESET

= VSS ± 0.3V

= VCC ± 0.3V

0.2 5

(Note 2, 4, 5) VIL Input Low Level -0.5 0.8 V VIH Input High Level 0.7 x VCC VCC + 0.3 V VID Voltage for Autoselect and

VCC = 3.3 V 11.5 12.5 V

Temporary Unprotect Sector

VOL Output Low Voltage IOL = 4.0mA, VCC = VCC Min 0.45 V VOH1 IOH = -2.0 mA, VCC = VCC Min 0.85 x VCC V VOH2

Output High Voltage

OH = -100 µA, VCC = VCC Min

VCC - 0.4 V

µA

µA µA

µA

Notes:

1. The ICC current listed is typically less than 2 mA/MHz, withOEat VIH. Typical VCC is 3.0V.

2. Maximum I

3. I

CC active while Embedded Algorithm (program or erase) is in progress.

4. Automatic sleep mode enables the low power mode when addresses remain stable for t

CC specifications are tested with VCC = VCC max.

ACC + 30ns. Typical sleep mode current

is 200nA.

5. Not 100% tested.

PRELIMINARY (July, 2005, Version 0.0) 19 AMIC Technology, Corp.

Page 21

A29L400A Series

DC Characteristics (continued)

Zero Power Flash

Supply Current in mA

0 500 1000 1500 2000 2500 3000 3500 4000

Time in ns

Note: Addresses are switching at 1MHz

Supply Current in mA

12345

CC1

Current vs. Time (Showing Active and Automatic Sleep Currents)

3.6V

2.7V

Frequency in MHz

C25T :Note °=

Typical I

PRELIMINARY (July, 2005, Version 0.0) 20 AMIC Technology, Corp.

CC1

vs. Frequency

Page 22

A29L400A Series

AC Characteristics

Read Only Operations (TA=0°C to 70°C or -40°C to +85°C)

Parameter Symbols Speed

JEDEC

tAVAV tRC tAVQV

tELQV tGLQV tOE

Std

ACC

Read Cycle Time (Note 1)

Address to Output Delay

Chip Enable to Output Delay Output Enable to Output Delay

Output Enable Hold

Time (Note 1)

Chip Enable to Output High Z

tEHQZ

tOEH

(Notes 1)

tGHQZ

Output Enable to Output High Z

(Notes 1) Output Hold Time from Addresses,

tAXQX tOH

or OE, Whichever Occurs First

Description Test Setup

-70

Read

Toggle and

Polling

Data

OE OE

= VIL = VIL

= VIL

Min.

Max.

Max. Max.

Min.

70 70

70 30

Min. 10 10

Max. 25 30

25 30

Min. 0 0 ns

(Note 1)

Notes:

1. Not 100% tested.

2. See Test Conditions and Test Setup for test specifications.

-90

90 90

90 35

Unit

ns ns

ns ns ns

Timing Waveforms for Read Only Operation

Addresses Addresses Stable

ACC

Output

RESET

RY/BY

OEH

High-Z

Output Valid

High-Z

PRELIMINARY (July, 2005, Version 0.0) 21 AMIC Technology, Corp.

Page 23

A29L400A Series

AC Characteristics Hardware Reset (

Parameter

JEDEC Std

Note: Not 100% tested.

RESET

Timings

RY/BY

CE, OE

READY

tRPD

RESET

Algorithms) to Read or Write (See Note)

RESET

Algorithms) to Read or Write (See Note)

tRP tRH tRB

RESET RESET

RY/BY Recovery Time

RESET

) (TA=0°C to 70°C or -40°C to +85°C)

Description Test Setup All Speed Options Unit

Pin Low (During Embedded

Pin Low (Not During Embedded

Pulse Width High Time Before Read (See Note)

Low to Standby Mode

Max 20

Max 500 ns

Min 500 ns Min 50 ns Min 0 ns Min 20

µs

RESET

RY/BY

CE, OE

RESET

Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

Ready

PRELIMINARY (July, 2005, Version 0.0) 22 AMIC Technology, Corp.

Page 24

A29L400A Series

Temporary Sector Unprotect (TA=0°C to 70°C or –40°C to +85°C)

Parameter

JEDEC Std

Note: Not 100% tested.

Temporary Sector Unprotect Timing Diagram

RESET

VIDR VID Rise and Fall Time (See Note) Min 500 ns

Setup Time for Temporary Sector

VIDR

RSP

12V

0 or 3V

RESET

Unprotect

Description All Speed Options Unit

Program or Erase Command Sequence

RSP

~ ~

Min 4

0 or 3V

VIDR

µs

RY/BY

PRELIMINARY (July, 2005, Version 0.0) 23 AMIC Technology, Corp.

Page 25

A29L400A Series

AC Characteristics

Word/Byte Configuration (

Parameter

JEDEC Std

ELFL/tELFH

FLQZ

HQV

BYTE BYTE

Timings for Read Operations

BYTE

Switching

from word to

byte mode

I/O0-I/O

I/O

(A-1)

BYTE

) (TA=0°C to 70°C or -40°C to +85°C)

BYTE

Description

Switching Low or High

BYTE

Switching Low to Output High-Z Switching High to Output Active

ELFL

ELFH

FLQZ

Data Output

(I/O

I/O

Output

All Speed Options

Unit

-70 -90

Max 5 ns Max 25 30 ns

Min 70 90 ns

Data Output

-I/O14)

(I/O

-I/O7)

Address Input

Data Output

(I/O

-I/O7)

BYTE

I/O0-I/O

Switching

from byte to

word mode

I/O

(A-1)

Address Input

FHQV

Timings for Write Operations

BYTE

The falling edge of the last WE signal

BYTE

SET

(tAS)

Note:

Refer to the Erase/Program Operations table for tAS and tAH specifications.

HOLD(tAH

Data Output

(I/O

-I/O14)

I/O

Output

)

PRELIMINARY (July, 2005, Version 0.0) 24 AMIC Technology, Corp.

Page 26

A29L400A Series

AC Characteristics

Erase and Program Operations (TA=0°C to 70°C or -40°C to +85°C)

Parameter Speed

JEDEC

tAVAV tAVWL tWLAX tDVWH tWHDX

tGHWL

tELWL tCS

tWHEH tWLWH tWHWL

tWHWH1 tWHWH1

Std

WC AS

OES

GHWL

WPH

Write Cycle Time (Note 1) Address Setup Time

Address Hold Time

Data Setup Time

Data Hold Time Output Enable Setup Time Read Recover Time Before Write

(

high to WE low)

Setup Time

Hold Time

Write Pulse Width Write Pulse Width High

Byte Programming Operation

(Note 2)

Description

-70

Min.

Min. Min. Min.

45 35

Min. Min.

Min.

Min. Min. Min.

Min.

Byte Typ. 5

Word Typ. 7

0 0

-90

45 45

Unit

ns ns ns ns ns ns

ns ns ns ns

µs

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ. 1.0 sec

BUSY

VCC Set Up Time (Note 1)

vcs RB

Recovery Time from RY/ Program/Erase Valid to RY/

Delay

Min.

Min Min

Notes:

1. Not 100% tested.

2. See the "Erase and Programming Performance" section for more information.

µs ns ns

PRELIMINARY (July, 2005, Version 0.0) 25 AMIC Technology, Corp.

Page 27

A29L400A Series

Timing Waveforms for Program Operation

Addresses

Data

RY/BY

VCC

VCS

Program Command Sequence (last two cycles)

555h

A0h PD

WPH

BUSY

Read Status Data (last two cycles)

WHWH1

Status

OUT

Note :

1. PA = program addrss, PD = program data, Dout is the true data at the program address.

2. Illustration shows device in word mode.

PRELIMINARY (July, 2005, Version 0.0) 26 AMIC Technology, Corp.

Page 28

A29L400A Series

Timing Waveforms for Chip/Sector Erase Operation

Addresses

Data

RY/BY

VCC

VCS

Erase Command Sequence (last two cycles)

2AAh

555h for chip erase

55h 30h

WPH

10h for chip erase

~ ~

BUSY

~ ~

WHWH2

Read Status Data

Progress

Complete

Note :

1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operaion Ststus").

2. Illustratin shows device in word mode.

PRELIMINARY (July, 2005, Version 0.0) 27 AMIC Technology, Corp.

Page 29

A29L400A Series

Timing Waveforms for

Addresses

I/O

Polling (During Embedded Algorithms)

Data

OEH

ACC

Complement

VAVA VA

Complement True

Valid Data

High-Z

- I/O

RY/BY

High-Z

BUSY

Status Data

Status Data True

Valid Data

I/O

Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data read cycle.

High-Z

PRELIMINARY (July, 2005, Version 0.0) 28 AMIC Technology, Corp.

Page 30

A29L400A Series

Timing Waveforms for Toggle Bit (During Embedded Algorithms)

Addresses

I/O6 , I/O2

RY/BY

tCH

tOEH

High-Z

tBUSY

tACC

tCE

tRC

VAVA VA

tOE

tDF

tOH

Valid Status

(first read) (second read) (stop togging)

Valid Status Valid Status Valid Data

Note: VA = Valid Address; not required for I/O6. Illustration shows first two status cycle after command sequence, last status

read cycle, and array data read cycle.

Timing Waveforms for Sector Protect/Unprotect

VID

RESET

SA, A6,

A1, A0

Data

Note : For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0

VIH

Valid* Valid* Valid*

Sector Protect/Unprotect Verify

60h 60h 40h Status

1us

Sector Protect:150us

Sector Unprotect:15ms

PRELIMINARY (July, 2005, Version 0.0) 29 AMIC Technology, Corp.

Page 31

A29L400A Series

Timing Waveforms for I/O2 vs. I/O6

Enter

Embedded

Erasing

I/O

Note : Both I/O6 and I/O2 toggle with OE or CE. See the text on I/O6 and I/O2 in the section "Write Operation Status" for more information.

Erase

Suspend

Erase

and I/O6 toggle with OE and CE

Erase Suspend

Read

Enter Erase

Suspend Program

Erase Suspend Program

Resume

Erase Suspend

Read

Erase

Timing Waveforms for Alternate

555 for program

2AA for erase

Addresses

Controlled Write Operation

PA for program SA for sector erase 555 for chip erase

Data Polling

Erase

Complete

Data

RESET

RY/BY

Note :

1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O

2. Figure indicates the last two bus cycles of the command sequence.

PRELIMINARY (July, 2005, Version 0.0) 30 AMIC Technology, Corp.

A0 for program 55 for erase

CPH

PD for program 30 for sector erase 10 for chip erase

BUSY

WHWH1 or 2

= Complement of Data Input, D

I/O

OUT

= Array Data.

Page 32

A29L400A Series

Erase and Programming Performance

Parameter Typ. (Note 1) Max. (Note 2) Un it Comments

Sector Erase Time 1.0 8 sec Chip Erase Time 10 sec Byte Programming Time 5 300 Word Programming Time 7 500

Chip Programming Time

(Note 3)

Byte Mode 7 18 sec

Word Mode 5 12 sec

µs µs

Excludes 00h programming prior to erasure

Excludes system-level overhead (Note 5)

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0V VCC, 10, 000 cycles. Addition ally, progr amming typically assumes checkerboard pattern.

2. Under worst case conditions of 90°C, VCC = 2.7V, 100,000 cycles.

3. The typical chip programming time is considerably less than the ma ximum chip programming time listed, since most bytes program faster than the maximum byte program time listed. If the maximum byte program time given is exc eeded, only then does the device set I/O

5 = 1. See the section on I/O5 for further information.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h befor e erasure.

5. System-level overhead is the time required to execute the four-bus-cycle comman d sequence for programming. See Table 5 for further information on command definitions.

6. The device has a guaranteed minimum erase and progra m cycle endurance of 10,000 cycles.

Latch-up Characteristics

Description Min. Max.

Input Voltage with respect to VSS on all I/O pins VCC Current Input voltage with respect to VSS on all pins except I/O pins

(including A9, OEand

RESET

)

Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at time.

TSOP and SOP Pin Capacitance

Parameter Symbol

CIN Input Capacitance

COUT

CIN2

Output Capacitance Control Pin Capacitance

Notes:

1. Sampled, not 100% tested.

2. Test conditions TA = 25°C, f = 1.0MHz

Parameter Description

Test Setup

Data Retention

Parameter

Test Conditions

IN=0

OUT=0

IN=0

-1.0V

-100 mA

-1.0V

Typ.

8.5

7.5

Min

Max.

7.5 12

VCC+1.0V

+100 mA

12.5V

Unit

pF pF pF

Unit

150°C

10 Years

Minimum Pattern Data Retention Time

125°C

20 Years

PRELIMINARY (July, 2005, Version 0.0) 31 AMIC Technology, Corp.

Page 33

A29L400A Series

Test Conditions

Test Specifications

Test Condition -70 -90 Unit

Output Load 1 TTL gate Output Load Capacitance, CL(including jig capacitance) 30 100 pF Input Rise and Fall Times 5 5 ns Input Pulse Levels 0.0 - 3.0 0.0 - 3.0 V Input timing measurement reference levels 1.5 1.5 V Output timing measurement reference levels 1.5 1.5 V

Test Setup

3.3 V

2.7 K

Ω

Device

Under

Test

6.2 K

Ω

Diodes = IN3064 or Equivalent

PRELIMINARY (July, 2005, Version 0.0) 32 AMIC Technology, Corp.

Page 34

A29L400A Series

Ordering Information Top Boot Sector Flash

Part No.

A29L400ATM-70 44Pin SOP A29L400ATM-70F 44Pin Pb-Free SOP A29L400ATM-70U 44Pin SOP A29L400ATM-70UF 44Pin Pb-Free SOP A29L400ATM-70I 44Pin SOP A29L400ATM-70IF 44Pin Pb-Free SOP A29L400ATV-70 48Pin TSOP A29L400ATV-70F 48Pin Pb-Free TSOP A29L400ATV-70U 48Pin TSOP A29L400ATV-70UF 48Pin Pb-Free TSOP A29L400ATV-70I 48Pin TSOP A29L400ATV-70IF 48Pin Pb-Free TSOP A29L400ATG-70 48-ball TFBGA A29L400ATG-70F 48-ball Pb-Free TFBGA A29L400ATG-70U 48-ball TFBGA A29L400ATG-70UF 48-ball Pb-Free TFBGA A29L400ATG-70I 48-ball TFBGA A29L400ATG-70IF A29L400ATM-90 44Pin SOP A29L400ATM-90F 44Pin Pb-Free SOP A29L400ATM-90U 44Pin SOP A29L400ATM-90UF 44Pin Pb-Free SOP A29L400ATM-90I 44Pin SOP A29L400ATM-90IF 44Pin Pb-Free SOP A29L400ATV-90 48Pin TSOP A29L400ATV-90F 48Pin Pb-Free TSOP A29L400ATV-90U 48Pin TSOP A29L400ATV-90UF 48Pin Pb-Free TSOP A29L400ATV-90I 48Pin TSOP A29L400ATV-90IF 48Pin Pb-Free TSOP A29L400ATG-90 48-ball TFBGA A29L400ATG-90F 48-ball Pb-Free TFBGA A29L400ATG-90U 48-ball TFBGA A29L400ATG-90UF 48-ball Pb-Free TFBGA A29L400ATG-90I 48-ball TFBGA A29L400ATG-90IF

Access Time

(ns)

70 4 20 0.2

90 4 20 0.2

Active Read

Current

Typ. (mA)

Program/Erase

Current

Typ. (mA)

Standby

Current

Typ. (µA)

Package

48-ball Pb-Free TFBGA

Note: -U is for industrial operating temperature range: -40°C to +85°C

-I is for industrial operating temperature range: -25°C to +85°C

PRELIMINARY (July, 2005, Version 0.0) 33 AMIC Technology, Corp.

Page 35

A29L400A Series

Ordering Information (continued) Bottom Boot Sector Flash

Part No.

A29L400AUM-70 44Pin SOP A29L400AUM-70F 44Pin Pb-Free SOP A29L400AUM-70U 44Pin SOP A29L400AUM-70UF 44Pin Pb-Free SOP A29L400AUM-70I 44Pin SOP A29L400AUM-70IF 44Pin Pb-Free SOP A29L400AUV-70 48Pin TSOP A29L400AUV-70F 48Pin Pb-Free TSOP A29L400AUV-70U 48Pin TSOP A29L400AUV-70UF 48Pin Pb-Free TSOP A29L400AUV-70I 48Pin TSOP A29L400AUV-70IF 48Pin Pb-Free TSOP A29L400AUG-70 48-ball TFBGA A29L400AUG-70F 48-ball Pb-Free TFBGA A29L400AUG-70U 48-ball TFBGA A29L400AUG-70UF 48-ball Pb-Free TFBGA A29L400AUG-70I 48-ball TFBGA A29L400AUG-70IF A29L400AUM-90 44Pin SOP A29L400AUM-90F 44Pin Pb-Free SOP A29L400AUM-90U 44Pin SOP A29L400AUM-90UF 44Pin Pb-Free SOP A29L400AUM-90I 44Pin SOP A29L400AUM-90IF 44Pin Pb-Free SOP A29L400AUV-90 48Pin TSOP A29L400AUV-90F 48Pin Pb-Free TSOP A29L400AUV-90U 48Pin TSOP A29L400AUV-90UF 48Pin Pb-Free TSOP A29L400AUV-90I 48Pin TSOP A29L400AUV-90IF 48Pin Pb-Free TSOP A29L400AUG-90 48-ball TFBGA A29L400AUG-90F 48-ball Pb-Free TFBGA A29L400AUG-90U 48-ball TFBGA A29L400AUG-90UF 48-ball Pb-Free TFBGA A29L400AUG-90I 48-ball TFBGA A29L400AUG-90IF

Access Time

(ns)

70 4 20 0.2

90 4 20 0.2

Active Read

Current

Typ. (mA)

Program/Erase

Current

Typ. (mA)

Standby

Current

Typ. (µA)

Package

48-ball Pb-Free TFBGA

Note: -U is for industrial operating temperature range: -40°C to +85°C

-I is for industrial operating temperature range: -25°C to +85°C

PRELIMINARY (July, 2005, Version 0.0) 34 AMIC Technology, Corp.

Page 36

A29L400A Series

Package Information SOP 44L Outline Dimensions

Seating Plane

unit: inches/mm

Gauge Plane

0.010"

Detail F

Symbol

Dimensions in inches Dimensions in mm

Min Nom Max Min Nom Max

A - - 0.118 - - 3.00 A1 0.004 - - 0.10 - A2 0.103 0.106 0.109 2.62 2.69 2.77

b 0.013 0.016 0.020 0.33 0.40 0.50

C 0.007 0.008 0.010 0.18 0.20 0.25

D - 1.122 1.130 - 28.50 28.70

E 0.490 0.496 0.500 12.45 12.60 12.70

- 0.050 - - 1.27 -

HE 0.620 0.631 0.643 15.75 16.03 16.33

L 0.024 0.032 0.040 0.61 0.80 1.02 L1 - 0.0675 - - 1.71 -

S - - 0.045 - - 1.14

y - - 0.004 - - 0.10

0°

See Detail F

8° 0°

8°

Notes:

1. The maximum value of dimension D includes end flash.

2. Dimension E d oes not include resin fins.

3. Dimension S includes end flash.

PRELIMINARY (July, 2005, Version 0.0) 35 AMIC Technology, Corp.

Page 37

A29L400A Series

Package Information TSOP 48L (Type I) Outline Dimensions

24 25

unit: inches/mm

Detail "A"

0.25 Detail "A"

Symbol

A - - 0.047 - - 1.20 A1 0.002 - 0.006 0.05 - 0.15 A2 0.037 0.039 0.042 0.94 1.00 1.06

b 0.007 0.009 0.011 0.18 0.22 0.27 c 0.004 - 0.008 0.12 - 0.20

D 0.779 0.787 0.795 19.80 20.00 20.20

D1 0.720 0.724 0.728 18.30 18.40 18.50

E - 0.472 0.476 - 12.00 12.10

e 0.020 BASIC 0.50 BASIC L 0.016 0.020 0.024 0.40 0.50 0.60

S 0.011 Typ. 0.28 Typ.

y - - 0.004 - - 0.10 θ

Dimensions in inches Dimensions in mm

Min Nom Max Min Nom Max

0° - 8° 0° - 8°

Notes:

1. The maximum value of dimension D includes end flash.

2. Dimension E does not include resin fins.

3. Dimension S includes end flash.

PRELIMINARY (July, 2005, Version 0.0) 36 AMIC Technology, Corp.

Page 38

A29L400A Series

Package Information 48LD CSP (6 x 8 mm) Outline Dimensions

(48TFBGA)

TOP VIEW

654321

H G

F E D C B A

Ball*A1 CORNER

SIDE VIEW

SEATING PLANE

0.10 C

Symbol

unit: mm

BOTTOM VIEW

123456

H G

F E D C B A

Dimensions in mm

Min.

Nom. Max.

A - - 1.20

A1 0.20 0.25 0.30

b 0.30 - 0.40

D 5.90 6.00 6.10

D1 4.00 BSC

e - 0.80 E 7.90 8.00 8.10

E1 5.60 BSC

PRELIMINARY (July, 2005, Version 0.0) 37 AMIC Technology, Corp.