Datasheet A29L320A Datasheet (AMIC)

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A29L320A Series

4M X 8 Bit / 2M X 16 Bit CMOS 3.0 Volt-only,

Boot Sector Flash Memory

Document Title 4M X 8 Bit / 2M X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory

Revision History

Rev. No.

History Issue Date Remark

0.0 Initial issue April 12, 2006 Preliminary

0.1 Error correction: Top/Bottom device ID code and pin configurations May 25, 2006

0.2 Change Table1 & Program/Erasure time July 3, 2006

1.0 Final version release January 5, 2007 Final

1.1 Modify symbol “L” outline dimensions in TSOP 48L package November 15, 2007

(November, 2007, Version 1.1)

AMIC Technology, Corp.

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A29L320A Series

4M X 8 Bit / 2M X 16 Bit CMOS 3.0 Volt-only,

Boot Sector Flash Memory

Features

 Single power supply operation

- Regulated voltage range: 2.7 to 3.6 volt read and write operations for compatibility with high performance 3 volt microprocessors

 Access times:

- 70/80/90/120 (max.)

 Current:

- 2mA active read current at 1MHz

- 10mA active read current at 5MHz

- 20 mA typical program/erase current

- 500 nA typical CMOS standby or Automatic Sleep Mode current

 Flexible sector architecture

- Eight 8 Kbyte sectors

- Sixty-three 64 kbyte sectors

- Any combination of sectors can be erased

- Supports full chip erase

- Sector protection:

 Unlock Bypass Program Command

- Reduces overall programming time when issuing multiple program command sequence

 Top or bottom boot block configurations available  Embedded Algorithms

- Embedded Erase algorithm will automatically erase the entire chip or any combination of designated sectors and verify the erased sectors

- Embedded Program algorithm automatically writes and verifies data at specified addresses

 Typical 100,000 program/erase cycles per sector  20-year data retention at 125°C

- Reliable operation for the life of the system

 CFI (Common Flash Interface) compliant

- Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices

 Compatible with JEDEC-standards

- Pinout and software compatible with single-power-supply Flash memory standard

- Superior inadvertent write protection



 Ready /

- Provides a hardware method of detecting completion of

 Erase Suspend/Erase Resume

 Hardware reset pin (



 Hardware/Software temporary sector block unprotect

 Hardware/Software sector protect/unprotect command  Package options

Polling and toggle bits

Data

- Provides a software method of detecting completion of program or erase operations

pin (RY / BY)

BUSY

program or erase operations

- Suspends a sector erase operation to read data from, or

program data to, a non-erasing sector, then resumes the erase operation

RESET

- Hardware method to reset the device to reading array data

/ACC input pin

- Write protect (

outermost boot sectors, regardless of sector protect status

- Acceleration (ACC) function provides accelerated

program times command allows code changes in previously locked

sectors

- 48-pin TSOP (I) or 48-ball TFBGA

- All Pb-free (Lead-free) products are RoHS compliant

)

) function allows protection of two

General Description

The A29L320A is a 32Mbit, 3.3 volt-only Flash memory organized as 2,097,152 words of 16 bits or 4,194,304 bytes of 8 bits each. The 8 bits of data appear on I/O0 - I/O7; the 16 bits of data appear on I/O 48-ball TFBGA and 48-Pin TSOP packages. This device is designed to be programmed in-system with the standard system 3.3 volt VCC supply. Additional 12.0 volt VPP is not required for in-system write or erase operations. However, the A29L320A can also be programmed in standard EPROM programmers. The A29L320A has the first toggle bit, I/O whether an Embedded Program or Erase is in progress, or it is in the Erase Suspend. Besides the I/O A29L320A has a second toggle bit, I/O the addressed sector is being selected for erase. The A29L320A also offers the ability to program in the Erase

(November, 2007, Version 1.1) 1

0~I/O15. The A29L320A is offered in

6, which indicates

6 toggle bit, the

2, to indicate whether

Suspend mode. The standard A29L320A offers access times of 70,80,90 and 120ns, allowing high-speed microprocesso rs to operate without wait states. To eliminate bus contention

the device has separate chip enable ( (

) and output enable (OE) controls.

The device requires only a single 3.3 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The A29L320A is entirely software command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and

), write enable

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A29L320A Series

erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by writing the proper program command sequence. This initiates the Embedded Program algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper program margin. Device erasure occurs by executing the proper erase command sequence. This initiates the Embedded Erase algorithm - an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper erase margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four.

The host system can detect whether a program or erase operation is complete by observing the RY / reading the I/O

7 (

Polling) and I/O6 (toggle) status bits.

Data

pin, or by

After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data

Pin Configurations



TSOP (I)

contents of other sectors. The A29L320A is fully erased when shipped from the factory. The hardware sector protection feature disables operations for both program and erase in any combination of the sectors of memory. This can be achieved via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any other sector that is not selected for erasure. True background erase can thus be achieved.

The hardware

RESET

pin terminates any operation in progress and resets the internal state machine to reading array data. The

RESET

pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up

firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.

A14 A13 A12 A11 A10

A19 A20

RESET

WP/ACC

RY/BY

A18 A17

1 2 3 4 5 6 7

9 10 11 12 13 14 15 16 17

24 25

A29L320AV

A16A15

BYTE

VSS I/O 15(A-1)

I/O7

I/O14

I/O6

I/O13

I/O5

I/O12

I/O

VCC

I/O 11

I/O3

I/O 10

34 33 I/O 32 I/O9 31

I/O1

I/O8

I/O0

VSS

(November, 2007, Version 1.1) 2 AMIC Technology, Corp.

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A29L320A Series

Pin Configurations (continued)



TFBGA

Top View, Balls Facing Down

A6 B6 C6 D6 E6 F6

A13 A12 A14 A15 A16 BYTE I/O15(A-1) VSS

A5 B5 C5 D5 E5 F5

A9 A8 A10 A11 I/O

A4 B4 C4 D4 E4 F4

7 I/O14 I/O13 I/O6

WE RESET NC A19 I/O5 I/O12 VCC I/O4

A3 B3 C3 D3 E3 F3

RY/BY A18 A20 I/O2 I/O10 I/O11 I/O3

WP/ACC

A2 B2 C2 D2 E2 F2

A7 A17 A6 A5 I/O0 I/O8 I/O9 I/O1

A1 B1 C1 D1 E1 F1

A3 A4 A2 A1 A0

CE OE

VSS

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A29L320A Series

Block Diagram

VCC

VSS

RESET

BYTE

WP/ACC

CE OE

A0-A20

RY/BY

State

Control

Command

VCC Detector

PGM Voltage

Generator

Timer

Sector Switches

Erase Voltage

Generator

STB

Chip Enable

Output Enable

Logic

Y-Decoder

X-decoder

Address Latch

STB

0 - I/O15 (A-1)

I/O

Input/Output

Buffers

Data Latch

Y-Gating

Cell Matrix

Pin Descriptions

A0 – A20 Address Inputs

I/O0 - I/O14 Data Inputs/Outputs

I/O15 (A-1)

RESET

Pin No. Description

I/O15 Data Input/Output, Word Mode

A-1 LSB Address Input, Byte Mode

BYTE

RY/BY

Chip Enable Write Enable Output Enable Hardware Reset Selects Byte Mode or Word Mode

Ready/

BUSY

- Output

VSS Ground VCC Power Supply

NC Pin not connected internally

/ACC

Hardware Write Protect / Acceleration Pin

(November, 2007, Version 1.1) 4 AMIC Technology, Corp.

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A29L320A Series

Absolute Maximum Ratings*

Storage Temperature Plastic Packages. . . -65°C to + 150°C Ambient Temperature with Power Applied. -55°C to + 125°C Voltage with Respect to Ground

VCC (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.0V

A9,

All other pins (Note 1) . . . . . . . . . . . . . . -0.5V to VCC + 0.5V

Output Short Circuit Current (Note 3) . . . . . . . . . . . . . 200mA

RESET

/ACC . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +10.5V

(Note 2) . . . . . . . . . . . . . -0.5V to +10.5V

Notes:

1. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, input or I/O pins may undershoot VSS to -2.0V for periods of up to 20ns. Maximum DC voltage on input and I/O pins is VCC +0.5V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0V for periods up to 20ns.

2. Minimum DC input voltage on A9,

0.5V. During voltage transitions, A9, may overshoot VSS to -2.0V for periods of up to 20ns. Maximum DC input voltage on A9 is +10.5V which may

overshoot to 14.0V for periods up to 20ns.

3. No more than one output is shorted at a time. Duration of the short circuit should not be greater than one second.

and

RESET

and

is -

RESET

Device Bus Operations

This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the

*Comments

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of these specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.

Operating Ranges

Commercial (C) Devices

Ambient Temperature (T

Extended Range Devices

Ambient Temperature (TA)

For –U series . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C

For –I series . . . . . . . . . . . . . . . . . . . . . . . . . -25°C to +85°C

VCC Supply Voltages

VCC for all devices . . . . . . . . . . . . . . . . . . . . +2.7V to +3.6V

Operating ranges define those limits between which the functionally of the device is guaranteed.

command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The appropriate device bus operations table lists the inputs and control levels required, and the resulting output. The following subsections describe each of these operations in further detail.

A) . . . . . . . . . . . . . . . . 0°C to +70°C

Table 1. A29L320A Device Bus Operations

Read L L H H L/H AIN DOUT DOUT Write L H L H (Note 3) AIN (Note 4) (Note 4) Accelerated

Program Standby

Output Disable L H H H L/H X High-Z High-Z High-Z Reset

Sector Protect (Note 2) Sector Unprotect (Note 2) Temporary Sector Unprotect

Legend: L = Logic Low = V

Notes:

1. Addresses are A20:A0 in word mode (

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See “Sector/Sector Block Protection and Unprotection”.

3. If

/ACC=VIL, the two outermost boot sectors remain protected. If

L H L H V

VCC ±

0.3 V

X X X L L H L V

L H L V

X X X V

IL, H = Logic High = VIH, VID = 8.5V-10.5V, VHH = 8.5V-10.5V, X = Don't Care, DIN = Data In, DOUT = Data Out, AIN = Address In

X X

RESET

VCC ±

0.3 V

ID L/H

ID L/H AIN (Note 4) (Note 4) High-Z

=VIH), A20: A

BYT

ACC

HH AIN (Note 4) (Note 4) High-Z

H X High-Z High-Z High-Z

L/H X L/H

A0 - A20

(Note 1)

Sector Address,

A6=L, A1=H, A0=L

Sector Address,

A6=H, A1=H, A0=L

in byte mode (

-1

I/O0 - I/O7

BYTE

High-Z High-Z

(Note 4) X X

=VIL).

BYTE

/ACC=VIH, the two outermost boot sector

I/O8 - I/O15 Operation

=VIH

BYTE

8~I/O14=High-Z

I/O

I/O15=A-1

High-Z

=VIL

protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection. If

IN or DOUT as required by command sequence, data polling, or sector protection algorithm.

4. D

/ACC = VHH, all sectors are unprotected.

(November, 2007, Version 1.1) 5 AMIC Technology, Corp.

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A29L320A Series

Word/Byte Configuration

The operate in the byte or word configuration. If the

set at logic ”1”, the device is in word configuration, I/O are active and controlled by

If the configuration, and only I/O

and OE. I/O8-I/O14 are tri-stated, and I/O15 pin is used

as an input for the LSB(A-1) address function.

pin determines whether the I/O pins I/O15-I/O0

BYTE

and OE.

pin is set at logic “0”, the device is in byte

BYTE

0-I/O7 are active and controlled by

BYTE

pin is

15-I/O0

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the selects the device.

data to the output pins. during read operation. The

and OE pins to VIL. CE is the power control and

is the output control and gates array

should remain at VIH all the time

pin determines whether

BYTE

the device outputs array data in words and bytes. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See "Reading Array Data" for more information. Refer to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for the timing waveforms,

CC1 in the DC Characteristics table represents the active

l current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which include s programming data to the device and erasing sectors of

memory), the system must drive

to VIH. For program operations, the

determines whether the device accepts program data in bytes or words, Refer to “Word/Byte Configuration” for more information. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “ Word / Byte Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequence. An erase operation can erase one sector, multiple sectors, or the entire device. The Sector Address Tables indicate the address range that each sector occupies. A "sector address" consists of the address inputs required to uniquely select a sector. See the "Command Definitions" section for details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on I/O read cycle timings apply in this mode. Refer to the "Autoselect Mode" and "Autoselect Command Sequence" sections for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC

and CE to VIL, and

BYTE

7 - I/O0. Standard

Characteristics" section contains timing specification tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may check the status of the operation by reading the status bits on I/O7 - I/O0. Standard read cycle timings and ICC read specifications apply. Refer to "Write Operation Status" for more information, and to each AC Characteristics section for timing diagrams.

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are

placed in the high impedance state, independent of the

input. The device enters the CMOS standby mode when the

RESET

more restricted voltage range than V are held at V

pins are both held at VCC ± 0.3V. (Note that this is a

IH.) If

IH, but not within VCC ± 0.3V, the device will be

and

RESET

in the standby mode, but the standby current will be greater. The device requires the standard access time (tCE) before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. I

CC3 and ICC4 in the DC Characteristics tables represent the

standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC +30ns. T he automatic

sleep mode is independent of the

,WEand OE control

signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. I

CC4 in the

DC Characteristics table represents the automatic sleep mode current specification.

Output Disable Mode

When the OE input is at VIH, output from the device is disabled. The output pins are placed in the high im pedance

state.

RESET

The the device to reading array data. When the system drives the

RESET

immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for

the duration of the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is

ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the When CMOS standby current (I

within VSS ± 0.3V, the standby current will be greater.

: Hardware Reset Pin

RESET

pin provides a hardware method of resetting

pin low for at least a period of tRP, the device

pulse. The device also resets the

pulse.

CC4 ). If

RESET

is held at VIL but not

RESET

is held at VSS ± 0.3V, the device draws

(November, 2007, Version 1.1) 6 AMIC Technology, Corp.

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A29L320A Series

The

RESET

system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If

RESET

the RY/ operation is complete, which requires a time tREADY (during Embedded Algorithms). The system can thus monitor

pin may be tied to the system reset circuitry. A

is asserted during a program or erase operation,

pin remains a “0” (busy) until the internal reset

RY/ complete. If operation is not executing (RY/ operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the Refer to the AC Characteristics tables for parameters and diagram.

to determine whether the reset operation is

is asserted when a program or erase

pin is “1”), the reset

RESET

pin return to VIH.

Table 2. A29L320A Top Boot Block Sector Address Table

Sector A20-A12

SA0 000000XXX 64/32 000000 - 00FFFF 000000 - 007FFF SA1 000001XXX 64/32 010000 - 01FFFF 008000 - 00FFFF SA2 000010XXX 64/32 020000 - 02FFFF 010000 - 017FFF SA3 000011XXX 64/32 030000 - 03FFFF 018000 - 01FFFF SA4 000100XXX 64/32 040000 - 04FFFF 020000 - 027FFF SA5 000101XXX 64/32 050000 - 05FFFF 028000 - 02FFFF SA6 000110XXX 64/32 060000 - 06FFFF 030000 - 037FFF SA7 000111XXX 64/32 070000 - 07FFFF 038000 - 03FFFF SA8 001000XXX 64/32 080000 - 08FFFF 040000 - 047FFF

SA9 001001XXX 64/32 090000 - 09FFFF 048000 - 04FFFF SA10 001010XXX 64/32 0A0000 - 0AFFFF 050000 - 057FFF SA11 001011XXX 64/32 0B0000 - 0BFFFF 058000 - 05FFFF SA12 001100XXX 64/32 0C0000 - 0CFFFF 060000 - 067FFF SA13 001101XXX 64/32 0D0000 - 0DFFFF 068000 - 06FFFF SA14 001110XXX 64/32 0E0000 - 0EFFFF 070000 - 077FFF SA15 001111XXX 64/32 0F0000 - 0FFFFF 078000 - 07FFFF SA16 010000XXX 64/32 100000 - 10FFFF 080000 - 087FFF SA17 010001XXX 64/32 110000 - 11FFFF 088000 - 08FFFF SA18 010010XXX 64/32 120000 - 12FFFF 090000 - 097FFF SA19 010011XXX 64/32 130000 - 13FFFF 098000 - 09FFFF SA20 010100XXX 64/32 140000 - 14FFFF 0A0000 - 0A7FFF SA21 010101XXX 64/32 150000 - 15FFFF 0A8000 - 0AFFFF SA22 010110XXX 64/32 160000 - 16FFFF 0B0000 - 0B7FFF SA23 010111XXX 64/32 170000 - 17FFFF 0B8000 - 0BFFFF SA24 011000XXX 64/32 180000 - 18FFFF 0C0000 - 0C7FFF SA25 011001XXX 64/32 190000 - 19FFFF 0C8000 - 0CFFFF SA26 011010XXX 64/32 1A0000 - 1AFFFF 0D0000 - 0D7FFF SA27 011011XXX 64/32 1B0000 - 1BFFFF 0D8000 - 0DFFFF SA28 011100XXX 64/32 1C0000 - 1CFFFF 0E0000 - 0E7FFF SA29 011101XXX 64/32 1D0000 - 1DFFFF 0E8000 - 0EFFFF SA30 011110XXX 64/32 1E0000 - 1EFFFF 0F0000 - 0F7FFF SA31 011111XXX 64/32 1F0000 - 1FFFFF 0F8000 - 0FBFFF SA32 100000XXX 64/32 200000 - 20FFFF 100000 - 107FFF SA33 100001XXX 64/32 210000 - 21FFFF 108000 - 10FFFF SA34 100010XXX 64/32 220000 - 22FFFF 110000 - 17FFFF

Sector Size

(Kbytes/ Kwords)

Address Range (in hexadecimal)

Byte Mode (x8) Word Mode (x16)

RESET

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A29L320A Series

Table 2. A29L320A Top Boot Block Sector Address Table

Sector A20-A12

Sector Size

(Kbytes/ Kwords)

Address Range (in hexadecimal)

Byte Mode (x8) Word Mode (x16)

SA35 100011XXX 64/32 230000 - 23FFFF 118000 - 11FFFF SA36 100100XXX 64/32 240000 - 24FFFF 120000 - 127FFF SA37 100101XXX 64/32 250000 - 25FFFF 128000 - 12FFFF SA38 100110XXX 64/32 260000 - 26FFFF 130000 - 137FFF SA39 100111XXX 64/32 270000 - 27FFFF 138000 - 13FFFF SA40 101000XXX 64/32 280000 - 28FFFF 140000 - 147FFF SA41 101001XXX 64/32 290000 - 29FFFF 148000 - 14FFFF SA42 101010XXX 64/32 2A0000 - 2AFFFF 150000 - 157FFF SA43 101011XXX 64/32 2B0000 - 2BFFFF 158000 - 15FFFF SA44 101100XXX 64/32 2C0000 - 2CFFFF 160000 - 167FFF SA45 101101XXX 64/32 2D0000 - 2DFFFF 168000 - 16FFFF SA46 101110XXX 64/32 2E0000 - 2EFFFF 170000 - 177FFF SA47 101111XXX 64/32 2F0000 - 2FFFFF 178000 - 17FFFF SA48 110000XXX 64/32 300000 - 30FFFF 180000 - 187FFF SA49 110001XXX 64/32 310000 - 31FFFF 188000 - 18FFFF SA50 110010XXX 64/32 320000 - 32FFFF 190000 - 197FFF SA51 110011XXX 64/32 330000 - 33FFFF 198000 - 19FFFF SA52 110100XXX 64/32 340000 - 34FFFF 1A0000 - 1A7FFF SA53 110101XXX 64/32 350000 - 35FFFF 1A8000 - 1AFFFF SA54 110110XXX 64/32 360000 - 36FFFF 1B0000 - 1B7FFF SA55 110111XXX 64/32 370000 - 37FFFF 1B8000 - 1BFFFF SA56 111000XXX 64/32 380000 - 38FFFF 1C0000 - 1C7FFF SA57 111001XXX 64/32 390000 - 39FFFF 1C8000 - 1CFFFF SA58 111010XXX 64/32 3A0000 - 3AFFFF 1D0000 - 1D7FFF SA59 111011XXX 64/32 3B0000 - 3BFFFF 1D8000 - 1DFFFF SA60 111100XXX 64/32 3C0000 - 3CFFFF 1E0000 - 1E7FFF SA61 111101XXX 64/32 3D0000 - 3DFFFF 1E8000 - 1EFFFF SA62 111110XXX 64/32 3E0000 - 3EFFFF 1F0000 - 1F7FFF SA63 111111000 8/4 3F0000 - 3FFFFF 1F8000 - 1F8FFF SA64 111111001 8/4 3F2000 - 3F3FFF 1F9000 - 1F9FFF SA65 111111010 8/4 3F4000 - 3F5FFF 1FA000 - 1FAFFF SA66 111111011 8/4 3F6000 - 3F7FFF 1FB000 - 1FBFFF SA67 111111100 8/4 3F8000 - 3F9FFF 1FC000 - 1FCFFF SA68 111111101 8/4 3FA000 - 3FBFFF 1FD000 - 1FDFFF SA69 111111110 8/4 3FC000 - 3FDFFF 1FE000 - 1FEFFF SA70 111111111 8/4 3FE000 - 3FFFFF 1FF000 - 1FFFFF

Note: Address range is A20 : A

in byte mode and A20 : A0 in word mode. See “Word/Byte Configuration” section.

-1

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A29L320A Series

Table 3. A29L320A Bottom Boot Block Sector Address Table

Address Range (in hexadecimal) Sector A20 -A12 Sector Size

(Kbytes/ Kwords)

SA0 000000000 8/4 000000 - 001FFF 000000 - 000FFF SA1 000000001 8/4 002000 - 003FFF 001000 - 001FFF SA2 000000010 8/4 004000 - 005FFF 002000 - 002FFF SA3 000000011 8/4 006000 - 007FFF 003000 - 003FFF SA4 000000100 8/4 008000 - 009FFF 004000 - 004FFF SA5 000000101 8/4 00A000 - 00BFFF 005000 - 005FFF SA6 000000110 8/4 00C000 - 00DFFF 006000 - 006FFF SA7 000000111 8/4 00E000 - 00FFFF 007000 - 007FFF SA8 000001XXX 64/32 010000 - 01FFFF 008000 - 00FFFF

SA9 000010XXX 64/32 020000 - 02FFFF 010000 - 017FFF SA10 000011XXX 64/32 030000 - 03FFFF 018000 - 01FFFF SA11 000100XXX 64/32 040000 - 04FFFF 020000 - 027FFF SA12 000101XXX 64/32 050000 - 05FFFF 028000 - 02FFFF SA13 000110XXX 64/32 060000 - 06FFFF 030000 - 037FFF SA14 000111XXX 64/32 070000 - 07FFFF 038000 - 03FFFF SA15 001000XXX 64/32 080000 - 08FFFF 040000 - 047FFF SA16 001001XXX 64/32 090000 - 09FFFF 048000 - 04FFFF SA17 001010XXX 64/32 0A0000 - 0AFFFF 050000 - 057FFF SA18 001011XXX 64/32 0B0000 - 0BFFFF 058000 - 05FFFF SA19 001100XXX 64/32 0C0000 - 0CFFFF 060000 - 067FFF SA20 001101XXX 64/32 0D0000 - 0DFFFF 068000 - 06FFFF SA21 001110XXX 64/32 0E0000 - 0EFFFF 070000 - 077FFF SA22 001111XXX 64/32 0F0000 - 0FFFFF 078000 - 07FFFF SA23 010000XXX 64/32 100000 - 10FFFF 080000 - 087FFF SA24 010001XXX 64/32 110000 - 11FFFF 088000 - 07FFFF SA25 010010XXX 64/32 120000 - 12FFFF 090000 - 097FFF SA26 010011XXX 64/32 130000 - 13FFFF 098000 - 09FFFF SA27 010100XXX 64/32 140000 - 14FFFF 0A0000 - 0A7FFF SA28 1010101XXX 64/32 140000 - 14FFFF 0A8000 - 0AFFFF SA29 010110XXX 64/32 160000 - 16FFFF 0B0000 - 0B7FFF SA30 010111XXX 64/32 170000 - 17FFFF 0B8000 - 0BFFFF SA31 011000XXX 64/32 180000 - 18FFFF 0C0000 - 0C7FFF SA32 011001XXX 64/32 190000 - 19FFFF 0C8000 - 0CFFFF SA33 011010XXX 64/32 1A0000 - 1AFFFF 0D0000 - 0D7FFF SA34 011011XXX 64/32 1B0000 - 1BFFFF 0D8000 - 0DFFFF

Byte Mode (x8) Word Mode (x16)

(November, 2007, Version 1.1) 9 AMIC Technology, Corp.

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A29L320A Series

Table 3. A29L320A Bottom Boot Block Sector Address Table

Sector A20 -A12 Sector Size

(Kbytes/ Kwords)

Address Range (in hexadecimal)

Byte Mode (x8) Word Mode (x16)

SA35 011100XXX 64/32 1C0000 - 1CFFFF 0E0000 - 0E7FFF SA36 011101XXX 64/32 1D0000 - 1DFFFF 0E8000 - 0EFFFF SA37 011110XXX 64/32 1E0000 - 1EFFFF 0F0000 - 0F7FFF SA38 011111XXX 64/32 1F0000 - 1FFFFF 0F8000 - 0FFFFF SA39 100000XXX 64/32 200000 - 20FFFF 100000 - 107FFF SA40 100001XXX 64/32 210000 - 21FFFF 108000 - 10FFFF SA41 100010XXX 64/32 220000 - 22FFFF 110000 - 117FFF SA42 100011XXX 64/32 230000 - 23FFFF 118000 - 11FFFF SA43 100100XXX 64/32 240000 - 24FFFF 120000 - 127FFF SA44 100101XXX 64/32 250000 - 25FFFF 128000 - 12FFFF SA45 100110XXX 64/32 260000 - 26FFFF 130000 - 137FFF SA46 100111XXX 64/32 270000 - 27FFFF 138000 - 13FFFF SA47 101000XXX 64/32 280000 - 28FFFF 140000 - 147FFF SA48 101001XXX 64/32 290000 - 29FFFF 148000 - 14FFFF SA49 101010XXX 64/32 2A0000 - 2AFFFF 150000 - 157FFF SA50 101011XXX 64/32 2B0000 - 2BFFFF 158000 - 15FFFF SA51 101100XXX 64/32 2C0000 - 2CFFFF 160000 - 167FFF SA52 101101XXX 64/32 2D0000 - 2DFFFF 168000 - 16FFFF SA53 101110XXX 64/32 2E0000 - 2EFFFF 170000 - 177FFF SA54 101111XXX 64/32 2F0000 - 2FFFFF 178000 - 17FFFF SA55 110000XXX 64/32 300000 - 30FFFF 180000 - 187FFF SA56 110001XXX 64/32 310000 - 31FFFF 188000 - 18FFFF SA57 110010XXX 64/32 320000 - 32FFFF 190000 - 197FFF SA58 110011XXX 64/32 330000 - 33FFFF 198000 - 19FFFF SA59 110100XXX 64/32 340000 - 34FFFF 1A0000 - 1A7FFF SA60 110101XXX 64/32 350000 - 35FFFF 1A8000 - 1AFFFF SA61 110110XXX 64/32 360000 - 36FFFF 1B0000 - 1B7FFF SA62 110111XXX 64/32 370000 - 37FFFF 1B8000 - 1BFFFF SA63 111000XXX 64/32 380000 - 38FFFF 1C0000 - 1C7FFF SA64 111001XXX 64/32 390000 - 39FFFF 1C8000 - 1CFFFF SA65 111010XXX 64/32 3A0000 - 3AFFFF 1D0000 - 1D7FFF SA66 111011XXX 64/32 3B0000 - 3BFFFF 1D8000 - 1DFFFF SA67 111100XXX 64/32 3C0000 - 3CFFFF 1E0000 - 1E7FFF SA68 111101XXX 64/32 3D0000 - 3DFFFF 1E8000 - 1EFFFF SA69 111110XXX 64/32 3E0000 - 3EFFFF 1F0000 - 1F7FFF SA70 111111XXX 64/32 3F0000 - 3FFFFF 1F8000 - 1FFFFF

Note: Address range is A20 : A

in byte mode and A20 : A0 in word mode. See “Word/Byte Configuration” section.

-1

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A29L320A Series

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on I/O7 - I/O0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID (8.5V to 10.5V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes (High Voltage Method) table. In addition, when verifying sector

protection, the sector address must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows the remaining address bits that are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on I/O

7 - I/O0.To access the

autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require VID. See "Command Definitions" for details on using the autoselect mode.

Table 4. A29L320A Autoselect Codes (High Voltage Method)

Description

Mode

I/O

A20

A11

A12

A9 A8

A10

A6 A5

A1 A0 I/O

Manufacturer ID: AMIC L L H X X VID X L X L L X 37h Device ID:

A29L320A (Top Boot Block)

Word

Byte

L L H X X V

ID XLXLH

22h F6h

X F6h

I/O

Device ID: A29L320A (Bottom Boot Block)

Word

Byte

22h F9h

L L H X X VID XLXLH

X F9h

Continuation ID L L H X X VID X L X H H X 7Fh

Sector Protection Verification L L H SA X VID XLXHL

01h

(protected)

00h

(unprotected)

L=Logic Low= VIL, H=Logic High=VIH, SA=Sector Address, X=Don’t Care. Note: The autoselect codes may also be accessed in-system via command sequences.

(November, 2007, Version 1.1) 11 AMIC Technology, Corp.

Page 13

A29L320A Series

Sector/Sector Block Protection and Unprotection

(Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of

two or more adjacent sectors that are protected or unprotected at the same time (see Tables 5 and 6).

Table 5. Top Boot Sector/Sector Block Addresses for Protection/Unprotection

Sector /

Sector Block

SA0 000000XXX 64 Kbytes

SA1-SA3

SA4-SA7 0001XXXXX 256 (4x64) Kbytes

SA8-SA11 0010XXXXX 256 (4x64) Kbytes SA12-SA15 0011XXXXX 256 (4x64) Kbytes SA16-SA19 0100XXXXX 256 (4x64) Kbytes SA20-SA23 0101XXXXX 256 (4x64) Kbytes SA24-SA27 0110XXXXX 256 (4x64) Kbytes

SA28-SA31 0111XXXXX 256 (4x64) Kbytes

SA32-SA35 1000XXXXX 256 (4x64) Kbytes SA36-SA39 1001XXXXX 256 (4x64) Kbytes SA40-SA43 1010XXXXX 256 (4x64) Kbytes SA44-SA47 1011XXXXX 256 (4x64) Kbytes SA48-SA51 1100XXXXX 256 (4x64) Kbytes SA52-SA55 1101XXXXX 256 (4x64) Kbytes SA56-SA59 1110XXXXX 256 (4x64) Kbytes

SA60-SA62

SA63 111111000 8 Kbytes SA64 111111001 8 Kbytes SA65 111111010 8 Kbytes SA66 111111011 8 Kbytes SA67 111111100 8 Kbytes SA68 111111101 8 Kbytes SA69 111111110 8 Kbytes SA70 111111111 8 Kbytes

A20–A12 Sector / Sector Block Size

000001XXX 000010XXX 000011XXX

111100XXX 111101XXX 111110XXX

192 (3x64) Kbytes

Table 6. Bottom Boot Sector/Sector Block Addresses for Protection/Unprotection

Sector /

Sector Block

SA70 111111XXX 64 Kbytes

SA69- SA67

SA66- SA63 1110XXXXX 256 (4x64) Kbytes SA62- SA59 1101XXXXX 256 (4x64) Kbytes SA58- SA55 1100XXXXX 256 (4x64) Kbytes SA54- SA51 1011XXXXX 256 (4x64) Kbytes

SA50- SA47 1010XXXXX 256 (4x64) Kbytes

SA46-SA43 1001XXXXX 256 (4x64) Kbytes SA42-SA39 1000XXXXX 256 (4x64) Kbytes SA38-SA35 0111XXXXX 256 (4x64) Kbytes SA34-SA31 0110XXXXX 256 (4x64) Kbytes SA30-SA27 0101XXXXX 256 (4x64) Kbytes SA26-SA23 0100XXXXX 256 (4x64) Kbytes SA22-SA19 0011XXXXX 256 (4x64) Kbytes SA18-SA15 0010XXXXX 256 (4x64) Kbytes SA14-SA11 0001XXXXX 256 (4x64) Kbytes

SA10-SA8

SA7 000000111 8 Kbytes SA6 000000110 8 Kbytes SA5 000000101 8 Kbytes SA4 000000100 8 Kbytes SA3 000000011 8 Kbytes SA2 000000010 8 Kbytes SA1 000000001 8 Kbytes SA0 000000000 8 Kbytes

A20–A12 Sector / Sector Block Size

111110XXX 111101XXX 111100XXX

000001XXX 000010XXX 000011XXX

192 (3x64) Kbytes

(November, 2007, Version 1.1) 12 AMIC Technology, Corp.

Page 14

A29L320A Series

Sector Protection/Unprotection

The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. It is possible to determine whether a sector is protected or unprotected. See “Autoselect Mode” for details. Sector protection / unprotection can be implemented via two methods. The primary method requires VID on the

RESET

via programming equipment. Figure 2 shows the algorithm and the Sector Protect / Unprotect Timing Diagram illustrates the timing waveforms for this feature. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. The alternate method for protection and unprotection is by software sector block protect/unprotect command. See Figure 2 for Command Flow. The device is shipped with all sectors unprotected. It is possible to determine whether a sector is protected or unprotected. See "Autoselect Mode" for details.

pin only, and can be implemented either in-system or

Hardware Data Protection

The requirement of command unlocking sequence for programming or erasing provides data protection against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up transitions, or from system noise. The device is powered up to read array data to avoid accidentally writing data to the array.

Write Pulse "Glitch" Protection

Noise pulses of less than 5ns (typical) on OE, CE or WE do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE=VIL,

= VIH or WE = VIH. To initiate a write cycle, CE and

must be a logical zero while OE is a logical one.

Power-Up Write Inhibit

= CE = VIL and OE = VIH during power up, the

device does not accept commands on the rising edge of

. The internal state machine is automatically reset to

reading array data on the initial power-up.

Temporary Sector Unprotect

This feature allows temporary unprotection of previous protected sectors to change data in-system. The Sector

Unprotect mode is activated by setting the During this mode, formerly protected sectors can be

programmed or erased by selecting the sector addresses. Once VID is removed from the protected sectors are protected again. Figure 1 shows the

algorithm, and the Temporary Sector Unprotect diagram shows the timing waveforms, for this feature.

RESET

pin, all the previously

pin to VID.

(November, 2007, Version 1.1) 13 AMIC Technology, Corp.

Page 15

A29L320A Series

START

RESET = VID

(Note 1)

Perform Erase or

Program Operations

RESET = VIH

Temporary Sector

Unprotect

Completed (Note 2)

Notes:

1. All protected sectors unprotected (If WP/ACC=V outermost boot sectors will remain protected).

2. All previously protect ed sectors are protected once again.

IL,

START

555/AA + 2AA/55 + 555/77

(Note 1)

Perform Erase or

Program Operations

XXX/F0

(Reset Command)

Soft-ware Temporary

Sector Unprotect

Completed

(Note 2)

Notes:

1. All protected sectors unprotected (If WP/ACC=V outermost boot sectors will remain protected).

2. All previously protected sectors are protected once again.

IL,

Figure 1-2. Temporary Sector Unprotect Operation by Software Mode

Figure 1-1. Temporary Sector Unprotect Operation by RESET Mode

(November, 2007, Version 1.1) 14 AMIC Technology, Corp.

Page 16

A29L320A Series

Temporary Sector

Unprotect Mode

Increment

PLSCNT

START

PLSCNT=1

RESET=VID

Wait 1 us

First Write

Cycle=60h?

Set up sector

address

Sector Protec:

Write 60h to sector

address with A6=0,

A1=1, A0=0

Wait 150 us

Verify Sector

Protect: Write 40h

to sector address with A6=0, A1=1,

A0=0

Read from

sector address

with A6=0,

A1=1, A0=0

Yes

Reset

PLSCNT=1

Protect all sectors:

The indicated portion of

the sector protect algorithm must be

performed for all

unprotected sectors prior

to issuing the first sector

unprotect address

Increment

PLSCNT

START

PLSCNT=1

RESET=VID

Wait 1 us

First Write

Cycle=60h?

All sectors protected?

Set up first sector

address

Sector Unprotect: Write 60h to sector address with A6=1,

A1=1, A0=0

Wait 15 ms

Verify Sector

Unprotect : Write

40h to sector

address with A6=1,

A1=1, A0=0

Yes

Temporary Sector

Unprotect Mode

PLSCNT

=25?

Yes

Device failed

Sector Protect

Algorithm

Data=01h?

Yes

Protect another

sector?

Remove VID

from RESET

Write reset

command

Sector Protect

complete

Yes

PLSCNT=

1000?

Yes

Device failed

Sector Unprotect

Algorithm

Figure 2-1. In-System Sector Protect/Unprotect

Algorithms

Read from sector address with A6=1,

A1=1, A0=0

Data=00h?

Yes

Last sector

verified?

Yes

Remove VID from RESET

Write reset Command

Sector Unprotect

complete

Set up

next sector

address

(November, 2007, Version 1.1) 15 AMIC Technology, Corp.

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A29L320A Series

Temporary Sector

Unprotect Mode

Increment

PLSCNT

START

PLSCNT=1

555/AA + 2AA/55 +

555/77

Wait 1 us

First Write

Cycle=60h?

Set up sector

address

Sector Protect:

Write 60h to sector

address with A6=0,

A1=1, A0=0

Wait 150 us

Verify Sector

Protect: Write 40h

to sector address with A6=0, A1=1,

A0=0

Read from

sector address

with A6=0,

A1=1, A0=0

Yes

Reset

PLSCNT=1

Protect all sectors:

The indicated portion of

the sector protect

algorithm must be

performed for all unprotected sectors prior to issuing the first sector

unprotect address

Increment

PLSCNT

START

PLSCNT=1

555/AA + 2AA/55 +

555/77

Wait 1 us

First Write

Cycle=60h?

All sectors protected?

Set up first sector

address

Sector Unprotect: Write 60h to sector address with A6=1,

A1=1, A0=0

Wait 15 ms

Verify Sector

Unprotect : Write

40h to sector

address with A6=1,

A1=1, A0=0

Yes

Temporary Sector

Unprotect Mode

PLSCNT

=25?

Yes

Device failed

Sector Protect

Algorithm

Data=01h?**

Yes

Protect another

sector?

Write reset

command

Sector Protect

complete

Yes

Sector Unprotect

Note: The term “sector” in the figure applies to both sectors and sector blocks * No other command is allowed during this process ** Access time is 200ns-300ns

Figure 2-2. Software Sector/Sector Block Protection and Unprotection Algorithms

PLSCNT=

1000?

Yes

Device failed

Algorithm

Read from sector address with A6=1,

A1=1, A0=0

Data=00h?**

Last sector

verified?

Write reset Command

Sector Unprotect

complete

Set up

next sector

address

Yes

(November, 2007, Version 1.1) 16 AMIC Technology, Corp.

Page 18

A29L320A Series

Common Flash Memory Interface (CFI)

The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interface for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is

ready to read array data. The system can read CFI information at the addresses given in Table 5-8. In word mode, the upper address bits (A7-MSB) must be all zeros. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Table 5-8. The system must write the reset command to return the device to the autoselect mode.

Table 7. CFI Query Identification String

Addresses

(Word Mode)

10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah

Addresses

(Byte Mode)

20h 22h 24h 26h 28h 2Ah

2Ch

2Eh 30h 32h 34h

Data Description

0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h

Query Unique ASCII string “QRY”

Primary OEM Command Set

Address for Primary Extended Table

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

Table 8. System Interface String

Addresses

(Word Mode)

1Bh 36h 0027h VCC Min. (write/erase)

Addresses

(Byte Mode)

Data Description

I/O7- I/O4 : volt, I/O3- I/O0: 100 millivolt

1Ch 38h 0036h VCC Max. (write/erase)

I/O7- I/O4: volt, I/O3- I/O0: 100 millivolt

1Dh 3Ah 0000h Vpp Min. voltage (00h = no Vpp pin present) 1Eh 3Ch 0000h Vpp Max. voltage (00h = no Vpp pin present) 1Fh 3Eh 0004h

20h 40h 0000h 21h 42h 000Ah Typical timeout per individual block erase 2N ms 22h 44h 0000h Typical timeout for full chip erase 2N ms (00h = not supported) 23h 46h 0005h Max. timeout for b yte/word write 2N times typical 24h 48h 0000h Max. timeout for buffer write 2N times typical 25h 4Ah 0004h Max. timeout per individual block erase 2N times typical 26h 4Ch 0000h Max. timeout for full chip erase 2N times typical (00h = not supported)

Typical timeout per single byte/word write 2 Typical timeout for Min. size buffer write 2

μs

μs (00h = not supported)

(November, 2007, Version 1.1) 17 AMIC Technology, Corp.

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A29L320A Series

Table 9. Device Geometry Definition

Addresses

(Word Mode)

27h 4Eh 0016h Device Size = 2N byte 28h

29h 2Ah 2Bh 2Ch 58h 0002h Number of Erase Block Regions within device 2Dh 2Eh 2Fh

30h

31h

32h

33h

34h

35h

36h

37h

38h

39h 3Ah

3BH

3Ch

Addresses

(Byte Mode)

50h 52h 54h 56h

5Ah

5Ch

5Eh 60h 62h 64h 66h 68h 6Ah

6Ch

6Eh 40h 72h 74h 76h 78h

Data Description

0002h 0000h 0000h 0000h

0007h 0000h 0020h 0000h 003Eh 0000h 0000h 0001h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h

Flash Device Interface description

Max. number of byte in multi-byte write = 2N (00h = not supported)

Erase Block Region 1 Information (refer to the CFI specification)

Erase Block Region 2 Information

Erase Block Region 3 Information

Erase Block Region 4 Information

(November, 2007, Version 1.1) 18 AMIC Technology, Corp.

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A29L320A Series

Table 10. Primary Vendor-Specific Extended Query

Addresses

(Word Mode)

40h

41h

42h

43h 86h 0031h Major version number, ASCII

44h 88h 0031h Minor version number, ASCII

45h 8Ah 0000h Address Sensitive Unlock

46h 8Ch 0002h Erase Suspend

47h 8Eh 0001h Sector Protect

48h 90h 0001h Sector Temporary Unprotect

49h 92h 0004h Sector Protect/Unprot ect scheme

4Ah 94h 0000h Simultaneous Operation

4Bh 96h 0000h Burst Mode Type

4Ch 98h 0000h Page Mode Type

4Dh 9Ah 0085h ACC (Acceleration) Supply Minimum

4Eh 9Ch 009 5h ACC (Acceleration) Supply Maximum

4Fh 9Eh 000Xh Top/Bottom Boot Sector Flag

Addresses

(Byte Mode)

80h 82h 84h

Data Description

0050h 0052h 0049h

Query-unique ASCII string “PRI”

0 = Required, 1 = Not Required

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

0 = Not Supported, X = Number of sectors in per group

00 = Not Supported, 01 = Supported

01 = 29F040 mode, 02 = 29F016 mode, 03 = 29F400 mode, 04 = 29L160 mode

00 = Not Supported, 01 = Supported

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

00 = Not Supported, D7-D4: Volt, D3-D0: 100mV

02 = Bottom Boot Device, 03h = Top Boot Device

(November, 2007, Version 1.1) 19 AMIC Technology, Corp.

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A29L320A Series

Command Definitions

Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data.

All addresses are latched on the falling edge of whichever happens later. All data is latched on the rising

edge of appropriate timing diagrams in the "AC Characteristics" section.

or CE, whichever happens first. Refer to the

or CE,

Reading Array Data

The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See "Erase Suspend/Erase Resume Commands" for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if I/O5 goes high, or while in the autoselect mode. See the "Reset Command" section, next. See also "Requirements for Reading Array Data" in the "Device Bus Operations" section for more information. The Read Operations table provides the read parameters, and Read Operation Timings diagram shows the timing diagram.

Reset Command

Writing the reset command to the device resets the device to reading array data. Address bits are don't care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If I/O5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. The Command Definitions table shows the address and data requirements. This method is an alternative to that shown in the Autoselect Codes (High Voltage Method) table, which is intended for PROM programmers and requires VID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code and another read cycle at XX11h retrieves the continuation code. A read cycle at address XX01h returns the device code. A read cycle containing a sector address (SA) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. Refer to the Sector Address tables for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data.

Word/Byte Program Command Sequence

The system may program the device by word or byte, depending on the state of the

four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verify the programmed cell margin. Table 9 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are longer latched. The system can determine the status of the

program operation by using I/O Operation Status” for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. T he Byte Program command sequence should be reinitiated once t he device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set I/O5 to

“1”, or cause the operation was successful. However, a succeeding read will

show that the data is still “0”. Only erase operations can convert a “0” to a “1”.

Polling algorithm to indicate the

Data

pin. Programming is a

BYTE

7, I/O6, or RY/

. See “White

(November, 2007, Version 1.1) 20 AMIC Technology, Corp.

Page 22

A29L320A Series

START

Write Program

Command Sequence

Embedded

Program

algorithm in

progress

Data Poll

from System

Verify Data ?

Yes

Increment Address

Last Address ?

Yes

Programming

Completed

Note : See the appropriate Command Definitions table for program command sequence.

Figure 3. Program Operation

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 9 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the twocycle unlock bypass reset command sequence. The first cycle must contain the data 90h; the second cycle the data

00h. Addresses are don’t care for both cycle. The device returns to reading array data. Figure 3 illustrates the algorithm for the program operation. See the Erase/Program Operations in “AC Characteristics” for parameters, and to Program Operation Timings for timing diagrams.

Chip Erase Command Sequence

Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The Command Definitions table shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Embedded Erase algorithm are ignored. The system can determine the status of the erase operation by using I/O7, I/O6, or I/O2. See "Write Operation Status" for information on these status bits. When the Embedded Erase algorithm is complete, the devic e returns to reading array data and addresses are no longer latched. Figure 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in "AC Characteristics" for parameters, and to the Chip/Sector Erase Operation Timings for timing waveforms.

Sector Erase Command Sequence

Sector erase is a six-bus-cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. The Command Definitions table shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase timeout of 50μs begins. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50μs, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50μs, the system need not monitor I/O Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands.

3. Any command other than

(November, 2007, Version 1.1) 21 AMIC Technology, Corp.

Page 23

A29L320A Series

The system can monitor I/O3 to determine if the sector erase timer has timed out. (See the " I/O

3: Sector Erase Timer"

section.) The time-out begins from the rising edge of the final

pulse in the command sequence.

Once the sector erase operation has begun, only the Eras e Suspend command is valid. All other commands are ignored. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using I/O7, I/O6, or I/O2. Refer to "Write Operation Status" for information on these status bits. 4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the "AC Characteristics" section for parameters, and to the Sector Erase Operations Timing diagram for timing waveforms.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50μs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are "don't cares" when writing the Erase Suspend command. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20μs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors produces status data on I/O7

- I/O0. The system can use I/O7, or I/O6 and I/O2 together, to determine if a sector is actively erasing or is erasesuspended. See "Write Operation Status" for information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within nonsuspended sectors. The system can determine the status of the program operation using the I/O as in the standard program operation. See "Write Operation Status" for more information. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See "Autoselect Command Sequence" for more information.

7 or I/O6 status bits, just

The system must write the Erase Resume command (address bits are "don't care") to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing.

START

Write Erase

Command Sequence

Data Poll

from System

Data = FFh ?

Embedded Erase algorithm in progress

Yes

Erasure Completed

Note :

1. See the appropriate Command Definitions table for erase command sequences.

2. See "I/O

: Sector Erase Timer" for more information.

Figure 4. Erase Operation

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Page 24

A29L320A Series

Table 11. A29L320A Command Definitions

Command

Sequence

(Note 1)

First Second Third Fourth Fifth Sixth

Cycles

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read (Note 6) 1 RA RD Reset (Note 7) 1 XXX F0

Manufacturer ID

Top Boot Block

Bottom Boot Block

Continuation ID

Autoselect (Note 8)

Sector Protect Verify

(Note 9)

CFI Query (Note 10)

Command Temporary Sector Unprotect (Note9)

Program

Unlock Bypass Unlock Bypass Program (Note

Word 555 2AA 555

Word 555 2AA 555 X01 22F6Device ID,

Word 555 2AA 555 X01 22F9Device ID,

Word 555 2AA 555 X03 Byte

Byte

AAA

555

Word 555 2AA 555

Byte Word 55

Byte

Word 555 2AA 555

Byte

Byte 555 2AA 555 Byte

Word 555 2AA 555

Byte

AAA

555

2 XXX A0 PA PD

11) Unlock Bypass Reset (Note 12) 2 XXX 90 XXX 00

Chip Erase

Sector Erase

Word 555 2AA 555 555 2AA 555

Word 555 2AA 555 555 2AA

Byte

AAA

555

555 Erase Suspend (Note 13) 1 XXX B0 Erase Resume (Note 14) 1 XXX 30

Legend: X = Don't care RA = Address of the memory location to be read. RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the

whichever happens later.

PD = Data to be programmed at location PA. Data la tches on th e rising edge o f SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A20- A12 select a unique sector.

Bus Cycles (Notes 2 - 5)

90 X00 37

AAA

A0 PA PD

AAA

X02 F6

X02 F9

X06 (SA)

X02

(SA) X04

XX00 XX01

00 01

AAA

555

55 SA 30

555

AAA

or CE pulse,

or CE pulse, whichever happens first.

(November, 2007, Version 1.1) 23 AMIC Technology, Corp.

Page 25

A29L320A Series

Note:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or autosel ect data, all bus cycles are write operation.

4. Address bits A20 - A11 are don't cares for unlock and command cycles, unless SA or PA required.

5. No unlock or command cycles required when reading array data.

6. The Reset command is required to return to reading array data when device is in the autoselect mode, or if I/O

5 goes high

(while the device is providing status data).

7. The fourth cycle of the autoselect command sequence is a read cycle.

8. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more information.

9. Once a reset command is applied, software temporary unprotect is exit to return to read array data. But under erase suspend condition, this command is still effective even a reset command has been appli ed. The reset command which can deactivate the software temporary unprotect command is useful only after the erase command is complete.

10. Command is valid when device is ready to r ead array data or when device is in autoselect mode.

11. The Unlock Bypass command is required pri or to the Unlock Bypass Program command.

12. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode.

13. The system may read and program in non-e rasing secto rs, or en te r the au tosele ct mode , when in the Era se Suspend mode .

14. The Erase Resume command is valid only during the Erase Suspen d mode.

(November, 2007, Version 1.1) 24 AMIC Technology, Corp.

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A29L320A Series

Write Operation Status

Several bits, I/O2, I/O3, I/O5, I/O6, I/O7, RY/ the A29L320A to determine the status of a write operation. Table 10 and the following subsections describe the

functions of these status bits. I/O

7, I/O6 and RY/BY each

offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first.

are provided in

START

Read I/O7-I/O

Address = VA

I/O7:

The

Polling

Data

Polling bit, I/O7, indicates to the host system

Data

whether an Embedded Algorithm is in progress or completed, or whether the device is in Erase Suspend.

Data

Polling is

valid after the rising edge of the final WE pulse in the program or erase command sequence. During the Embedded Program algorithm, the device outputs

7 the complement of the datum programmed to I/O7.

on I/O This I/O

7 status also applies to programming during Erase

Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to I/O7. The system must provide the program address to read valid status information on I/O7. If a program address falls within a

protected sector,

Polling on I/O7 is active for

Data

approximately 2μs, then the device returns to reading array data.

During the Embedded Erase algorithm,

Data

Polling

produces a "0" on I/O7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode,

Polling produces a "1" on I/O7.This is analogous to the

Data

complement/true datum output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to "1"; prior to this, the device outputs the "complement," or "0." The system must provide an address within any of the sectors selected for erasure to read valid status information on I/O

After an erase command sequence is written, if all sectors selected for erasing are protected,

Polling on I/O7 is

Data

active for approximately 100μs, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. When the system detects I/O complement to true data, it can read valid data at I/O on the following read cycles. This is because I/O change asynchronously with I/O

) is asserted low. The

(

7 has changed from the

7 - I /O0

7 may

0 - I/O6 while Output Enable

Polling Timings (During

Data

Embedded Algorithms) figure in the "AC Characteristics" section illustrates this. Table 10 shows the outputs for

Polling on I/O

7. Figure 5 shows the

Polling algorithm.

Data

Yes

I/O7 = Data ?

Note :

1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address.

2. I/O

should be rechecked even if I/O5 = "1" because

I/O

may change simultaneously with I/O5.

I/O5 = 1?

Yes

Read I/O7 - I/O

Address = VA

I/O7 = Data ?

FAIL

Yes

PASS

Figure 5. Data Polling Algorithm

(November, 2007, Version 1.1) 25 AMIC Technology, Corp.

Page 27

A29L320A Series

RY/

The RY/

: Read/

is a dedicated, open-drain output pin that

Busy

indicates whether an Embedded algorithm is in progress or complete. The RY/ the final

pulse in the command sequence. Since RY/BY

is an open-drain output, several RY/

status is valid after the rising edge of

pins can be tied

together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode.

Table 10 shows the outputs for RY/

. Refer to “

RESET

Timings”, “Timing Waveforms for Program Operation” and “Timing Waveforms for Chip/Sector Erase Operation” for more information.

I/O6: Toggle Bit I

Toggle Bit I on I/O6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge

of the final program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause I/O6 to toggle.

(The system may use either OE or CE to control the read cycles.) When the operation is complete, I/O6 stops toggling. After an erase command sequence is written, if all sectors

selected for erasing are protected, I/O6 toggles for approximately 100μs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use I/O whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), I/O enters the Erase Suspend mode, I/O However, the system must also use I/O sectors are erasing or erase-suspended. Alternatively, the

system can use I/O Polling").

If a program address falls within a protected sector, I/O toggles for approximately 2μs after the program command sequence is written, then returns to reading array data.

6 also toggles during the erase-suspend-program mode,

I/O and stops toggling once the Embedded Program algorithm is complete. The Write Operation Status table shows the outputs for Toggle Bit I on I/O algorithm, and to the Toggle Bit Timings figure in the "AC Characteristics" section for the timing diagram. The I/O2 vs.

6 figure shows the differences between I/O2 and I/O6 in

I/O graphical form. See also the subsection on " I/O II".

pulse in the command sequence (prior to the

6 and I/O2 together to determine

6 toggles. When the device

6 stops toggling.

2 to determine which

7 (see the subsection on " I/O7 :

6. Refer to Figure 6 for the toggle bit

2: Toggle Bit

Data

I/O2: Toggle Bit II

The "Toggle Bit II" on I/O2, when used with I/O6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the

rising edge of the final WE pulse in the command sequence.

2 toggles when the system reads at addresses within those

I/O sectors that have been selected for erasure. (The system may

use either

or CE to control the read cycles.) But I/O2

cannot distinguish whether the sector is actively erasing or is erase-suspended. I/O

6, by comparison, indicates whether the

device is actively erasing, or is in Erase Suspend, but c annot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 10 to compare outputs for I/O

2 and I/O6.

Figure 6 shows the toggle bit algorithm in flowchart form, and the section " I/O also the " I/O

2: Toggle Bit II" explains the algorithm. See

6: Toggle Bit I" subsection. Refer to the Toggle

Bit Timings figure for the toggle bit timing diagram. The I/O vs. I/O

6 figure shows the differences between I/O2 and I/O6 in

graphical form.

Reading Toggle Bits I/O6, I/O2

Refer to Figure 6 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read I/O7 - I/O0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on I/O7 - I/O0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of I/O

5). If it is, the system should then determine again

on I/O

5 is high (see the section

whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as I/O5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and I/O

5 has not gone high. The

system may continue to monitor the toggle bit and I/O through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure

6).

I/O5: Exceeded Timing Limits

I/O5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions I/O5 produces a "1." This is a failure condition that indicates the program or erase cycle was not successfully completed.

(November, 2007, Version 1.1) 26 AMIC Technology, Corp.

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A29L320A Series

The I/O

5 failure condition may appear if the system tries to

program a "1 "to a location that is previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, I/O5 produces a "1." Under both these conditions, the system must issue the reset command to return the device to reading array data.

I/O3: Sector Erase Timer

After writing a sector erase command sequence, the system may read I/O operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out is complete, I/O ignore I/O between additional sector erase commands will always be less than 50μs. See also the "Sector Erase Command Sequence" section. After the sector erase command sequence is written, the

system should read the status on I/O (Toggle Bit 1) to ensure the device has accepted the

command sequence, and then read I/O internally controlled erase cycle has begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If I/O accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of I/O subsequent sector erase command. If I/O second status check, the last command might not have been accepted. Table 10 shows the outputs for I/O3.

3 to determine whether or not an erase

3 switches from "0" to "1." The system may

3 if the system can guarantee that the time

7 (

3 is "0", the device will

3 prior to and following each

Polling) or I/O6

Data

3. If I/O3 is "1", the

3 is high on the

START

Read I/O7-I/O

Toggle Bit

= Toggle ?

Yes

I/O5 = 1?

Yes

Read I/O7 - I/O

Twice

Toggle Bit

= Toggle ?

Yes

(Note 1)

(Notes 1,2)

Program/Erase

Operation Not

Commplete, Write

Reset Command

Notes :

1. Read toggle bit twice to determine whether or not it is toggling. See text.

2. Recheck toggle bit because it may stop toggling as I/O changes to "1". See text.

Program/Erase

Operation Complete

Figure 6. Toggle Bit Algorithm

(November, 2007, Version 1.1) 27 AMIC Technology, Corp.

Page 29

A29L320A Series

Table 12. Write Operation Status

Operation

I/O7 I/O6 I/O5 I/O3 I/O2

(Note 1) (Note 2) (Note 1)

Standard Mode

Erase Suspend Mode

Embedded Program Algorithm

7I/O

Toggle 0 N/A No toggle 0

Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0 Reading within Erase

Suspended Sector Reading within Non-Erase

Suspend Sector Erase-Suspend-Program

1 No toggle 0 N/A Toggle 1

Data Data Data Data Data 1

7I/O

Toggle 0 N/A N/A 0

Notes:

1. I/O

7 and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

2. I/O

5 switches to “1” when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “I/O5: Exceeded Timing Limits” for more information.

Maximum Negative Input Overshoot

20ns 20ns

+0.8V

RY/BY

-0.5V

-2.0V

Maximum Positive Input Overshoot

VCC+2.0V

VCC+0.5V

2.0V

20ns

20ns20ns

(November, 2007, Version 1.1) 28 AMIC Technology, Corp.

Page 30

A29L320A Series

DC Characteristics

CMOS Compatible

Parameter

Symbol

ILI Input Load Current

Parameter Description

Test Description

IN = VSS to VCC. VCC = VCC Max

Min.

Typ.

ILIT A9 Input Load Current VCC = VCC Max, A9 =12.5V 35

ILO

ICC1

ICC2

Output Leakage Current

VCC Active Read Current (Notes 1, 2)

VCC Active Write (Program/Erase) Current (Notes 2, 3, 4)

ICC3 ICC4

VCC Standby Current (Note 2) VCC Standby Current During Reset

(Note 2)

ICC5

Automatic Sleep Mode (Note 2, 4, 5)

VIL Input Low Level VIH Input High Level

VHH

VID

Voltage for Unprotect and Program Acceleration

Voltage for Autoselect and

/ACC Sector Protect/

Temporary Unprotect Sector

VOL Output Low Voltage VOH1 VOH2

Output High Voltage

OUT = VSS to VCC. VCC = VCC Max

= VIL, OE = VIH

Byte Mode

= VIL, OE = VIH

5 MHz 1 MHz

Word Mode

= VIL, OE =VIH

RESET

IH = VCC ± 0.3V; VIL = VSS ± 0.3V

= VCC ± 0.3V

= VSS ± 0.3V

VCC=3.0V ± 10%

VCC = 3.0 V ± 10% I

OL = 4.0mA, VCC = VCC Min OH = -2.0 mA, VCC = VCC Min

I IOH = -100 μA, VCC = VCC Min

5 MHz 1 MHz

10 16

2 4

0.5

0.5 5

-0.5

0.7 x VCC

8.5

0.85 x VCC VCC - 0.4

Max.

Unit

±1.0 μA

μA

±1.0

μA

30 Ma

μA μA

μA

0.8

VCC + 0.3 V

10.5 V

10.5

0.45

V V

Notes:

CC current listed is typically less than 2 mA/MHz, with

1. The I

2. Maximum I

CC active while Embedded Algorithm (program or erase) is in progress.

3. I

CC specifications are tested with VCC = VCC max.

at VIH. Typical VCC is 3.3V.

4. Automatic sleep mode enables the low power mode when addresses remain stable for t is 500nA.

5. Not 100% tested.

ACC + 30ns. Typical sleep mode current

(November, 2007, Version 1.1) 29 AMIC Technology, Corp.

Page 31

A29L320A Series

DC Characteristics (continued)

Zero Power Flash

Supply Current in mA

0 500 1000 1500 2000 2500 3000 3500 4000

Time in ns

Note: Addresses are switching at 1MHz

Supply Current in mA

CC1

Current vs. Time (Showing Active and Automatic Sleep Currents)

3.6V

3.0V

12345

Frequency in MHz

C25T :Note °=

Typical ICC1 vs. Frequency

(November, 2007, Version 1.1) 30 AMIC Technology, Corp.

Page 32

A29L320A Series

AC Characteristics

Read Only Operations

Parameter

Description Test Setup

Symbols

JEDEC

tAVAV tRC tAVQV

tELQV tGLQV tOE

tEHQZ

Std

ACC

tOEH

Read Cycle Time (Note 1) Address to Output Delay

Chip Enable to Output Delay Output Enable to Output Delay

Read

Output Enable Hold Time (Note 1)

Toggle and

Data

Chip Enable to Output High Z

Polling

(Notes 1)

tGHQZ

Output Enable to Output High Z

(Notes 1) Output Hold Time from Addresses,

tAXQX tOH

or OE, Whichever Occurs First

(Note 1)

Notes:

1. Not 100% tested.

2. See Test Conditions and Test Setup for test specifications.

Timing Waveforms for Read Only Operation

CE OE

= VIL = VIL

= VIL

Min.

Max.

Max. Max.

Max.

Min.

Speed Unit

-70

70 30

-80

80 30

-90

90 40

-120

120

0 0

10 10 10 10

16 16 16 16

ns ns ns

16 16 16 16 ns

0 0 0 0 ns

Addresses Addresses Stable

ACC

Output

RESET

RY/BY

OEH

High-Z

Output Valid

High-Z

(November, 2007, Version 1.1) 31 AMIC Technology, Corp.

Page 33

A29L320A Series

AC Characteristics Hardware Reset (

Parameter

JEDEC Std

tRP tRH tRB tRPD

Note: Not 100% tested.

RESET

READY

Timings

RY/BY

RESET

Algorithms) to Read or Write (See Note)

RESET

Algorithms) to Read or Write (See Note)

RESET

RY/

RESET

)

Description Test Setup All Speed Options Unit

Pin Low (During Embedded

Pin Low (Not During Embedded

Pulse Width High Time Before Read (See Note)

Recovery Time

Low to Standby Mode

Max 20

Max 500 ns

Min 500 ns Min 50 ns Min 0 ns Min 20

μs

CE, OE

RESET

RY/BY

CE, OE

RESET

Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

Ready

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Page 34

A29L320A Series

Temporary Sector Unprotect

Parameter

JEDEC Std

tVHH VHH Rise and Fall Time (See Note) Min 250 ns

Note: Not 100% tested.

VIDR VID Rise and Fall Time (See Note) Min 500 ns

RSP

RRB

RESET

Unprotect

RESET

Temporary Sector/Sector Block Unprotect

Setup Time for Temporary Sector

Hold Time from RY/BY High for

Description All Speed Options Unit

Min 4

Temporary Sector Unprotect Timing Diagram

VID

VSS, VIL,

or V

RESET

RY/BY

VID VSS, VIL,

or V

tVIDR

tRSP

Program or Erase Command Sequence

tVIDR

tRRB

μs

Accelerated Program Timing Diagram

VCC

WP/ACC

VHH

VIL or VIH VIL or VIH

tVHH tVHH

AC Characteristics

Word/Byte Configuration (

Parameter All Speed Options

JEDEC Std

tELFL/tELFH tFLQZ

tHQV

BYTE BYTE

)

BYTE

Description

Switching Low or High

BYTE

Switching Low to Output High-Z Switching High to Output Active

Max Max

Min

-70 -80 -90 -120

25 25 30 30 70 80 90 120

Unit

ns ns

(November, 2007, Version 1.1) 33 AMIC Technology, Corp.

Page 35

A29L320A Series

Timings for Read Operations

BYTE

Switching

I/O0-I/O

ELFL

Data Output

-I/O14)

(I/O

Data Output

-I/O7)

(I/O

from word to

byte mode

I/O

(A-1)

ELFH

FLQZ

I/O

Output

Address Input

BYTE

I/O0-I/O

Switching

from byte to

I/O

word mode

(A-1)

Timings for Write Operations

BYTE

Note:

Refer to the Erase/Program Operations table for t

Data Output

(I/O

Address Input

FHQV

SET

(tAS)

AS and tAH specifications.

Data Output

-I/O7)

(I/O

I/O

Output

-I/O14)

The falling edge of the last WE signal

HOLD(tAH

)

(November, 2007, Version 1.1) 34 AMIC Technology, Corp.

Page 36

A29L320A Series

AC Characteristics

Erase and Program Operations

Parameter Speed

JEDEC

tAVAV tAVWL

tWLAX tDVWH tWHDX

tGHWL

Std

OES

GHWL

Write Cycle Time (Note 1) Address Setup Time

Address Hold Time

Data Setup Time

Data Hold Time Output Enable Setup Time Read Recover Time Before Write

Description

Min. Min. Min. Min. Min. Min.

Min.

-70 -80 -90

70 80 90

0 0 0 0 40 45 45 40 45 45

(OE high to WE low)

tELWL tCS

tWHEH tWLWH tWHWL

WPH

tWHWH1 tWHWH1

Setup Time

Hold Time

Write Pulse Width Write Pulse Width High

Byte Programming Operation (Note 2)

Byte Typ. 6

Word Typ. 9

Min. Min. Min.

Min.

30 35 35

0 0

-120

120

50 50

Unit

ns ns ns ns ns ns

ns ns ns ns

μs

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ. 0.7 sec

BUSY

VCC Set Up Time (Note 1)

vcs

Recovery Time from RY/ Program/Erase Valid to RY/

(Note 1)

Delay (Note 1)

Min.

Min Min

Notes:

1. Not 100% tested.

2. See the "Erase and Programming Performance" section for more information.

μs ns ns

(November, 2007, Version 1.1) 35 AMIC Technology, Corp.

Page 37

A29L320A Series

Timing Waveforms for Program Operation

Addresses

Data

RY/BY

VCC

VCS

Program Command Sequence (last two cycles)

555h

A0h PD

WPH

BUSY

Read Status Data (last two cycles)

WHWH1

Status

OUT

Note :

1. PA = program addrss, PD = program data, Dout is the true data at the program address.

2. Illustration shows device in word mode.

(November, 2007, Version 1.1) 36 AMIC Technology, Corp.

Page 38

A29L320A Series

Timing Waveforms for Chip/Sector Erase Operation

Addresses

Data

RY/BY

VCC

VCS

Erase Command Sequence (last two cycles)

2AAh

555h for chip erase

55h 30h

WPH

10h for chip erase

~ ~

BUSY

~ ~

WHWH2

Read Status Data

Progress

Complete

Note :

1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operaion Ststus").

2. Illustratin shows device in word mode.

(November, 2007, Version 1.1) 37 AMIC Technology, Corp.

Page 39

A29L320A Series

Timing Waveforms for

Addresses

tCH

I/O7

tOEH

Polling (During Embedded Algorithms)

Data

tRC

tACC

tCE

tOE

tDF

tOH

Complement

VAVA VA

Complement True

Valid Data

High-Z

I/O

0 - I/O6

RY/BY

Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data read cycle.

High-Z

tBUSY

Status Data

Status Data True

Valid Data

High-Z

(November, 2007, Version 1.1) 38 AMIC Technology, Corp.

Page 40

A29L320A Series

Timing Waveforms for Toggle Bit (During Embedded Algorithms)

Addresses

VAVA VA

ACC

I/O6 ,

RY/BY

I/O

OEH

High-Z

BUSY

Valid Status

(first read) (second read) (stop togging)

Valid Status Valid Status Valid Data

Note: VA = Valid Address; not required for I/O6. Illustration shows first two status cycle after command sequence, last status

read cycle, and array data read cycle.

(November, 2007, Version 1.1) 39 AMIC Technology, Corp.

Page 41

A29L320A Series

Timing Waveforms for Sector Protect/Unprotect

RESET

SA, A6,

A1, A0

Data

Valid* Valid* Valid*

Sector Protect/Unprotect Verify

60h 60h 40h Status

1us

Sector Protect:150us

Sector Unprotect:15ms

Note : For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0

Timing Waveforms for I/O

Enter

Embedded

Erasing

I/O

2 vs. I/O6

Erase

Suspend

Erase

Erase Suspend

Read

Enter Erase

Suspend Program

Erase Suspend Program

Resume

Erase Suspend

Read

Erase

Complete

I/O

and I/O6 toggle with OE and CE

Note : Both I/O6 and I/O2 toggle with OE or CE. See the text on I/O6 and I/O2 in the section "Write Operation Status" for more information.

(November, 2007, Version 1.1) 40 AMIC Technology, Corp.

Page 42

A29L320A Series

Timing Waveforms for Alternate CE Controlled Write Operation

PA for program SA for sector erase 555 for chip erase

CPH

BUSY

PD for program 30 for sector erase 10 for chip erase

Data Polling

WHWH1 or 2

I/O

OUT

Addresses

Data

RESET

555 for program

2AA for erase

A0 for program 55 for erase

RY/BY

Note :

1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O

2. Figure indicates the last two bus cycles of the command sequence.

= Complement of Data Input, D

OUT

= Array Data.

Erase and Programming Performance

Parameter Typ. (Note 1) Unit Comments

Sector Erase Time 0.7 sec Chip Erase Time 45 sec Byte Programming Time 6 Word Programming Time 9

μs μs

Byte Mode 32 sec Chip Programming Time

(Note 2)

Word Mode 20 sec

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0V VCC, 100,000 cycles. Additionally, programming typically assumes checkerboard pattern..

2. The typical chip programming time is considerably less than the ma ximum chip programming time listed, since most bytes program faster than the maximum byte program time listed. If the maximum byte program time given is exc eeded, only then does the device set I/O

5 = 1. See the section on I/O5 for further information.

3. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h befor e erasure.

4. System-level overhead is the time required to execute the four-bus-cycle comman d sequence for programming. See Table 9 for further information on command definitions.

5. The device has a guaranteed minimum erase and progra m cycle endurance of 100,000 cycles.

Excludes 00h programming prior to erasure

Excludes system-level overhead (Note 4)

(November, 2007, Version 1.1) 41 AMIC Technology, Corp.

Page 43

A29L320A Series

Latch-up Characteristics

Description Min. Max.

Input Voltage with respect to VSS on all I/O pins

-1.0V

VCC+1.0V VCC Current Input voltage with respect to VSS on all pins except I/O pins

(including A9, OEand

RESET

)

Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at time.

TSOP/TFBGA Pin Capacitance

Parameter Symbol

CIN Input Capacitance

COUT

CIN2 Control Pin Capacitance

Notes:

1. Sampled, not 100% tested.

2. Test conditions TA = 25°C, f = 1.0MHz

Parameter Description

Output Capacitance

Test Setup

IN=0

OUT=0

IN=0

Data Retention

Parameter

Test Conditions

TSOP

TFBGA

TSOP

TFBGA

TSOP

TFBGA

-100 mA

-1.0V

Typ.

4.2

8.5

5.4

7.5

3.9

Min

Max.

7.5 5

6.5 9

4.7

+100 mA

12.5V

Unit

pF pF pF pF

pF pF

Unit

Minimum Pattern Data Retention Time

150°C 125°C

10 Years 20 Years

(November, 2007, Version 1.1) 42 AMIC Technology, Corp.

Page 44

A29L320A Series

Test Conditions

Test Specifications

Test Condition -70 -80 -90 -120 Unit

Output Load 1 TTL gate Output Load Capacitance, CL(including jig capacitance) 30 100 100 100 pF Input Rise and Fall Times 5 ns Input Pulse Levels 0.0 – VCC V Input timing measurement reference levels 0.5VCC V Output timing measurement reference levels 0.5VCC V

Test Setup

3.0V

2.7 KW

Device

Under

Test

Input Waveforms and Measurement Levels

VCC

Input 0.5VCC 0.5VCC Output

0.0V

6.2 KW

Measurement Level

Diodes = IN3064 or Equival en t

(November, 2007, Version 1.1) 43 AMIC Technology, Corp.

Page 45

A29L320A Series

Ordering Information Top Boot Sector Flash

Part No.

A29L320ATV-70 48Pin TSOP

A29L320ATV-70U 48Pin TSOP

A29L320ATV-70I 48Pin TSOP

A29L320ATV-70F 48 Pin Pb-Free TSOP

A29L320ATV-70UF 48 Pin Pb-Free TSOP

A29L320ATV-70IF 48 Pin Pb-Free TSOP

A29L320ATG-70 48 ball TFBGA

A29L320ATG-70U 48 ball TFBGA

A29L320ATG-70I 48 ball TFBGA

A29L320ATG-70F 48 ball Pb-Free TFBGA

A29L320ATG-70UF 48 ball Pb-Free TFBGA

Access Time

(ns)

70 10 20 0.5

Active Read

Current

Typ. (mA)

Program/Erase

Current

Typ. (mA)

Standby Current

Typ. (μA)

Package

A29L320ATG-70IF

A29L320ATV-80 48Pin TSOP

A29L320ATV-80U 48Pin TSOP

A29L320ATV-80I 48Pin TSOP

A29L320ATV-80F 48Pin Pb-Free TSOP

A29L320ATV-80UF 48Pin Pb-Free TSOP

A29L320ATV-80IF 48Pin Pb-Free T SOP

80 10 20 0.5

A29L320ATG-80 48 ball TFBGA

A29L320ATG-80U 48 ball TFBGA

A29L320ATG-80I 48 ball TFBGA

A29L320ATG-80F 48 ball Pb-Free TFBGA

A29L320ATG-80UF 48 ball Pb-Free TFBGA

A29L320ATG-80IF

48 ball Pb-Free TFBGA

Note: -U is for industrial operating temperature range: -40°C to +85°C

-I is for industrial operating temperature range: -25°C to +85°C

(November, 2007, Version 1.1) 44 AMIC Technology, Corp.

Page 46

A29L320A Series

Ordering Information (continued) Top Boot Sector Flash

Part No.

A29L320ATV-90 48Pin TSOP

A29L320ATV-90U 48Pin TSOP

A29L320ATV-90I 48Pin TSOP

A29L320ATV-90F 48Pin Pb-Free TSOP

A29L320ATV-90UF 48Pin Pb-Free TSOP

A29L320ATV-90IF 48Pin Pb-Free T SOP

A29L320ATG-90 48 ball TFBGA

A29L320ATG-90U 48 ball TFBGA

A29L320ATG-90I 48 ball TFBGA

A29L320ATG-90F 48 ball Pb-Free TFBGA

A29L320ATG-90UF 48 ball Pb-Free TFBGA

Access Time

(ns)

90 10 20 0.5

Active Read

Current

Typ. (mA)

Program/Erase

Current

Typ. (mA)

Standby Current

Typ. (μA)

Package

A29L320ATG-90IF

A29L320ATV-120 48Pin TSOP

A29L320ATV-120U 48Pin TSOP

A29L320ATV-120I 48Pin TSOP

A29L320ATV-120F 48Pin Pb-Free TSOP

A29L320ATV-120UF 48Pin Pb-Free TSOP

A29L320ATV-120IF 48Pin Pb-Free TSOP

120 10 20 0.5

A29L320ATG-120 48 ball TFBGA

A29L320ATG-120U 48 ball TFBGA

A29L320ATG-120I 48 ball TFBGA

A29L320ATG-120F 48 ball Pb-Free TFBGA

A29L320ATG-120UF 48 ball Pb-Free TFBGA

A29L320ATG-120IF

48 ball Pb-Free TFBGA

Note: -U is for industrial operating temperature range: -40°C to +85°C

-I is for industrial operating temperature range: -25°C to +85°C

(November, 2007, Version 1.1) 45 AMIC Technology, Corp.

Page 47

A29L320A Series

Ordering Information (continued) Bottom Boot Sector Flash

Part No.

A29L320AUV-70 48Pin TSOP

A29L320AUV-70U 48Pin TSOP

A29L320AUV-70I 48Pin TSOP

A29L320AUV-70F 48 Pin Pb-Free TSOP

A29L320AUV-70UF 48 Pin Pb-Free TSOP

A29L320AUV-70IF 48 Pin Pb-Free TSOP

A29L320AUG-70 48 ball TFBGA

A29L320AUG-70U 48 ball TFBGA

A29L320AUG-70I 48 ball TFBGA

A29L320AUG-70F 48 ball Pb-Free TFBGA

A29L320AUG-70UF 48 ball Pb-Free TFBGA

Access Time

(ns)

70 10 20 0.5

Active Read

Current

Typ. (mA)

Program/Erase

Current

Typ. (mA)

Standby Current

Typ. (μA)

Package

A29L320AUG-70IF

A29L320AUV-80 48Pin TSOP

A29L320AUV-80U 48Pin TSOP

A29L320AUV-80I 48Pin TSOP

A29L320AUV-80F 48Pin Pb-Free TSOP

A29L320AUV-80UF 48Pin Pb-Free TSOP

A29L320AUV-80IF 48Pin Pb-Free TSOP

80 10 20 0.5

A29L320AUG-80 48 ball TFBGA

A29L320AUG-80U 48 ball TFBGA

A29L320AUG-80I 48 ball TFBGA

A29L320AUG-80F 48 ball Pb-Free TFBGA

A29L320AUG-80UF 48 ball Pb-Free TFBGA

A29L320AUG-80IF

48 ball Pb-Free TFBGA

Note: -U is for industrial operating temperature range: -40°C to +85°C

-I is for industrial operating temperature range: -25°C to +85°C

(November, 2007, Version 1.1) 46 AMIC Technology, Corp.

Page 48

A29L320A Series

Ordering Information (continued) Bottom Boot Sector Flash

Part No.

A29L320AUV-90 48Pin TSOP

A29L320AUV-90U 48Pin TSOP

A29L320AUV-90I 48Pin TSOP

A29L320AUV-90F 48Pin Pb-Free TSOP

A29L320AUV-90UF 48Pin Pb-Free TSOP

A29L320AUV-90IF 48Pin Pb-Free TSOP

A29L320AUG-90 48 ball TFBGA

A29L320AUG-90U 48 ball TFBGA

A29L320AUG-90I 48 ball TFBGA

A29L320AUG-90F 48 ball Pb-Free TFBGA

A29L320AUG-90UF 48 ball Pb-Free TFBGA

Access Time

(ns)

90 10 20 0.5

Active Read

Current

Typ. (mA)

Program/Erase

Current

Typ. (mA)

Standby Current

Typ. (μA)

Package

A29L320AUG-90IF

A29L320AUV-120 48Pin TSOP

A29L320AUV-120U 48Pin TSOP

A29L320AUV-120I 48Pin T SOP

A29L320AUV-120F 48Pin Pb-Free TSOP

A29L320AUV-120UF 48Pin Pb-Free TSOP

A29L320AUV-120IF 48Pin Pb-Free TSOP

120 10 20 0.5

A29L320AUG-120 48 ball TFBGA

A29L320AUG-120U 48 ball TFBGA

A29L320AUG-120I 48 ball TFBGA

A29L320AUG-120F 48 ball Pb-Free TFBGA

A29L320AUG-120UF 48 ball Pb-Free TFBGA

A29L320AUG-120IF

48 ball Pb-Free TFBGA

Note: -U is for industrial operating temperature range: -40°C to +85°C

-I is for industrial operating temperature range: -25°C to +85°C

(November, 2007, Version 1.1) 47 AMIC Technology, Corp.

Page 49

A29L320A Series

Package Information TSOP 48L (Type I) Outline Dimensions

24 25

unit: inches/mm

y D

Detail "A"

0.25 Detail "A"

Symbol

A - - 0.047 - - 1.20 A1 0.002 - 0.006 0.05 - 0.15 A2 0.037 0.039 0.042 0.94 1.00 1.06

b 0.007 0.009 0.011 0.18 0.22 0.27 c 0.004 - 0.008 0.12 - 0.20

D 0.779 0.787 0.795 19.80 20.00 20.20

D1 0.720 0.724 0.728 18.30 18.40 18.50

E - 0.472 0.476 - 12.00 12.10

e 0.020 BASIC 0.50 BASIC L 0.020 0.024 0.0275 0.50 0.60 0.70

S 0.011 Typ. 0.28 Typ.

y - - 0.004 - - 0.10 θ

Dimensions in inches Dimensions in mm

Min Nom Max Min Nom Max

0° - 8° 0° - 8°

Notes:

1. The maximum value of dimension D includes end flash.

2. Dimension E does not include resin fins.

3. Dimension S includes end flash.

(November, 2007, Version 1.1) 48 AMIC Technology, Corp.

Page 50

A29L320A Series

Package Information 48LD CSP (6 x 8 mm) Outline Dimensions

(48TFBGA)

TOP VIEW

654321

unit: mm

BOTTOM VIEW

123456

H G F E D C B A

0.10 C

Ball*A1 CORNER

SIDE VIEW

SEATING PLANE

H G F E D C B A

Symbol

A - - 1.20

A1 0.20 0.25 0.30

b 0.30 - 0.40 D 5.90 6.00 6.10

D1 4.00 BSC

e - 0.80 E 7.90 8.00 8.10

E1 5.60 BSC

Dimensions in mm

Min.

Nom. Max.

(November, 2007, Version 1.1) 49 AMIC Technology, Corp.

Datasheet A29L320A Datasheet (AMIC)

Specifications and Main Features

Frequently Asked Questions

User Manual