Datasheet A29L160 Datasheet (AMIC)

A29L160 Series

2M X 8 Bit / 1M X 16 Bit CMOS 3.0 Volt-only,

Boot Sector Flash Memory

Document Title
2M X 8 Bit / 1M X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory

Revision History

Rev.

0.0 Initial issue July 31, 2002 Preliminary

0.1 Add 48pin Pb-Free TSOP Package for A29L160TV-70F & February 20, 2004

1.0 Final version release May 13, 2004 Final

History Issue Date Remark

A29L160UV-70F

Change storage temperature from “0°C to +70°C” to “-65°C to +150°C”
Change ambient temperature from “0°C to 70°C” to “-55°C to +125°C”

(May, 2004, Version 1.0)

AMIC Technology, Corp.

A29L160 Series

2M X 8 Bit / 1M X 16 Bit CMOS 3.0 Volt-only,

Boot Sector Flash Memory

Features

 Single power supply operation

- Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications

- Regulated voltage range: 3.0 to 3.6 volt read and write
operations for compatibility with high performance 3.3
volt microprocessors

 Access times:

- 70/90/120 (max.)

 Current:

- 9 mA typical active read current

- 20 mA typical program/erase current

- 200 nA typical CMOS standby

- 200 nA Automatic Sleep Mode current

 Flexible sector architecture

- 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX31 sectors

- 8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX31 sectors

- Any combination of sectors can be erased

- Supports full chip erase

- Sector protection:

A hardware method of protecting sectors to prevent any
inadvertent program or erase operations within that
sector. Temporary Sector Unprotect feature allows
code changes in previously locked sectors

 Unlock Bypass Program Command

- Reduces overall programming time when issuing
multiple program command sequence

 Top or bottom boot block configurations available
 Embedded Algorithms

- Embedded Erase algorithm will automatically erase the
entire chip or any combination of designated sectors
and verify the erased sectors

- Embedded Program algorithm automatically writes and
verifies data at specified addresses

 Typical 100,000 program/erase cycles per sector
 20-year data retention at 125°C

- Reliable operation for the life of the system

 CFI (Common Flash Interface) compliant

- Provides device-specific information to the system,
allowing host software to easily reconfigure for different
Flash devices

 Compatible with JEDEC-standards

- Pinout and software compatible with single-power­supply Flash memory standard

- Superior inadvertent write protection



 Ready /

- Provides a hard ware method of detecting completion of

 Erase Suspend/Erase Resume

 Hardware reset pin (

 Package options

Polling and toggle bits

Data

- Provides a software method of detecting completion of
program or erase operations

pin (RY / BY)

BUSY

program or erase operations (not available on 44-pin
SOP)

- Suspends a sector erase operation to read data from,

or program data to, a non-erasing sector, then
resumes the erase operation

RESET

- Hard ware method to reset the device to reading array
data

- 44-pin SOP or 48-pin TSOP (I) or 48-ball TFBGA

)

General Description

The A29L160 is a 16Mbit, 3.0 volt-only Flash memory
organized as 2,097,152 bytes of 8 bits or 1,048,576 words
of 16 bits each. The 8 bits of data appear on I/O0 - I/O7; the
16 bits of data appear on I/O
offered in 48-ball FBGA, 44-pin SOP and 48-Pin TSOP
packages. This device is designed to be programmed in­system with the standard system 3.0 volt VCC supply.
Additional 12.0 volt VPP is not required for in-system write
or erase operations. However, the A29L160 can also be
programmed in standard EPROM programmers.
The A29L160 has the first toggle bit, I/O
whether an Embedded Program or Erase is in progress, or
it is in the Erase Suspend. Besides the I/O6 toggle bit, the
A29L160 has a second toggle bit, I/O
the addressed sector is being selected for erase. The
A29L160 also offers the ability to program in the Erase
Suspend mode. The standard A29L160 offers access times
of 70, 90 and 120ns, allowing high-speed microprocessors
to operate without wait states. To eliminate bus contention

(May, 2004, Version 1.0) 1

0~I/O15. The A29L160 is

6, which indicates

2, to indicate whether

the device has separate chip enable (
(

) and output enable (OE) controls.

WE

The device requires only a single 3.0 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program an d erase
operations.
The A29L160 is entirely software command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register contents
serve as input to an internal state-machine that controls the
erase and programming circuitry. Write cycles also
internally latch addresses and data needed for the
programming and erase operations. Reading data out of
the device is similar to reading from other Flash or EPROM
devices.

Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times

), write enable

CE

AMIC Technology, Corp.

A29L160 Series

the program pulse widths and verifies proper program
margin.
Device erasure occurs by executing the proper erase
command sequence. This initiates the Embedded Erase
algorithm - an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper erase margin. The Unlock Bypass mode
facilitates faster programming times by requiring only two
write cycles to program data instead of four.

The host system can detect whether a program or erase
operation is complete by observing the RY / BY pin, or by
reading the I/O7 (

Polling) and I/O6 (toggle) status bits.

Data

After a program or erase cycle has been completed, the
device is ready to read array data or accept another
command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data
contents of other sectors. The A29L160 is fully erased
when shipped from the factory.

Pin Configurations

SOP  TSOP (I)



RESET

A18
A17

VSS

I/O
I/O
I/O
I/O
I/O

I/O

I/O

I/O

A7
A6
A5
A4
A3
A2
A1
A0

CE

OE

0

8

1

9

2

10

3

11

1
2

3
4
5
6
7
8
9
10
11
12

A29L160

13
14
15
16 29
17
18
19
20
21

22

WE

44

A19

43

A8

42

A9

41

A10

40

A11

39

A12

38

A13

37

A14

36

A15

35

A16

34
33

BYTE
VSS

32

I/O15(A-1)

31

I/O

7

30

I/O

14

28

I/O

6

27

I/O

13

26

I/O

5

25

I/O

12

24

I/O

4

VCC

23

RESET

1
2

A14

3

A13

4

A12

5

A11

6

A10

7

A9

8

A8

9

A19

10

NC

11

WE

12
13

NC

14

NC

15

RY/BY

A18

16
17

A17

18

A7

19

A6

20

A5

21

A4

22

A3

23

A2

24 25

A1

The hardware sector protection feature disables operations
for both program and erase in any combination of the
sectors of memory. This can be achieved via programming
equipment.

The Erase Suspend/Erase Resume feature enables the
user to put erase on hold for any period of time to read data
from, or program data to, any other sector that is not
selected for erasure. True background erase can thus be
achieved.

The hardware

RESET

pin terminates any operation in
progress and resets the internal state machine to reading
array data. The

RESET

pin may be tied to the system

reset circuitry. A system reset would thus also reset the
device, enabling the system microprocessor to read the
boot-up firmware from the Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of time,
the device enters the automatic sleep mode. The system
can also place the device into the standby mode. Power
consumption is greatly reduced in both these modes.

A16A15

48
47

BYTE

46

VSS
I/O15(A-1)

45

I/O

7

44

I/O

14

43

I/O

6

42

I/O

13

41

I/O

5

40

I/O

12

39

I/O

4

38

VCC

A29L160V

37
36
35
34
33 I/O
32 I/O
31
30
29
28
27
26

I/O
I/O
I/O

I/O
I/O
I/O
OE
VSS
CE
A0

11
3
10
2
9
1
8
0

(May, 2004, Version 1.0) 2 AMIC Technology, Corp.

A29L160 Series

Pin Configurations (continued)

TFBGA



TFBGA

Top View, Balls Facing Down

A6 B6 C6 D6 E6 F6

G6

A13 A12 A14 A15 A16 BYTE I/O15(A-1) VSS

A5 B5 C5 D5 E5 F5

A9 A8 A10 A11 I/O

A4 B4 C4 D4 E4 F4

WE RESET NC A19 I/O

A3 B3 C3 D3 E3 F3

RY/BY NC A18 NC I/O

A2 B2 C2 D2 E2 F2

A7 A17 A6 A5 I/O

A1 B1 C1 D1 E1 F1

7

5

2

0

I/O

I/O

I/O

I/O

14

12

10

8

G5

I/O

13

G4

VCC I/O

G3

I/O

11

G2

I/O

9

G1

A3 A4 A2 A1 A0 CE OE VSS

I/O

I/O

I/O

H6

H5

6

H4

4

H3

3

H2

1

H1

(May, 2004, Version 1.0) 3 AMIC Technology, Corp.

A29L160 Series

Block Diagram

VCC
VSS

RESET

BYTE

A0-A19

WE

CE
OE

RY/BY

State

Control

Command

Register

VCC Detector

PGM Voltage

Generator

Timer

Sector Switches

Erase Voltage

Generator

STB

Chip Enable

Output Enable

Logic

Y-Decoder

X-decoder

Address Latch

STB

0

- I/O

I/O

15

Input/Output

Buffers

Data Latch

Y-Gating

Cell Matrix

(A-1)

Pin Descriptions

A0 - A19 Address Inputs

I/O0 - I/O14 Data Inputs/Outputs

I/O15 (A-1)

RESET

Pin No. Description

I/O15

Data Input/Output, Word Mode

A-1 LSB Address Input, Byte Mode

CE

WE

OE

BYTE

RY/BY

Chip Enable
Write Enable
Output Enable
Hardware Reset (N/A A29L1601)
Selects Byte Mode or Word Mode

Ready/

BUSY

- Output

VSS Ground
VCC Power Supply

NC Pin not connected internally

(May, 2004, Version 1.0) 4 AMIC Technology, Corp.

A29L160 Series

Absolute Maximum Ratings*

Storage Temperature Plastic Packages . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to + 150°C

Ambient Temperature with Power Applied . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to + 125°C

Voltage with Respect to Ground

VCC (Note 1) . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.0V

A9,

OE

&

RESET

(Note 2) . . . . . . . . . . . . -0.5 to +12.5V

All other pins (Note 1) . . . . . . . . . . . . -0.5V to VCC + 0.5V

Output Short Circuit Current (Note 3) . . . . . . . . . 200mA

Notes:

1. Minimum DC voltage on input or I/O pins is -0.5V.

During voltage transitions, input or I/O pins may
undershoot VSS to -2.0V for periods of up to 20ns.
Maximum DC voltage on input and I/O pins is VCC
+0.5V. During voltage transitions, input or I/O pins may
overshoot to VCC +2.0V for periods up to 20ns.

2. Minimum DC input voltage on A9,

-0.5V. During voltage transitions, A9,

OE

OE

and

RESET

and

is

RESET

may overshoot VSS to -2.0V for periods of up to 20ns.
Maximum DC input voltage on A9 is +12.5V which may
overshoot to 14.0V for periods up to 20ns.

3. No more than one output is shorted at a time. Duration

of the short circuit should not be greater than one
second.

Device Bus Operations

This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location. The
register is composed of latches that store the commands,
along with the address and data information needed to

*Comments

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended
periods may affect device reliability.

Operating Ranges

Commercial (C) Devices

Ambient Temperature (T

VCC Supply Voltages

VCC for all devices . . . . . . . . . . . . . . . . . . +2.7V to +3.6V

Operating ranges define those limits between which the
functionally of the device is guaranteed.

execute the command. The contents of the register serve
as inputs to the internal state machine. The state machine
outputs dictate the function of the device. The appropriate
device bus operations table lists the inputs and control
levels required, and the resulting output. The following
subsections describe each of these operations in further
detail.

A) . . . . . . . . . . . . . . 0°C to +70°C

Table 1. A29L160 Device Bus Operations

CE

OE

WE

RESET

A0 – A19

(Note 1)

I/O0 - I/O7

BYTE

Read L L H H AIN DOUT DOUT

I/O

=VIH

8 - I/O15 Operation

BYTE

I/O

8~I/O4=High-Z

I/O

15=A-1

=VIL

Write L H L H AIN DIN DIN High-Z
CMOS Standby

VCC ± 0.3 V

X X

VCC ± 0.3 V

X High-Z High-Z High-Z
Output Disable L H H H X High-Z High-Z High-Z
Hardware Reset X X X L X High-Z High-Z High-Z
Sector Protect

(See Note 2)
Sector Unprotect

(See Note 2)
Temporary Sector

Unprotect

L H L V

L H L V

X X X V

ID

ID

ID AIN DIN DIN X

Sector Address,

A6=L, A1=H, A0=L

Sector Address,

A6=H, A1=H, A0=L

DIN X X

IN X X

D

Legend:
L = Logic Low = V

IL, H = Logic High = VIH, VID = 12.0 ± 0 .5V, X = Don 't Care, DIN = Data In, DOUT = Data Out , AIN = Address In

Notes:

1. Addresses are A19:A0 in word mode (

BYTE

=VIH), A19: A

in byte mode (

-1

BYTE

=VIL).

2. See the “Sector Protection/Unprotection” section and Temporary Sector Unprotect for more information.

(May, 2004, Version 1.0) 5 AMIC Technology, Corp.

A29L160 Series

Word/Byte Configuration

The
operate in the byte or word configuration. If the

is set at logic ”1”, the device is in word configuration, I/O

0 are active and controlled by

I/O
If the

configuration, and only I/O
by CE and OE. I/O8-I/O14 are tri-stated, and I/O15 pin is

used as an input for the LSB(A-1) address function.

pin determines whether the I/O pins I/O15-I/O0

BYTE

and OE.

CE

pin is set at logic “0”, the device is in byte

BYTE

0-I/O7 are active and controlled

BYTE

pin

15-

Requirements for Reading Array Data

To read array data from the outputs, the system must drive
the
selects the device.

array data to the output pins.
the time during read operation. The

and OE pins to VIL. CE is the power control and

CE

is the output control and gates

OE

should remain at VIH all

WE

pin determines

BYTE

whether the device outputs array data in words and bytes.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content
occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid addresses on
the device address inputs produce valid data on the device
data outputs. The device remains enabled for read access
until the command register contents are altered.
See "Reading Array Data" for more information. Refer to
the AC Read Operations table for timing specifications and
to the Read Operations Timings diagram for the timing
waveforms, l

CC1 in the DC Characteristics table represents

the active current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which
includes programming data to the device and erasing

sectors of memory), the system must drive
to V

IL, and

to VIH. For progra m operations, the

OE

pin determines whether the device accepts program data in
bytes or words, Refer to “Word/Byte Configuration” for
more information. The device features an Unlock Bypass
mode to facilitate faster programming. Once the device
enters the Unlock Bypass mode, only two write cycles are
required to program a word or byte, instead of four. The “
Word / Byte Program Command Sequence” section has
details on programming data to the device using both
standard and Unlock Bypass command sequence. An
erase operation can erase one sector, multiple sectors, or
the entire device. The Sector Address Tables indicate the
address range that each sector occupies. A "sector
address" consists of the address inputs required to
uniquely select a sector. See the "Command Definitions"
section for details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can
then read autoselect codes from the internal register (which
is separate from the memory array) on I/O

7 - I/O0. Standard

read cycle timings apply in this mode. Refer to the
"Autoselect Mode" and "Autoselect Command Sequence"
sections for more information.
ICC2 in the DC Characteristics table represents the active
current specification for the write mode. The "AC

WE

and CE

BYTE

Characteristics" section contains timing specification tables
and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may
check the status of the operation by reading the status bits
on I/O7 - I/O0. Standard read cycle timings and ICC read
specifications apply. Refer to "Write Operation Status" for
more information, and to each AC Characteristics section
for timing diagrams.

Standby Mode

When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs
are placed in the high impedance state, independent of the

input.

OE

The device enters the CMOS standby mode when the
&

RESET

is a more restricted voltage range than V

RESET

pins are both held at VCC ± 0.3V. (Note that this

IH.) If

are held at VIH, but not within VCC ± 0.3V, the

CE

CE

and

device will be in the standby mode, but the standby current
will be greater. The device requires the standard access
time (tCE) before it is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
ICC3 and ICC4 in the DC Characteristics tables represent the
standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for tACC +30ns. The

automatic sleep mode is independent of the

control signals. Standard address access timings

OE

,WEand

CE

provide new data when addresses are changed. While in
sleep mode, output data is latched and always available to
the system. I

CC4 in the DC Characteristics table represents

the automatic sleep mode current specification.

Output Disable Mode

When the OE input is at VIH, output from the device is
disabled. The output pins are placed in the high impeda nce
state.

RESET

The
the device to reading array data. When the system drives
the
immediately terminates any operation in progress, tristates
all data output pins, and ignores all read/write attempts for
the duration of the
the internal state machine to reading array data. The

operation that was interrupted should be reinitiated once
the device is ready to accept another command sequence,
to ensure data integrity.

Current is reduced for the duration of the
When
CMOS standby current (ICC4 ). If

not within VSS ± 0.3V, the standby current will be greater.

: Hardware Reset Pin

RESET

RESET

pin provides a hardware method of resetting

pin low for at least a period of tRP, the device

RESET

is held at VSS ± 0.3V, the device draws

RESET

pulse. The device also resets

pulse.

RESET

RESET

is held at VIL but

(May, 2004, Version 1.0) 6 AMIC Technology, Corp.

A29L160 Series

The

RESET

system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
If

RESET

the RY/
operation is complete, which requires a time tREADY (during
Embedded Algorithms). The system can thus monitor

pin may be tied to the system reset circuitry. A

is asserted during a program or erase operation,

pin remains a “0” (busy) until the internal reset

BY

RY/
complete. If
operation is not executing (RY/
operation is completed within a time of tREADY (not duri ng
Embedded Algorithms). The system can read data tRH after
the
Refer to the AC Characteristics tables for
parameters and diagram.

to determine whether the reset operation is

BY

is asserted when a program or erase

pin is “1”), the reset

BY

RESET

RESET

pin return to VIH.

Table 2. A29L160 Top Boot Block Sector Address Table

Sector A19 A18 A17 A16 A15 A14 A13 A12

SA0 0 0 0 0 0 X X X 64/32 000000 - 00FFFF 00000 - 07FFF
SA1 0 0 0 0 1 X X X 64/32 010000 - 01FFFF 08000 - 0FFFF
SA2 0 0 0 1 0 X X X 64/32 020000 - 02FFFF 10000 - 17FFF
SA3 0 0 0 1 1 X X X 64/32 030000 - 03FFFF 18000 - 1FFFF
SA4 0 0 1 0 0 X X X 64/32 040000 - 04FFFF 20000 - 27FFF
SA5 0 0 1 0 1 X X X 64/32 050000 - 05FFFF 28000 - 2FFFF
SA6 0 0 1 1 0 X X X 64/32 060000 - 06FFFF 30000 - 37FFF
SA7 0 0 1 1 1 X X X 64/32 070000 - 07FFFF 38000 - 3FFFF
SA8 0 1 0 0 0 X X X 64/32 080000 - 08FFFF 40000 - 47FFF

SA9 0 1 0 0 1 X X X 64/32 090000 - 09FFFF 48000 - 4FFFF
SA10 0 1 0 1 0 X X X 64/32 0A0000 - 0AFFFF 50000 - 57FFF
SA11 0 1 0 1 1 X X X 64/32 0B0000 - 0BFFFF 58000 - 5FFFF
SA12 0 1 1 0 0 X X X 64/32 0C0000 - 0CFFFF 60000 - 67FFF
SA13 0 1 1 0 1 X X X 64/32 0D0000 - 0DFFFF 68000 - 6FFFF
SA14 0 1 1 1 0 X X X 64/32 0E0000 - 0EFFFF 70000 - 77FFF
SA15 0 1 1 1 1 X X X 64/32 0F0000 - 0FFFFF 78000 - 7FFFF
SA16 1 0 0 0 0 X X X 64/32 100000 - 10FFFF 80000 - 87FFF
SA17 1 0 0 0 1 X X X 64/32 110000 - 11FFFF 88000 - 8FFFF
SA18 1 0 0 1 0 X X X 64/32 120000 - 12FFFF 90000 - 97FFF
SA19 1 0 0 1 1 X X X 64/32 130000 - 13FFFF 98000 - 9FFFF
SA20 1 0 1 0 0 X X X 64/32 140000 - 14FFFF A0000 - A7FFF
SA21 1 0 1 0 1 X X X 64/32 150000 - 15FFFF A8000 - AFFFF
SA22 1 0 1 1 0 X X X 64/32 160000 - 16FFFF B0000 - B7FFF
SA23 1 0 1 1 1 X X X 64/32 170000 - 17FFFF B8000 - BFFFF
SA24 1 1 0 0 0 X X X 64/32 180000 - 18FFFF C0000 - C7FFF
SA25 1 1 0 0 1 X X X 64/32 190000 - 19FFFF C8000 - CFFFF
SA26 1 1 0 1 0 X X X 64/32 1A0000 - 1AFFFF D0000 - D7FFF
SA27 1 1 0 1 1 X X X 64/32 1B0000 - 1BFFFF D8000 - DFFFF
SA28 1 1 1 0 0 X X X 64/32 1C0000 - 1CFFFF E0000 - E7FFF
SA29 1 1 1 0 1 X X X 64/32 1D0000 - 1DFFFF E8000 - EFFFF
SA30 1 1 1 1 0 X X X 64/32 1E0000 - 1EFFFF F0000 - F7FFF
SA31 1 1 1 1 1 0 X X 32/16 1F0000 - 1F7FFF F8000 - FBFFF
SA32 1 1 1 1 1 1 0 0 8/4 1F8000 - 1F9FFF FC000 - FCFFF
SA33 1 1 1 1 1 1 0 1 8/4 1FA000 - 1FBFFF FD000 - FDFFF
SA34 1 1 1 1 1 1 1 X 16/8 1FC000 - 1FFFFF FE000 - FFFFF

Sector Size

(Kbytes/
Kwords)

Address Range (in hexadecimal)

Byte Mode

(x8)

Word Mode

(x16)

RESET

Note:
Address range is A19 : A

(May, 2004, Version 1.0) 7 AMIC Technology, Corp.

in byte mode and A19 : A0 in word mode. See “Word/Byte Configuration” section.

-1

A29L160 Series

Table 3. A29L160 Bottom Boot Block Sector Address Table

Sector A19 A18 A17 A16 A15 A14 A13 A12

Sector Size

(Kbytes/
Kwords)

Address Range (in hexadecimal)

Byte Mode

(x8)

Word Mode

(x16)

SA0 0 0 0 0 0 0 0 X 16/8 000000 - 003FFF 00000 - 01FFF

SA1 0 0 0 0 0 0 1 0 8/4 004000 - 005FFF 02000 - 02FFF

SA2 0 0 0 0 0 0 1 1 8/4 006000 - 007FFF 03000 - 03FFF

SA3 0 0 0 0 0 1 X X 32/16 008000 - 00FFFF 04000 - 07FFF

SA4 0 0 0 0 1 X X X 64/32 010000 - 01FFFF 08000 - 0FFFF

SA5 0 0 0 1 0 X X X 64/32 020000 - 02FFFF 10000 - 17FFF

SA6 0 0 0 1 1 X X X 64/32 030000 - 03FFFF 18000 - 1FFFF

SA7 0 0 1 0 0 X X X 64/32 040000 - 04FFFF 20000 - 27FFF

SA8 0 0 1 0 1 X X X 64/32 050000 - 05FFFF 28000 - 2FFFF

SA9 0 0 1 1 0 X X X 64/32 060000 - 06FFFF 30000 - 37FFF
SA10 0 0 1 1 1 X X X 64/32 070000 - 07FFFF 38000 - 3FFFF
SA11 0 1 0 0 0 X X X 64/32 080000 - 08FFFF 40000 - 47FFF
SA12 0 1 0 0 1 X X X 64/32 090000 - 09FFFF 48000 - 4FFFF
SA13 0 1 0 1 0 X X X 64/32 0A0000 - 0AFFFF 50000 - 57FFF
SA14 0 1 0 1 1 X X X 64/32 0B0000 - 0BFFFF 58000 - 5FFFF
SA15 0 1 1 0 0 X X X 64/32 0C0000 - 0CFFFF 60000 - 67FFF
SA16 0 1 1 0 1 X X X 64/32 0D0000 - 0DFFFF 68000 - 6FFFF
SA17 0 1 1 1 0 X X X 64/32 0E0000 - 0EFFFF 70000 - 77FFF
SA18 0 1 1 1 1 X X X 64/32 0F0000 - 0FFFFF 78000 - 7FFFF
SA19 1 0 0 0 0 X X X 64/32 100000 - 10FFFF 80000 - 87FFF
SA20 1 0 0 0 1 X X X 64/32 110000 - 11FFFF 88000 - 8FFFF
SA21 1 0 0 1 0 X X X 64/32 120000 - 12FFFF 90000 - 97FFF
SA22 1 0 0 1 1 X X X 64/32 130000 - 13FFFF 98000 - 9FFFF
SA23 1 0 1 0 0 X X X 64/32 140000 - 14FFFF A0000 - A7FFF
SA24 1 0 1 0 1 X X X 64/32 150000 - 15FFFF A8000 - AFFFF
SA25 1 0 1 1 0 X X X 64/32 160000 - 16FFFF B0000 – B7FFF
SA26 1 0 1 1 1 X X X 64/32 170000 - 17FFFF B8000 - BFFFF
SA27 1 1 0 0 0 X X X 64/32 180000 - 18FFFF C0000 - C7FFF
SA28 1 1 0 0 1 X X X 64/32 190000 - 19FFFF C8000 - CFFFF
SA29 1 1 0 1 0 X X X 64/32 1A0000 - 1AFFFF D0000 - D7FFF
SA30 1 1 0 1 1 X X X 64/32 1B0000 - 1BFFFF D8000 - DFFFF
SA31 1 1 1 0 0 X X X 64/32 1C0000 - 1CFFFF E0000 - E7FFF
SA32 1 1 1 0 1 X X X 64/32 1D0000 - 1DFFFF E8000 - EFFFF
SA33 1 1 1 1 0 X X X 64/32 1E0000 - 1EFFFF F0000 - F7FFF
SA34 1 1 1 1 1 X X X 64/32 1F0000 - 1FFFFF F8000 - FFFFF

Note:
Address range is A19 : A

in byte mode and A19 : A0 in word mode. See “Word/Byte Configuration” section.

-1

(May, 2004, Version 1.0) 8 AMIC Technology, Corp.

A29L160 Series

Autoselect Mode

The autoselect mode provides manufacturer and device
identification, and sector protection verification, through
identifier codes output on I/O7 - I/O0. This mode is primarily
intended for programming equipment to automatically
match a device to be programmed with its corresponding
programming algorithm. However, the autoselect codes
can also be accessed in-system through the command
register.
When using programming equipment, the autoselect mode
requires V
pins A6, A1, and A0 must be as shown in Autoselect
Codes (High Voltage Method) table. In addition, when

ID (11.5V to 12.5 V) on address pin A9. Address

verifying sector protection, the sector address must appear
on the appropriate highest order address bits. Refer to the
corresponding Sector Address Tables. The Command
Definitions table shows the remaining address bits that are
don't care. When all necessary bits have been set as
required, the programming equipment may then read the
corresponding identifier code on I/O7 - I/O0.To access the
autoselect codes in-system, the host system can issue the
autoselect command via the command register, as shown
in the Command Definitions table. This method does not
require VID. See "Command Definitions" for details on using
the autoselect mode.

Table 4. A29L160 Autoselect Codes (High Voltage Method)

Description

Mode

CE

I/O

8

to

15

A19

A11

OE

WE

to

A12

A9 A8

to

A10

to

A7

A6 A5

to

A2

A1 A0 I/O

Manufacturer ID: AMIC L L H X X VID X L X L L X 37h

Word B3h A8h Device ID:
A29L160
(Top Boot Block)

Byte

L L H X X V

ID XLXL H

X A8h

I/O

to

I/O

7

0

Device ID:
A29L160
(Bottom Boot Block)

Word B3h 29h

L L H X X V

Byte

ID XLXL H

X 29h

Continuation ID L L H X X VID X L X H H X 7Fh

01h

(protected)

00h

(unprotected)

Sector Protection
Verification

X

L L H SA X VID XLXH L

X

L=Logic Low= VIL, H=Logic High=VIH, SA=Sector Address, X=Don’t Care.
Note: The autoselect codes may also be accessed in-system via command sequences.

(May, 2004, Version 1.0) 9 AMIC Technology, Corp.

A29L160 Series

Sector Protection/Unprotection

The hardware sector protection feature disables both
program and erase operations in any sector. The hardware
sector unprotection feature re-enables both program and
erase operations in previously protected sectors.
It is possible to determine whether a sector is protected or
unprotected. See “Autoselect Mode” for details.
Sector protection / unprotection can be implemented via
two methods. The primary method requires VID on the

RESET

pin only, and can be implemented either in-system
or via programming equipment. Figure 2 shows the
algorithm and the Sector Protect / Unprotect Timing
Diagram illustrates the timing waveforms for this feature.
This method uses standard microprocessor bus cycle
timing. For sector unprotect, all unprotected sectors must
first be protected prior to the first sector unprotect write
cycle. The alternate method must be implemented using
programming equipment. The procedure requires a high
voltage (V

ID) on address pin A9 and the control pins.

The device is shipped with all sectors unprotected.
It is possible to determine whether a sector is protected or
unprotected. See "Autoselect Mode" for details.

Hardware Data Protection

The requirement of command unlocking sequence for
programming or erasing provides data protection against
inadvertent writes (refer to the Command Definitions table).
In addition, the following hardware data protection
measures prevent accidental erasure or programming,
which might otherwise be caused by spurious s ystem level
signals during VCC power-up transitions, or from system
noise. The device is powered up to read array data to avoid
accidentally writing data to the array.

Temporary Sector Unprotect

This feature allows temporary unprotection of previous
protected sectors to change data in-system. The Sector

Unprotect mode is activated by setting the
V

ID. During this mode, formerly protected sectors can be

RESET

programmed or erased by selecting the sector addresses.
Once V

ID is removed from the

RESET

previously protected sectors are protected again. Figure 1
shows the algorithm, and the Temporary Sector Unprotect
diagram shows the timing waveforms, for this feature.

START

RESET = V

(Note 1)

Perform Erase or

Program Operations

RESET = V

ID

IH

pin to

pin, all the

Write Pulse "Glitch" Protection

Noise pulses of less than 5ns (typical) on OE, CE or WE
do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE=VIL,

= VIH or WE = VIH. To initiate a write cycle, CE and

CE

must be a logical zero while OE is a logical one.

WE

Power-Up Write Inhibit

If

= CE = VIL and OE = VIH during power up, the

WE

device does not accept commands on the rising edge of

. The internal state machine is automatically reset to

WE

reading array data on the initial power-up.

Temporary Sector

Unprotect

Completed (Note 2)

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once again.

Figure 1. Temporary Sector Unprotect Operation

(May, 2004, Version 1.0) 10 AMIC Technology, Corp.

A29L160 Series

Temporary Sector

Unprotect Mode

Increment

PLSCNT

No

PLSCNT

=25?

Yes

Device failed

START

PLSCNT=1

RESET=V

Wait 1 us

No

First Write

Cycle=60h?

Set up sector

address

Sector Protec:

Write 60h to sector

address with A6=0,

A1=1, A0=0

Wait 150 us

Verify Sector

Protect: Write 40h

to sector address
with A6=0, A1=1,

Read from

sector address

with A6=0,

A1=1, A0=0

No

Data=01h?

Protect another

sector?

Remove V

from RESET

A0=0

Yes

No

Yes

START

Protect all sectors:

The indicated portion of

the sector protect

algorithm must be

ID

Reset

PLSCNT=1

Yes

ID

performed for all

unprotected sectors prior

to issuing the first sector

unprotect address

Increment

PLSCNT

No

PLSCNT=

1000?

Yes

Device failed

PLSCNT=1

RESET=V

Wait 1 us

No

First Write

Cycle=60h?

All sectors
protected?

Set up first sector

address

Sector Unprotect:
Write 60h to sector
address with A6=1,

A1=1, A0=0

Wait 15 ms

Verify Sector

Unprotect : Write

40h to sector

address with A6=1,

A1=1, A0=0

Read from sector

address with A6=1,

A1=1, A0=0

No

Data=00h?

Last sector

verified?

Yes

Yes

Yes

ID

No

Temporary Sector

Unprotect Mode

Set up

next sector

address

No

Sector Protect

Algorithm

Write reset

command

Sector Protect

complete

Sector Unprotect

Algorithm

Sector Unprotect

Yes

Remove V
from RESET

Write reset

Command

complete

ID

Figure 2. In-System Sector Protect/Unprotect Algorithms

(May, 2004, Version 1.0) 11 AMIC Technology, Corp.

A29L160 Series

Common Flash Memory Interface (CFI)

The Common Flash Interface (CFI) specification outlines
device and host system software interrogation handshake,
which allows specific vendor-specified software algorithms
to be used for entire families of devices. Software suppor t
can then be device-independent, JEDEC ID-independent,
and forward- and backward-compatible for the specified
flash device families. Flash vendors can standardize their
existing interface for long-term compatibility.
This device enters the CFI Query mode when the system
writes the CFI Query command, 98h, to address 55h in
word mode (or address AAh in byte mode), any time the

device is ready to read array data. The system can read
CFI information at the addresses given in Table 5-8. In
word mode, the upper address bits (A7-MSB) must be all
zeros. To terminate reading CFI data, the system must
write the reset command.
The system can also write the CFI query command when
the device is in the autoselect mode. The device enters the
CFI query mode, and the system can read CFI data at the
addresses given in Table 5-8. The system must write the
reset command to return the device to the autoselect mode.

Table 5. CFI Query Identification String

Addresses

(Word Mode)

10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah

Addresses

(Byte Mode)

20h
22h
24h
26h
28h

2Ah
2Ch
2Eh

30h

32h

34h

Data Description

0051h
0052h
0059h
0002h
0000h
0040h
0000h
0000h
0000h
0000h
0000h

Query Unique ASCII string “QRY”

Primary OEM Command Set

Address for Primary Extended Table

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

Table 6 System Interface String

Addresses

(Word Mode)

1Bh 36h 0027h VCC Min. (write/erase)

Addresses

(Byte Mode)

Data Description

I/O7- I/O4 : volt, I/O3- I/O0: 100 millivolt

1Ch 38h 0036h VCC Max. (write/erase)

I/O7- I/O4: volt, I/O3- I/O0: 100 millivolt

1Dh 3Ah 0000h Vpp Min. voltage (00h = no Vpp pin present)
1Eh 3Ch 0000h Vpp Max. voltage (00h = no Vpp pin present)
1Fh 3Eh 0004h
20h 40h 0000h
21h 42h 000Ah Typical timeout per individual block erase 2N ms
22h 44h 0000h Typical timeout for full chip erase 2N ms (00h = not supported)
23h 46h 0005h Max. timeout for byte/word write 2N times typical
24h 48h 0000h Max. timeout for buffer write 2N times typical
25h 4Ah 0004h Max. timeout per individual block erase 2N times typical
26h 4Ch 0000h Max. timeout for full chip erase 2N times typical (00h = not supported)

Typical timeout per single byte/word write 2
Typical timeout for Min. size buffer write 2

N

µs

N

µs (00h = not supported)

(May, 2004, Version 1.0) 12 AMIC Technology, Corp.

A29L160 Series

Table 7 Device Geometry Definition

Addresses

(Word Mode)

27h 4Eh 0015h Device Size = 2N byte
28h
29h
2Ah
2Bh
2Ch 58h 0004h Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h

3Ah
3BH
3Ch

Addresses

(Byte Mode)

50h
52h
54h
56h

5Ah
5Ch
5Eh

60h
62h
64h
66h

68h
6Ah
6Ch
6Eh

40h

72h

74h

76h

78h

Data Description

0002h
0000h
0000h
0000h

0000h
0000h
0040h
0000h
0001h
0000h
0020h
0000h
0000h
0000h
0080h

0000h
001Eh
0000h
0000h
0001h

Flash Device Interface description
Max. number of byte in multi-byte write = 2N

(00h = not supported)

Erase Block Region 1 Information
(refer to the CFI specification)

Erase Block Region 2 Information

Erase Block Region 3 Information

Erase Block Region 4 Information

Table 8 Primary Vendor-Specific Extended Query

Addresses

(Word Mode)

40h
41h
42h
43h 86h 0031h Major version number, ASCII
44h 88h 0030h Minor version number, ASCII

45h 8Ah 0000h

46h 8Ch 0002h

47h 8Eh 0001h

48h 90h 0001h

49h 92h 0004h

4Ah 94h 0000h

48h 96h 0000h

4Ch 98h 0000h

Addresses

(Byte Mode)

80h
82h
84h

Data Description

0050h
0052h
0049h

Query-unique ASCII string “PRI”

Address Sensitive Unlock
0 = Required, 1 = Not Required
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29L160 mode
Simultaneous Operation
00 = Not Supported, 01 = Supported
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

(May, 2004, Version 1.0) 13 AMIC Technology, Corp.

A29L160 Series

Command Definitions

Writing specific address and data commands or sequences
into the command register initiates device operations. T he
Command Definitions table defines the valid register
command sequences. Writing incorrect address and data
values or writing them in the improper sequence resets the
device to reading array data.

All addresses are latched on the falling edge of WE or

, whichever happens later. All data is latched on the

CE

rising edge of WE or CE, whichever happens first. Refer
to the appropriate timing diagrams in the "AC

Characteristics" section.

Reading Array Data

The device is automatically set to reading array data after
device power-up. No commands are required to retrieve
data. The device is also ready to read array data after
completing an Embedded Program or Embedded Erase
algorithm. After the device accepts an Erase Suspend
command, the device enters the Erase Suspend mode. The
system can read array data using the standard read
timings, except that if it reads at an address within erase­suspended sectors, the device outputs status data. After
completing a programming operation in the Erase Suspend
mode, the system may once again read array data with the
same exception. See "Erase Suspend/Erase Resume
Commands" for more information on this mode.
The system must issue the reset command to re-enable the
device for reading array data if I/O5 goes high, or while in
the autoselect mode. See the "Reset Command" section,
next.
See also "Requirements for Reading Array Data" in the
"Device Bus Operations" section for more information. The
Read Operations table provides the read parameters, and
Read Operation Timings diagram shows the timing
diagram.

Reset Command

Writing the reset command to the device resets the device
to reading array data. Address bits are don't care for this
command. The reset command may be written between the
sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ignores
reset commands until the operation is complete.
The reset command may be written between the sequence
cycles in a program command sequence before
programming begins. This resets the device to reading
array data (also applies to programming in Erase Suspend
mode). Once programming begins, however, the device
ignores reset commands until the operation is complete.
The reset command may be written between the sequence
cycles in an autoselect command sequence. Once in the
autoselect mode, the reset command must be written to
return to reading array data (also applies to autoselect
during Erase Suspend).
If I/O5 goes high during a program or erase operation,
writing the reset command returns the device to reading
array data (also applies during Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host system
to access the manufacturer and devices codes, and
determine whether or not a sector is protected. The
Command Definitions table shows the address and data
requirements. This method is an alternative to that shown in
the Autoselect Codes (High Voltage Method) table, which is
intended for PROM programmers and requires VID on
address bit A9.
The autoselect command sequence is initiated by writing
two unlock cycles, followed by the autoselect command. The
device then enters the autoselect mode, and the system
may read at any address any number of times, without
initiating another command sequence.
A read cycle at address XX00h retrieves the manufacturer
code and another read cycle at XX11h retrieves the
continuation code. A read cycle at address XX01h returns
the device code. A read cycle containing a sector address
(SA) and the address 02h in returns 01h if that sector is
protected, or 00h if it is unprotected. Refer to the Sector
Address tables for valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.

Word/Byte Program Command Sequence

The system may program the device by word or byte,
depending on the state of the

four-bus-cycle operation. The program command sequence
is initiated by writing two unlock write cycles, followed by the
program set-up command. The program address and data
are written next, which in turn initiate the Embedded
Program algorithm. The system is not required to provide
further controls or timings. The device automatically
provides internally generated program pulses and verify the
programmed cell margin. Table 9 shows the address and
data requirements for the byte program command
sequence.
When the Embedded Program algorithm is complete, the
device then returns to reading array data and addresses are
longer latched. The system can determine the status of the

program operation by using I/O
“White Operation Status” for information on these status
bits.
Any commands written to the device during the Embedded
Program Algorithm are ignored. Note that a hardware reset
immediately terminates the programming operation. The
Byte Program command sequence should be reinitiated
once the device has reset to reading array data, to ensure
data integrity.
Programming is allowed in any sequence and across sector
boundaries. A bit cannot be programmed from a “0” back to
a “1”. Attempting to do so may halt the operation and set

I/O5 to “1”, or cause the
the operation was successful. However, a succeeding read
will show that the data is still “0”. Only erase operations can

convert a “0” to a “1”.

Data

pin. Programming is a

BYTE

7, I/O6, or RY/

Polling algorithm to indicate

BY

. See

(May, 2004, Version 1.0) 14 AMIC Technology, Corp.

A29L160 Series

START

Write Program

Command

Sequence

Embedded

Program

algorithm in

progress

Data Poll

from System

Verify Data ?

No

Yes

Increment Address

No

Last Address ?

Yes

Programming

Completed

Note : See the appropriate Command Definitions table for
program command sequence.

Figure 3. Program Operation

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to program
bytes or words to the device faster than using the standard
program command sequence. The unlock bypass
command sequence is initiated by first writing two unlock
cycles. This is followed by a third write cycle containing the
unlock bypass command, 20h. The device then enters the
unlock bypass mode. A two-cycle unlock bypass program
command sequence is all that is required to program in this
mode. The first cycle in this sequence contains the unlock
bypass program command, A0h; the second cycle contains
the program address and data. Additional data is
programmed in the same manner. This mode dispenses
with the initial two unlock cycles required in the standard
program command sequence, resulting in faster total
programming time. Table 9 shows the requirements for the
command sequence.
During the unlock bypass mode, only the Unlock Bypass
Program and Unlock Bypass Reset commands are valid. To
exit the unlock bypass mode, the system must issue the
two-cycle unlock bypass reset command sequence. The
first cycle must contain the data 90h; the second cycle the

data 00h. Addresses are don’t care for both cycle. The
device returns to reading array data.
Figure 3 illustrates the algorithm for the program operation.
See the Erase/Program Operations in “AC Characteristics”
for parameters, and to Program Operation Timings for
timing diagrams.

Chip Erase Command Sequence

Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which
in turn invokes the Embedded Erase algorithm. The device
does not require the system to preprogram prior to erase.
The Embedded Erase algorithm automatically preprograms
and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to
provide any controls or timings during these operations. The
Command Definitions table shows the address and data
requirements for the chip erase command sequence.
Any commands written to the chip during the Embedded
Erase algorithm are ignored. The system can determine the
status of the erase operation by using I/O7, I/O6, or I/O2.
See "Write Operation Status" for information on these status
bits. When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are no
longer latched.
Figure 4 illustrates the algorithm for the erase operation.
See the Erase/Program Operations tables in "AC
Characteristics" for parameters, and to the Chip/Sector
Erase Operation Timings for timing waveforms.

Sector Erase Command Sequence

Sector erase is a six-bus-cycle operation. The sector eras e
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the address of the sector to be
erased, and the sector erase command. The Command
Definitions table shows the address and data requirements
for the sector erase command sequence.
The device does not require the system to preprogram the
memory prior to erase. The Embedded Erase algorithm
automatically programs and verifies the sector for an all
zero data pattern prior to electrical erase. The system is not
required to provide any controls or timings during these
operations.
After the command sequence is written, a sector erase
time-out of 50µs begins. During the time-out period,
additional sector addresses and sector erase commands
may be written. Loading the sector erase buffer may be
done in any sequence, and the number of sectors ma y be
from one sector to all sectors. The time between these
additional cycles must be less than 50µs, otherwise the last
address and command might not be accepted, and erasure
may begin. It is recommended that processor interrupts be
disabled during this time to ensure all commands are
accepted. The interrupts can be re-enabled after the last
Sector Erase command is written. If the time between
additional sector erase commands can be assumed to be
less than 50µs, the system need not monitor I/O3. Any
command other than Sector Erase or Erase Suspend during
the time-out period resets the device to reading array data.
The system must rewrite the command sequence and any
additional sector addresses and commands.

(May, 2004, Version 1.0) 15 AMIC Technology, Corp.

A29L160 Series

The system can monitor I/O3 to determine if the sector
erase timer has timed out. (See the " I/O

3: Sector Erase

Timer" section.) The time-out begins from the rising edge of
the final WE pulse in the command sequence.

Once the sector erase operation has begun, only the Erase
Suspend command is valid. All other commands are
ignored.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are no
longer latched. The system can determine the status of the
erase operation by using I/O

7, I/O6, or I/O2. Refer to "Write

Operation Status" for information on these status bits.
4 illustrates the algorithm for the erase operation. Refer to
the Erase/Program Operations tables in the "AC
Characteristics" section for parameters, and to the Sector
Erase Operations Timing diagram for timing waveforms.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to
interrupt a sector erase operation and then read data from,
or program data to, any sector not selected for erasure.
This command is valid only during the sector erase
operation, including the 50µs time-out period during the
sector erase command sequence. The Erase Suspend
command is ignored if written during the chip erase
operation or Embedded Program algorithm. Writing the
Erase Suspend command during the Sector Erase time-out
immediately terminates the time-out period and suspends
the erase operation. Addresses are "don't cares" when
writing the Erase Suspend command.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum of
20µs to suspend the erase operation. However, when the
Erase Suspend command is written during the sector erase
time-out, the device immediately terminates the time-out
period and suspends the erase operation.
After the erase operation has been suspended, the system
can read array data from or program data to any sector not
selected for erasure. (The device "erase suspends" all
sectors selected for erasure.) Normal read and write
timings and command definitions apply. Reading at any
address within erase-suspended sectors produces status
data on I/O
I/O

2 together, to determine if a sector is actively erasing or

is erase-suspended. See "Write Operation Status" for
information on these status bits.
After an erase-suspended program operation is complete,
the system can once again read array data within non­suspended sectors. The system can determine the status of
the program operation using the I/O7 or I/O6 status bits, just
as in the standard program operation. See "Write Operation
Status" for more information.

7 - I/O0. The system can use I/O7, or I/O6 and

The system may also write the autoselect command
sequence when the device is in the Erase Suspend m ode.
The device allows reading autoselect codes even at
addresses within erasing sectors, since the codes are not
stored in the memory array. When the device exits the
autoselect mode, the device reverts to the Erase Suspend
mode, and is ready for another valid operation. See
"Autoselect Command Sequence" for more information.
The system must write the Erase Resume command
(address bits are "don't care") to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another Erase
Suspend command can be written after the device has
resumed erasing.

START

Write Erase

Command

Sequence

Data Poll

from System

Embedded
Erase
algorithm in
progress

No

Data = FFh ?

Yes

Erasure Completed

Note :

1. See the appropriate Command Definitions table for erase
command sequences.

2. See "I/O

3

: Sector Erase Timer" for more information.

Figure 4. Erase Operation

(May, 2004, Version 1.0) 16 AMIC Technology, Corp.

A29L160 Series

Table 9. A29L160 Command Definitions

Command

Sequence

(Note 1)

Read (Note 6) 1 RA RD

Reset (Note 7) 1 XXX F0

Manufacturer ID

Top Boot Block

Bottom Boot Block
Continuation ID

Autoselect (Note 8)

Sector Protect Verify
(Note 9)

CFI Query (Note 10)

Program

Unlock Bypass
Unlock Bypass Program (Note 11) 2 XXX A0 PA PD

Unlock Bypass Reset (Note 12) 2 XXX 90 XXX 00
Chip Erase

Sector Erase
Erase Suspend (Note 13) 1 XXX B0

Erase Resume (Note 14) 1 XXX 30

Legend:
X = Don't care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the

whichever happens later.

PD = Data to be programmed at location PA. Data la tches on th e rising edge o f
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A19 - A12 select a unique sector.

Note:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all bus cycles are write operation.

4. Address bits A19 - A11 are don't cares for unlock and command cycles, unless SA or PA required.

5. No unlock or command cycles required when reading array data.

6. The Reset command is required to return to reading array data when device is in the autoselect mode, or if I/O
high (while the device is providing status data).

7. The fourth cycle of the autoselect command sequence is a read cycle.

8. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for
more information.

9. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” f or
more information.

10. Command is valid when device is ready to read array data or when device is in autoselect mode.

11. The Unlock Bypass command is required prior to the Unloc k Bypass Program command.

12. T he Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypas s
mode.

13. The system may read and program in non -erasing sectors, o r en te r the au tosele ct mode , when in the Erase Suspend mode .

14. The Erase Resume command is valid only during the Erase Suspend mode.

Word 555 2AA 555

Byte

Word 555 2AA 555 X01 B3A8 Device ID,

Byte

Word 555 2AA 555 X01 B329 Device ID,

Byte
Word 555 2AA 555 X03
Byte

Word 555 2AA 555

Byte

Word 55

Byte

Byte 555 2AA 555

Byte

Word 555 2AA 555

Byte

Word 555 2AA 555 555 2AA 555

Byte

Word 555 2AA 555 555 2AA

Byte

First Second Third Fourth Fifth Sixth

Cycles

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

4

4

4

4

4

1

4

3

6

6

AAA

AAA

AAA

AAA

AAA

AA

AAA

AAA

AAA

AAA

AA

AA

AA

AA

AA

98

AA

AA

AA

AA

55

555

55

555

55

555

55

555

55

555

55

555

55

555

55

555

555

Bus Cycles (Notes 2 - 5)

90 X00 37

AAA

90

AAA

90

AAA

90

AAA

90

AAA

A0 PA PD

AAA

20

AAA

80

AAA

55

AAA

80

WE

X02 A8

X02 29

X06

(SA)

X02

(SA)

X04

AAA

AAA

or CE pulse, whichever happens first.

7F

XX00
XX01

00
01

AA

AA

55

555

55 SA 30

555

WE

AAA

or CE pulse,

10

5 goes

(May, 2004, Version 1.0) 17 AMIC Technology, Corp.

A29L160 Series

Write Operation Status

Several bits, I/O2, I/O3, I/O5, I/O6, I/O7, RY/

are provided

BY

in the A29L160 to determine the status of a write operation.
Table 10 and the following subsections describe the

functions of these status bits. I/O

7, I/O6 and RY/BY each

offer a method for determining whether a program or erase
operation is complete or in progress. These three bits are
discussed first.

I/O7:

The

Polling

Data

Polling bit, I/O7, indicates to the host system

Data

whether an Embedded Algorithm is in progress or
completed, or whether the device is in Erase Suspend.

Polling is valid after the rising edge of the final WE

Data

pulse in the program or erase command sequence.
During the Embedded Program algorithm, the device
outputs on I/O

7. This I/O7 status also applies to programming during

to I/O

7 the complement of the datum programmed

Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to
I/O

7. The system must provide the program address to

read valid status information on I/O
falls within a protected sector,

7. If a program address

Polling on I/O7 is

Data

active for approximately 2µs, then the device returns to
reading array data.

During the Embedded Erase algorithm,

Data

Polling
produces a "0" on I/O7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase

Suspend mode,

Polling produces a "1" on I/O7.This

Data

is analogous to the complement/true datum output
described for the Embedded Program algorithm: the erase
function changes all the bits in a sector to "1"; prior to this,
the device outputs the "complement," or "0." The system
must provide an address within any of the sectors selected
for erasure to read valid status information on I/O

7.

After an erase command sequence is written, if all sectors
selected for erasing are protected,

Polling on I/O7 is

Data

active for approximately 100µs, then the device returns to
reading array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
protected.
When the system detects I/O7 has changed from the
complement to true data, it can read valid data at I/O
on the following read cycles. This is because I/O
change asynchronously with I/O

(OE) is asserted low. The

0 - I/O6 while Output Enable

Polling Timings (During

Data

7 - I/O0

7 may

Embedded Algorithms) figure in the "AC Characteristics"
section illustrates this. Table 10 shows the outputs for

Polling on I/O7. Figure 5 shows the

Data

Data

Polling
algorithm.

START

Read I/O7-I/O

Address = VA

I/O7 = Data ?

No

Note :

1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.

2. I/O

7

should be rechecked even if I/O5 = "1" because

I/O

7

may change simultaneously with I/O5.

I/O5 = 1?

Read I/O7 - I/O

Address = VA

I/O7 = Data ?

FAIL

0

Yes

No

Yes

0

Yes

No

PASS

Figure 5. Data Polling Algorithm

(May, 2004, Version 1.0) 18 AMIC Technology, Corp.

A29L160 Series

RY/

BY

: Read/

Busy

The RY/BY is a dedicated, open-drain output pin that
indicates whether an Embedded algorithm is in progress or

complete. The RY/
of the final
RY/

BY

WE

is an open-drain output, several RY/BY pins can

status is valid after the rising edge

BY

pulse in the command sequence. Since

be tied together in parallel with a pull-up resistor to VCC.
(The RY/

pin is not available on the 44-pin SOP

BY

package)
If the output is low (Busy), the device is actively erasing or
programming. (This includes programming in the Erase
Suspend mode.) If the output is high (Ready), the device is
ready to read array data (including during the Erase
Suspend mode), or is in the standby mode.

Table 10 shows the outputs for RY/BY. Refer to “

RESET

Timings”, “Timing Waveforms for Program Operation” and
“Timing Waveforms for Chip/Sector Erase Operation” for
more information.

I/O6: Toggle Bit I

Toggle Bit I on I/O6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address, and is valid after

the rising edge of the final WE pulse in the command
sequence (prior to the program or erase operation), and
during the sector erase time-out.
During an Embedded Program or Erase algorithm
operation, successive read cycles to any address cause

6 to toggle. (The system may use either

I/O
control the read cycles.) When the operation is complete,

6 stops toggling.

I/O
After an erase command sequence is written, if all sectors
selected for erasing are protected, I/O6 toggles for
approximately 100µs, then returns to reading array data. If
not all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use I/O

6 and I/O2 together to determine

whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), I/O

6 toggles. When the

device enters the Erase Suspend mode, I/O
toggling. However, the system must also use I/O
determine which sectors are erasing or erase-suspende d.
Alternatively, the system can use I/O7 (see the subsection

on " I/O

7 :

Data

Polling").
If a program address falls within a protected sector, I/O
toggles for approximately 2µs after the program command
sequence is written, then returns to reading array data.
I/O

6 also toggles during the erase-suspend-program mode,

and stops toggling once the Embedded Program algorithm
is complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on I/O

6. Refer to Figure 6 for the toggle bit

algorithm, and to the Toggle Bit Timings figure in the "AC
Characteristics" section for the timing diagram. The I/O

6 figure shows the differences between I/O2 and I/O6 in

I/O
graphical form. See also the subsection on " I/O
Bit II".

OE

or CE to

6 stops

2 to

6

2 vs.

2: Toggle

I/O2: Toggle Bit II

The "Toggle Bit II" on I/O2, when used with I/O6, indicates
whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that
sector is erase-suspended. Toggle Bit II is valid after the

rising edge of the final

pulse in the command

WE

sequence.

2 toggles when the system reads at addresses within

I/O
those sectors that have been selected for erasure. (The

system may use either
cycles.) But I/O

2 cannot distinguish whether the sector is

actively erasing or is erase-suspended. I/O

or CE to control the read

OE

6, by

comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both status
bits are required for sector and mode information. Refer to
Table 10 to compare outputs for I/O

2 and I/O6.

Figure 6 shows the toggle bit algorithm in flowchart form,
and the section " I/O2: Toggle Bit II" explains the algorithm.
See also the " I/O

6: Toggle Bit I" subsection. Refer to the

Toggle Bit Timings figure for the toggle bit timing diagram.
The I/O2 vs. I/O6 figure shows the differences between I/O2

6 in graphical form.

and I/O

Reading Toggle Bits I/O6, I/O2

Refer to Figure 6 for the following discussion. Whenever
the system initially begins reading toggle bit status, it must
read I/O7 - I/O0 at least twice in a row to determine whether
a toggle bit is toggling. Typically, a system would note and
store the value of the toggle bit after the first read. After the
second read, the system would compare the new value of
the toggle bit with the first. If the toggle bit is not toggling,
the device has completed the program or erase operation.
The system can read array data on I/O7 - I/O0 on the
following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system
also should note whether the value of I/O5 is high (see the
section on I/O

5). If it is, the system should then determine

again whether the toggle bit is toggling, since the toggle bit
may have stopped toggling just as I/O5 went high. If the
toggle bit is no longer toggling, the device has successfully
completed the program or erase operation. If it is still
toggling, the device did not complete the operation
successfully, and the system must write the reset
command to return to reading array data.
The remaining scenario is that the system initially
determines that the toggle bit is toggling and I/O

5 has not

gone high. The system may continue to monitor the toggle
bit and I/O5 through successive read cycles, determining
the status as described in the previous paragraph.
Alternatively, it may choose to perform other system tasks.
In this case, the system must start at the beginning of the
algorithm when it returns to determine the status of the
operation (top of Figure 6).

I/O5: Exceeded Timing Limits

I/O5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions I/O5 produces a "1." This is a failure
condition that indicates the program or erase cycle was not
successfully completed.

(May, 2004, Version 1.0) 19 AMIC Technology, Corp.

A29L160 Series

The I/O5 failure condition may appear if the system tries to
program a "1 "to a location that is previously progr ammed
to "0." Only an erase operation can change a "0" back to a
"1." Under this condition, the device halts the operation,
and when the operation has exceeded the timing limits,
I/O

5 produces a "1."

Under both these conditions, the system must issue the
reset command to return the device to reading array data.

I/O3: Sector Erase Timer

After writing a sector erase command sequence, the
system may read I/O

3 to determine whether or not an

erase operation has begun. (The sector erase timer does
not apply to the chip erase command.) If additional sectors
are selected for erasure, the entire time-out also applies
after each additional sector erase command. When the
time-out is complete, I/O

3 switches from "0" to "1." The

Table 10. Write Operation Status

I/O7 I/O6 I/O5 I/O3 I/O2

(Note 1) (Note 2) (Note 1)

7I/O

1 No toggle 0 N/A Toggle 1

Data Data Data Data Data 1

7I/O

Standard
Mode

Erase
Suspend
Mode

Operation

Embedded Program Algorithm
Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0

Reading within Erase
Suspended Sector

Reading within Non-Erase
Suspend Sector

Erase-Suspend-Program

system may ignore I/O

3 if the system can guarantee that

the time between additional sector erase commands will
always be less than 50µs. See also the "Sector Erase
Command Sequence" section.
After the sector erase command sequence is written, the

system should read the status on I/O

7 (

Data

Polling) or
I/O6 (Toggle Bit 1) to ensure the device has accepted the
command sequence, and then read I/O

3. If I/O3 is "1", the

internally controlled erase cycle has begun; all further
commands (other than Erase Suspend) are ignored until
the erase operation is complete. If I/O

3 is "0", the device

will accept additional sector erase commands. To ensure
the command has been accepted, the system software
should check the status of I/O
subsequent sector erase command. If I/O

3 prior to and following each

3 is high on the

second status check, the last command might not have
been accepted. Table 10 shows the outputs for I/O

3.

RY/

BY

Toggle 0 N/A No toggle 0

Toggle 0 N/A N/A 0

Notes:

1. I/O7 and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.

5 switches to “1” when an Embedded Program or Embedded Erase operation has exceeded the maximum timing

2. I/O

limits. See “I/O5: Exceeded Timing Limits” for more information.

Maximum Negative Input Overshoot

20ns 20ns

+0.8V

-0.5V

-2.0V

20ns

(May, 2004, Version 1.0) 20 AMIC Technology, Corp.

A29L160 Series

Maximum Positive Input Overshoot

20ns

VCC+2.0V

VCC+0.5V

2.0V

20ns20ns

DC Characteristics

CMOS Compatible

Parameter

Symbol

ILI Input Load Current

Parameter Description

Test Description

V

IN = VSS to VCC. VCC = VCC Max

Min.

Typ.

ILIT A9 Input Load Current VCC = VCC Max, A9 =12.5V 35
ILO

ICC1

ICC2

Output Leakage Current

VCC Active Read Current
(Notes 1, 2)

VCC Active Write (Program/Erase)
Current (Notes 2, 3, 4)

ICC3
ICC4

VCC Standby Current (Note 2)
VCC Standby Current During Reset

(Note 2)

ICC5

Automatic Sleep Mode
(Note 2, 4, 5)

VIL Input Lo w Level
VIH Input High Level

VID

Voltage for Autoselect and

OUT = VSS to VCC. VCC = VCC Max

V

= VIL, OE = VIH

CE

Byte Mode

= VIL, OE = VIH

CE

5 MHz
1 MHz

Word Mode

= VIL, OE =VIH

CE

= VIH,

CE

RESET

V

IH = VCC ± 0.3V; VIL = VSS ± 0.3V

RESET

= VSS ± 0.3V

= VCC ± 0.3V

VCC = 3.3 V

5 MHz
1 MHz

9 16
2 4
9

2

20

0.2

0.2 5

0.2 5

-0.5

0.7 x VCC

11.5

Temporary Unprotect Sector

VOL Output Low Voltage
VOH1
VOH2

Output High Voltage

I

OL = 4.0mA, VCC = VCC Min
OH = -2.0 mA, VCC = VCC Min

I
IOH = -100 µA, VCC = VCC Min

0.85 x VCC
VCC - 0.4

Max.

Unit

±1.0 µA

µA

±1.0

16

µA

mA

4

30 mA

5

µA
µA

µA

0.8

VCC + 0.3 V

12.5

0.45

V

V
V

V
V

Notes:

1. The ICC current listed is typically less than 2 mA/MHz, withOEat VIH. Typical VCC is 3.0V.

2. Maximum ICC specifications are tested with VCC = VCC max.

3. I

CC active while Embedded Algorithm (program or erase) is in progress.

4. Automatic sleep mode enables the low power mode when addresses remain stable for t

ACC + 30ns. Typical sleep mode

current is 200nA.

5. Not 100% tested.

(May, 2004, Version 1.0) 21 AMIC Technology, Corp.

A29L160 Series

DC Characteristics (continued)

Zero Power Flash

25

20

15

10

Supply Current in mA

5

0

0 500 1000 1500 2000 2500 3000 3500 4000

Time in ns

Note: Addresses are switching at 1MHz

10

8

6

4

Supply Current in mA

2

0

I

CC1

Current vs. Time (Showing Active and Automatic Sleep Currents)

3.6V

2.7V

12345

Frequency in MHz

C25T :Note °=

Typical I

CC1

vs. Frequency

(May, 2004, Version 1.0) 22 AMIC Technology, Corp.

A29L160 Series

AC Characteristics

Read Only Operations

Parameter Symbols Speed

JEDEC

tAVAV tRC
tAVQV

tELQV
tGLQV tOE

Std

ACC

t

CE

t

Read Cycle Time (Note 1)

Address to Output Delay

Chip Enable to Output Delay
Output Enable to Output Delay

Output Enable Hold
Time (Note 1)

Chip Enable to Output High Z

DF

tEHQZ

tOEH

t

(Notes 1)

tGHQZ

t

Output Enable to Output High Z

DF

(Notes 1)

Output Hold Time from Addresses,

tAXQX tOH

or OE, Whichever Occurs First

CE

Description Test Setup

-70

Read
Toggle and

Polling

Data

CE
OE

OE

= VIL
= VIL

= VIL

Min.

Max.

Max.
Max.

Min.

70
70

70
30

0

Min. 10 10 10

Max. 25 30 30

25 30 30

Min. 0 0 0 ns

-90 -120

90 120
90 120

90 120
35 50

0 0

(Note 1)

Notes:

1. Not 100% tested.

2. See Test Conditions and Test Setup for test specifications.

Unit

ns
ns

ns
ns
ns

ns

ns

ns

Timing Waveforms for Read Only Operation

t

RC

Addresses Addresses Stable

t

ACC

CE

t

OE

t

CE

OE

WE

Output

RESET

RY/BY

0V

t

OEH

High-Z

Output Valid

t

DF

OH

t

High-Z

(May, 2004, Version 1.0) 23 AMIC Technology, Corp.

A29L160 Series

AC Characteristics
Hardware Reset (

Parameter

JEDEC Std

tRP
tRH
tRB
tRPD

Note: Not 100% tested.

RESET

READY

t

READY

t

Timings

RY/BY

RESET

RESET

Algorithms) to Read or Write (See Note)

RESET

Algorithms) to Read or Write (See Note)

RESET
RESET

RY/

RESET

)

Description Test Setup All Speed Options Unit

Pin Low (During Embedded

Pin Low (Not During Embedded

Pulse Width
High Time Before Read (See Note)

Recovery Time

BY

Low to Standby Mode

Max 20

Max 500 ns

Min 500 ns
Min 50 ns
Min 0 ns
Min 20

µs

µs

CE, OE

RESET

RY/BY

CE, OE

RESET

t

RH

t

RP

t

Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t

Ready

~

~

~

~

~

~

t

RP

t

RB

(May, 2004, Version 1.0) 24 AMIC Technology, Corp.

A29L160 Series

Temporary Sector Unprotect

Parameter

JEDEC Std

Note: Not 100% tested.

VIDR VID Rise and Fall Time (See Note) Min 500 ns

t

RSP

t

RESET

Unprotect

Setup Time for Temporary Sector

Description All Speed Options Unit

Temporary Sector Unprotect Timing Diagram

12V

0 or 3V

RESET

CE

WE

RY/BY

t

VIDR

t

Program or Erase Command Sequence

RSP

~

~
~

~

~

~
~

~

Min 4

0 or 3V

t

VIDR

µs

AC Characteristics

Word/Byte Configuration (

Parameter

JEDEC Std

ELFL/tELFH

t

FLQZ

t

HQV

t

)

BYTE

Description

to

CE

BYTE
BYTE

Switching Low or High

BYTE

Switching Low to Output High-Z
Switching High to Output Active

All Speed Options

-70 -90 -120

Max 5 ns
Max 25 30 30 ns

Min 70 90 120 ns

Unit

(May, 2004, Version 1.0) 25 AMIC Technology, Corp.

A29L160 Series

Timings for Read Operations

BYTE

CE

OE

BYTE

BYTE

Switching

I/O0-I/O

ELFL

14

Data Output

0

-I/O14)

(I/O

Data Output

0

-I/O7)

(I/O

t

from word to

byte mode

I/O

15

(A-1)

t

ELFH

t

FLQZ

I/O

15

Output

Address Input

BYTE

Data Output

0

-I/O7)

(I/O

BYTE

I/O0-I/O

14

Switching

from byte to

word mode

I/O

15

(A-1)

Address Input

t

FHQV

Timings for Write Operations

BYTE

CE

WE

BYTE

t

SET

(tAS)

Note:

Refer to the Erase/Program Operations table for tAS and tAH specifications.

The falling edge of the last WE signal

t

HOLD(tAH

Output

)

Data Output

0

-I/O14)

(I/O

I/O

15

(May, 2004, Version 1.0) 26 AMIC Technology, Corp.

A29L160 Series

AC Characteristics

Erase and Program Operations

Parameter Speed

JEDEC

tAVAV
tAVWL
tWLAX
tDVWH
tWHDX

tGHWL

Std

t

WC
AS

t

AH

t

DS

t

DH

t

OES

t

GHWL

t

Write Cycle Time (Note 1)

Address Setup Time
Address Hold Time
Data Setup Time

Data Hold Time

Output Enable Setup Time

Read Recover Time Before Write

Description

Min.
Min.
Min.
Min.
Min.
Min.

Min.

-70

70

45
35

(OE high to WE low)

tELWL tCS
tWHEH

tWLWH
tWHWL

CH

t

WP

t

t

WPH

tWHWH1 tWHWH1

Setup Time

CE

Hold Time

CE

Write Pulse Width
Write Pulse Width High

Byte Programming Operation
(Note 2)

Byte Typ. 5

Word Typ. 7

Min.
Min.
Min.
Min.

35

-90 -120

90 120

0
45 50
45 50

0

0

0

0

0
35 50
30

Unit

ns
ns
ns
ns
ns
ns

ns

ns
ns
ns
ns

µs

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ. 0.7 sec

t

t

BUSY

t

VCC Set Up Time (Note 1)

vcs
RB

Recovery Time from RY/
Program/Erase Valid to RY/

BY

BY

Delay

Min.

Min
Min

50

0
90

Notes:

1. Not 100% tested.

2. See the "Erase and Programming Performance" section for more information.

µs
ns
ns

(May, 2004, Version 1.0) 27 AMIC Technology, Corp.

A29L160 Series

Timing Waveforms for Program Operation

Addresses

CE

OE

WE

Program Command Sequence (last two cycles)

t

WC

555h

t

CS

t

CH

t

WP

t

DS

t

t

AS

WPH

PA

t

DH

t

AH

Read Status Data (last two cycles)

~

~

PA

~

~

~

~

~

~

t

WHWH1

~

~

PA

Data

RY/BY

t

VCS

VCC

Note :

1. PA = program addrss, PD = program data, Dout is the true data at the program address.

2. Illustration shows device in word mode.

A0h PD

t

BUSY

~

~

~

~

~

~

Status

OUT

D

t

RB

(May, 2004, Version 1.0) 28 AMIC Technology, Corp.

A29L160 Series

Timing Waveforms for Chip/Sector Erase Operation

Addresses

CE

OE

WE

Data

Erase Command Sequence (last two cycles)

t

t

WC

2AAh

t

CS

t

CH

t

WP

t

DS

55h 30h

AS

SA

555h for chip erase

t

WPH

t

DH

10h for chip erase

t

AH

~
~

~

~

~

~

t

BUSY

~
~

~

~

~

t

~

WHWH2

Read Status Data

VA

In

Progress

VA

Complete

t

RB

RY/BY

~

t

VCS

VCC

Note :

1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operaion Ststus").

2. Illustratin shows device in word mode.

~

~

~

(May, 2004, Version 1.0) 29 AMIC Technology, Corp.

A29L160 Series

Timing Waveforms for

Addresses

CE

t

CH

OE

t

OEH

WE

I/O

7

I/O

0

- I/O

6

High-Z

Polling (During Embedded Algorithms)

Data

t

t

ACC

RC

t

CE

t

OE

t

DF

t

OH

Complement

Status Data

~

~

VAVA VA

~

~

~

~

~

~

~

~

Complement True

~

~

Status Data True

~

~

Valid Data

High-Z

High-Z

Valid Data

t

BUSY

RY/BY

~

~

Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data
read cycle.

(May, 2004, Version 1.0) 30 AMIC Technology, Corp.

A29L160 Series

Timing Waveforms for Toggle Bit (During Embedded Algorithms)

t

Addresses

CE

RC

VAVA VA

t

ACC

t

CE

t

CH

t

OE

~

~

VA

~

~

~

~

OE

t

OEH

WE

I/O

6

,

I/O

2

RY/BY

High-Z

t

BUSY

Valid Status

(first read) (second read) (stop togging)

Note: VA = Valid Address; not required for I/O

read cycle, and array data read cycle.

~

t

DF

t

OH

Valid Status Valid Status Valid Data

6. Illustration shows first two status cycle after command sequence, last status

~

~

~

~

~

~

~

(May, 2004, Version 1.0) 31 AMIC Technology, Corp.

A29L160 Series

Timing Waveforms for Sector Protect/Unprotect

V

ID

V

RESET

SA, A6,

A1, A0

Data

CE

WE

IH

~

~

Valid* Valid* Valid*

~

Sector Protect/Unprotect Verify

60h 60h 40h Status

1us

Sector Protect:150us

Sector Unprotect:15ms

~

~

~

~

~

OE

Note : For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0

Timing Waveforms for I/O

Enter

Embedded

Erasing

WE

I/O

I/O

6

2

I/O

Erase

2

2 vs. I/O6

Erase

Suspend

~

~

~

~

~

~

and I/O6 toggle with OE and CE

~

~

Erase Suspend

Read

~

~

~

~

Enter Erase

Suspend Program

Suspend
Program

Erase

~

~

Erase Suspend

~

~

~

~

~

Read

~

~

~

~

~

Erase

Resume

Erase

~

~

~

~

Erase

Complete

~

~

Note : Both I/O6 and I/O2 toggle with OE or CE. See the text on I/O6 and I/O2 in the section "Write Operation Status" for
more information.

(May, 2004, Version 1.0) 32 AMIC Technology, Corp.

A29L160 Series

AC Characteristics

Erase and Program Operations

Alternate

Controlled Writes

CE

Parameter

JEDEC Std

tAVAV tWC Write Cycle Time (Note 1) Min. 70 90 120 ns
tAVEL tAS Address Setup Time Min. 0 ns

tELAX tAH Address Hold Time Min. 45 45 50 ns
tDVEH tDS Data Setup Time Min. 35 45 50 ns
tEHDX tDH Data Hold Time Min. 0 ns

tOES Output Enable Setup Time Min. 0 ns

tGHEL tGHEL

tWLEL tWS
tEHWH tWH

tELEH tCP

tEHEL tCPH

tWHWH1 tWHWH1

Read Recover Time Before Write
(OE High to WE Low)

Setup Time

WE

Hold Time

WE

Pulse Width

CE

Pulse Width High

CE

Programming Operation
(Note 2)

Description

Speed

-70 -90 -120

Min. 0 ns

Min. 0 ns
Min. 0 ns
Min. 35 35 50 ns

Min. 30 ns

Byte Typ. 5

Word Typ. 7

Unit

µs

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ. 0.7 sec

Notes:

1. Not 100% tested.

2. See the "Erase and Programming Performance" section for more information.

(May, 2004, Version 1.0) 33 AMIC Technology, Corp.

A29L160 Series

Timing Waveforms for Alternate CE Controlled Write Operation

Addresses

WE

OE

Data

RESET

CE

t

RH

555 for program

2AA for erase

t

WC

t

WS

A0 for program
55 for erase

PA for program
SA for sector erase
555 for chip erase

t

AS

t

WH

t

CP

t

CPH

t

DS

t

DH

t

AH

t

BUSY

PD for program
30 for sector erase
10 for chip erase

Data Polling

~

~

~

~

~

~

~

~

t

WHWH1 or 2

~

~

~

~

~

~

PA

I/O

OUT

D

7

RY/BY

~

~

Note :

1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O

2. Figure indicates the last two bus cycles of the command sequence.

7

= Complement of Data Input, D

OUT

= Array Data.

Erase and Programming Performance

Parameter Typ. (Note 1) Max. (Note 2) Unit Comments

Sector Erase Time 1.0 8 sec
Chip Erase Time 35 sec
Byte Programming Time 35 300
Word Programming Time 12 500

µs
µs

Byte Mode 11 33 sec Chip Programming Time

(Note 3)

Word Mode 7.2 21.6 sec

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0V VCC, 10,000 cycles. Additionally,
programming typically assumes checkerboard pattern.

2. Under worst case conditions of 90°C, VCC = 2.7V, 100,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only
then does the device set I/O

5 = 1. See the section on I/O5 for further information.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h befor e erasure.

5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table
9 for further information on command definitions.

6. The device has a guaranteed minimum erase and progra m cycle endurance of 10,000 cycles.

Excludes 00h programming
prior to erasure

Excludes system-level
overhead (Note 5)

(May, 2004, Version 1.0) 34 AMIC Technology, Corp.

A29L160 Series

Latch-up Characteristics

Description Min. Max.

Input Voltage with respect to VSS on all I/O pins

-1.0V

VCC+1.0V
VCC Current
Input voltage with respect to VSS on all pins except I/O pins

(including A9, OEand

RESET

)

Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at time.

TSOP and SOP Pin Capacitance

Parameter Symbol

CIN Input Capacitance

COUT

CIN2

Output Capacitance
Control Pin Capacitance

Notes:

1. Sampled, not 100% tested.

2. Test conditions TA = 25°C, f = 1.0MHz

Parameter Description

Test Setup

Data Retention

Parameter

Minimum Pattern Data Retention Time

Test Conditions

150°C
125°C

IN=0

V

V

OUT=0

V

IN=0

-100 mA

-1.0V

Typ.

6

8.5

7.5

Min

Max.

7.5
12

9

+100 mA

12.5V

Unit

pF
pF
pF

Unit

10 Years
20 Years

(May, 2004, Version 1.0) 35 AMIC Technology, Corp.

A29L160 Series

Test Conditions

Test Specifications

Test Condition -70 -90, -120 Unit

Output Load 1 TTL gate
Output Load Capacitance, CL(including jig capacitance) 30 100 pF
Input Rise and Fall Times 5 5 ns
Input Pulse Levels 0.0 - 3.0 0.0 - 3.0 V
Input timing measurement reference levels 1.5 1.5 V
Output timing measurement reference levels 1.5 1.5 V

Test Setup

3.3 V

2.7 K

Ω

Device

Under

Test

6.2 K

C

L

Ω

Diodes = IN3064 or Equivalent

(May, 2004, Version 1.0) 36 AMIC Technology, Corp.

A29L160 Series

Ordering Information
Top Boot Sector Flash

Part No.

A29L160TM-70 44Pin SOP

A29L160TV-70 48Pin TSOP

A29L160TV-70F 48 Pin Pb-Free TSOP

A29L160TG-70

A29L160TM-90 44Pin SOP

A29L160TV-90 48Pin TSOP

A29L160TG-90

A29L160TM-120 44Pin SOP

A29L160TV-120 48Pin TSOP

A29L160TG-120

Access Time

(ns)

70 9 20 0.2

90 9 20 0.2

120 9 20 0.2

Active Read

Current

Typ. (mA)

Program/Erase

Current

Typ. (mA)

Standby Current

Typ. (µA)

Package

48-ball TFBGA

48-ball TFBGA

48-ball TFBGA

Bottom Boot Sector Flash

Part No.

A29L160UM-70 44Pin SOP

A29L160UV-70 48Pin TSOP

A29L160UV-70F 48 Pin Pb-Free TSOP

A29L160TG-70

A29L160UM-90 44Pin SOP

A29L160UV-90 48Pin TSOP

A29L160TG-90

A29L160UM-120 44Pin SOP

A29L160UV-120 48Pin TSOP

A29L160TG-120

Access Time

(ns)

70 9 20 0.2

90 9 20 0.2

120 9 20 0.2

Active Read

Current

Typ. (mA)

Program/Erase

Current

Typ. (mA)

Standby

Current

Typ. (µA)

Package

48-ball TFBGA

48-ball TFBGA

48-ball TFBGA

(May, 2004, Version 1.0) 37 AMIC Technology, Corp.

A29L160 Series

Package Information
SOP 44L Outline Dimensions

44

1

S

Seating Plane

unit: inches/mm

23

E

HE

Gauge Plane

θ

0.010"

22

b

L

Detail F

D

C

A

A2

L

y

D

e

A1

See Detail F

1

Symbol

A - - 0.118 - - 3.00
A1 0.004 - - 0.10 - ­A2 0.103 0.106 0.109 2.62 2.69 2.77

b 0.013 0.016 0.020 0.33 0.40 0.50
C 0.007 0.008 0.010 0.18 0.20 0.25
D - 1.122 1.130 - 28.50 28.70
E 0.490 0.496 0.500 12.45 12.60 12.70

e

HE 0.620 0.631 0.643 15.75 16.03 16.33

L 0.024 0.032 0.040 0.61 0.80 1.02

L1 - 0.0675 - - 1.71 -

S - - 0.045 - - 1.14

y - - 0.004 - - 0.10

θ

Dimensions in inches Dimensions in mm

Min Nom Max Min Nom Max

- 0.050 - - 1.27 -

0°

-

8° 0°

-

8°

Notes:

1. The maximum value of dimension D includes end flash.

2. Dimension E does not include resin fins.

3. Dimension S includes end flash.

(May, 2004, Version 1.0) 38 AMIC Technology, Corp.

A29L160 Series

Package Information
TSOP 48L (Type I) Outline Dimensions

D

D

1

1

24 25

Detail "A"

Symbol

A - - 0.047 - - 1.20

A1 0.002 - 0.006 0.05 - 0.15
A2 0.037 0.039 0.042 0.94 1.00 1.06

b 0.007 0.009 0.011 0.18 0.22 0.27

c 0.004 - 0.008 0.12 - 0.20
D 0.779 0.787 0.795 19.80 20.00 20.20

D1 0.720 0.724 0.728 18.30 18.40 18.50

E - 0.472 0.476 - 12.00 12.10
e 0.020 BASIC 0.50 BASIC
L 0.016 0.020 0.024 0.40 0.50 0.60
S 0.011 Typ. 0.28 Typ.

y - - 0.004 - - 0.10

θ

unit: inches/mm

A

A1

A2

48

E

c

L

0.25

Dimensions in inches Dimensions in mm

Min Nom Max Min Nom Max

0° - 8° 0° - 8°

y

D

b

e

S

θ

Detail "A"

Notes:

1. The maximum value of dimension D includes end flash.

2. Dimension E does not include resin fins.

3. Dimension S includes end flash.

(May, 2004, Version 1.0) 39 AMIC Technology, Corp.

A29L160 Series

Package Information
48 Balls CSP (6 x 8 mm) Outline Dimensions

(48TFBGA)

TOP VIEW

unit: mm

BOTTOM VIEW

b

H

G

F
E
D
C
B
A

C

0.10 C

123456

Ball*A1 CORNER

SIDE VIEW

SEATING PLANE

A1

H

G

F
E
D
C
B
A

e

D

1

D

A

e

E

E1

Symbol

A - - 1.20

A1 0.20 0.25 0.30

b 0.30 - 0.40

D 5.90 6.00 6.10

D1 4.00 BSC

e - 0.80 ­E 7.90 8.00 8.10

E1 5.60 BSC

Dimensions in mm

Min.

Nom. Max.

(May, 2004, Version 1.0) 40 AMIC Technology, Corp.