Datasheet A29800 Datasheet (AMIC)

Download

Page 1

A29800 Series

1024K X 8 Bit / 512K X 16 Bit CMOS 5.0 Volt-only,

Boot Sector Flash Memory

Document Title 1024K X 8 Bit / 512K X 16 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory

Revision History

Rev. No.

History Issue Date Remark

0.0 Initial issue May 4, 2001 Preliminary

0.1 Error Correction:

1.0 Final version release October 7, 2003 Final

1.1 Add Pb-Free package type for -70 grade July 15, 2004

P.10: Autoselect Command Sequence (line 15), XX11h → XX03h

December 24, 2002

(July, 2004, Version 1.1)

AMIC Technology, Corp.

Page 2

A29800 Series

1024K X 8 Bit / 512K X 16 Bit CMOS 5.0 Volt-only,

Boot Sector Flash Memory

Features

 5.0V ± 10% for read and write operations  Access times:

- 55/70/90 (max.)  Current:

- 28mA read current (word mode)

- 20 mA typical active read current (byte mode)

- 30 mA typical program/erase current

- 1 µA typical CMOS standby  Flexible sector architecture

- 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX15 sectors

- 8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX15 sectors

- Any combination of sectors can be erased

- Supports full chip erase

- Sector protection:

A hardware method of protecting sectors to prevent any inadvertent program or erase operations within that sector

 Top or bottom boot block configurations available  Embedded Erase Algorithms

- Embedded Erase algorithm will automatically erase the entire chip or any combination of designated sectors and verify the erased sectors

- Embedded Program algorithm automatically writes and verifies bytes at specified addresses

 Typical 100,000 program/erase cycles per sector  20-year data retention at 125°C

- Reliable operation for the life of the system  Compatible with JEDEC-standards

- Pinout and software compatible with single-power-supply Flash memory standard

- Superior inadvertent write protection



Polling and toggle bits

Data

- Provides a software method of detecting completion of program or erase operations

 Erase Suspend/Erase Resume

- Suspends a sector erase operation to read data from, or

program data to, a non-erasing sector, then resumes the erase operation

 Hardware reset pin (

RESET

)

- Hardware method to reset the device to reading array data

 Package options

- 44-pin SOP or 48-pin TSOP (I)

General Description

The A29800 is a 5.0 volt only Flash memory organized as 1048,576 bytes of 8 bits or 524,288 words of 16 bits each.

The A29800 offers the

RESET

data are further divided into nineteen sectors for flexible sector erase capability. The 8 bits of data appear on I/O

7 while the addresses are input on A1 to A18; the 16 bits

I/O of data appear on I/O

0~I/O15. The A29800 is offered in 44-pin

SOP and 48-Pin TSOP packages. This device is designed to be programmed in-system with the standard system 5.0 volt VCC supply. Additional 12.0 volt VPP is not required for insystem write or erase operations. However, the A29800 can also be programmed in standard EPROM programmers. The A29800 has the first toggle bit, I/O whether an Embedded Program or Erase is in progress, or it is in the Erase Suspend. Besides the I/O A29800 has a second toggle bit, I/O addressed sector is being selected for erase. The A29800 also offers the ability to program in the Erase Suspend mode. The standard A29800 offers access times of 55, 70 and 90 ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention the device has

separate chip enable ( enable (

) controls.

The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.

function. The 1024 Kbytes of

0 -

6, which indicates

6 toggle bit, the

2, to indicate whether the

), write enable (WE) and output

The A29800 is entirely software command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by writing the proper program command sequence. This initiates the Embedded Program algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper program margin. Device erasure occurs by executing the proper erase command sequence. This initiates the Embedded Erase algorithm - an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper erase margin. The host system can detect whether a program or erase

operation is complete by reading the I/O I/O

6 (toggle) status bits. After a program or erase cycle has

7 (

Polling) and

Data

been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data

(July, 2004, Version 1.1) 1

AMIC Technology, Corp.

Page 3

A29800 Series

contents of other sectors. The A29800 is fully erased when shipped from the factory. The hardware sector protection feature disables operations for both program and erase in any combination of the sectors of memory. This can be achieved via programming equipment.

The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data

Pin Configurations



SOP  TSOP (I)

to, any other sector that is not selected for erasure. True background erase can thus be achieved. Power consumption is greatly reduced when the device is placed in the standby mode.

The hardware

RESET

pin terminates any operation in

progress and resets the internal state machine to reading array data.

RY/BY

A18

A17

A7 A6 A5 A4 A3 A2 A1 A0

VSS

OE I/O I/O

I/O I/O I/O

I/O

1 2

3 4 5 6 7 8 9

10 11 12 13 14

16 29

19 20

44 43 42 41 40 39 38 37 36 35 34 33

A29800

32 31 30

28 27 26 25 24

RESET

A8 A9

A10 A11 A12

A13

A14 A15

A16 BYTE

VSS I/O

I/O

VCC

(A-1)

A14 A13 A12 A11 A10

A9 A8

RESET

NC NC

RY/BY

A18

A17

A7 A6 A5 A4 A3 A2 A1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

17 18 19 20

21 22 23 24 25

A29800V

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 I/O

A16A15

BYTE VSS I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O

32 I/O

I/O

31 30

I/O

OE VSS

27 26

CE A0

15 7 14 6 13 5 12 4

11 3 10 2

9 1 8 0

(A-1)

(July, 2004, Version 1.1) 2 AMIC Technology, Corp.

Page 4

A29800 Series

Block Diagram

VCC

VSS

RESET

RY/BY

Sector Switches

Erase Voltage

Generator

I/O

- I/O

Input/Output

Buffers

(A-1)

BYTE

CE OE

VCC Detector

A0-A18

Pin Descriptions

State

Control

Command

I/O15 (A-1)

PGM Voltage

Generator

Chip Enable

Output Enable

Logic

STB

Timer

Y-Decoder

X-decoder

Address Latch

Pin No. Description

A0 - A18 Address Inputs

I/O0 - I/O14 Data Inputs/Outputs

I/O15

Data Input/Output, Word Mode

A-1 LSB Address Input, Byte Mode

RESET

BYTE

Chip Enable Write Enable Output Enable Hardware Reset (N/A A298001) Selects Byte Mode or Word Mode

STB

Data Latch

Y-Gating

Cell Matrix

RY/BY

Ready/

BUSY

- Output

VSS Ground VCC Power Supply

(July, 2004, Version 1.1) 3 AMIC Technology, Corp.

Page 5

A29800 Series

Absolute Maximum Ratings*

Ambient Operating Temperature . . . . ….. -55°C to + 125°C

Storage Temperature . . . . . . . . . . . . . . …. -65°C to + 125°C

Ground to VCC . . . . . . . . . . . . . . . . . . . . . ….. -2.0V to 7.0V

Output Voltage (Note 1) . . . . . . . . . . . . . . …... -2.0V to 7.0V

RESET

A9,

All other pins (Note 1) . . . . . . . . . . . . . . . . ….. -2.0V to 7.0V

Output Short Circuit Current (Note 3) . . . . . . ….. . . . 200mA

(Note 2) . . . . . . . . . . ….. -2.0V to 12.5V

Notes:

1. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may undershoot VSS to -2.0V for periods of up to 20ns. Maximum DC voltage on output and I/O pins is VCC +0.5V. During voltage transitions, outputs may overshoot to VCC +2.0V for periods up to 20ns.

2. Minimum DC input voltage on A9 pins is -0.5V. During

voltage transitions, A9, VSS to -2.0V for periods of up to 20ns. Maximum DC

input voltage on A9 and overshoot to 13.5V for periods up to 20ns.

3. No more than one output is shorted at a tim e. Duration of

the short circuit should not be greater than one second.

and

RESET

is +12.5V which may

may overshoot

Device Bus Operations

This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve

Table 1. A29800 Device Bus Operations

*Comments

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of these specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.

Operating Ranges

Commercial (C) Devices

Ambient Temperature (T

VCC Supply Voltages

VCC for ± 10% devices . . . . . . . . . . . …... . . +4.5V to +5.5V

Operating ranges define those limits between which the functionally of the device is guaranteed.

as inputs to the internal state machine. The state machine outputs dictate the function of the device. The appropriate device bus operations table lists the inputs and control levels required, and the resulting output. The following subsections describe each of these operations in further detail.

A) . . . . . . . . …. .. . . . . 0°C to +70°C

RESET

A0 - A18 I/O

0 - I/O7

BYTE

Read L L H H AIN DOUT DOUT High-Z Write L H L H AIN DIN DIN High-Z CMOS Standby TTL Standby H X X H X High-Z High-Z High-Z Output Disable L H H H X High-Z High-Z High-Z Hardware Reset X X X L X High-Z High-Z High-Z Temporary Sector

Unprotect (See Note)

Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0 .5V, X = Don' t Care, DIN = Data In, DOUT = Data Out , AIN = Address In Note: See the "Sector Protection/Unprotection" section and Temporary Sector Unprotect for more information.

(July, 2004, Version 1.1) 4 AMIC Technology, Corp.

VCC ± 0.5 V

X X X V

X X

VCC ± 0.5 V

ID AIN DIN DIN X

X High-Z High-Z High-Z

I/O

=VIH

8 - I/O15 Operation

BYTE

=VIL

Page 6

A29800 Series

Word/Byte Configuration

Program and Erase Operation Status

The operate in the byte or word configuration. If the

set at logic “1”, the device is in word configuration, I/O

pin determines whether the I/O pins I/O15 - I/O0

BYTE

pin is

15 - I/O0

are active and controlled by CEand OE. If the

configuration, and only I/O

and OE. I/O8- I/O14 are tri-stated, and I/O15 pin is used

pin is set at logic “0”, the device is in byte

BYTE

0 - I/O7 are active and controlled by

as an input for the LSB(A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the

selects the device. data to the output pins.

and OE pins to VIL. CE is the power control and

is the output control and gates array

should remain at VIH all the time

during read operation. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See "Reading Array Data" for more information. Refer to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for the timing waveforms,

CC1 in the DC Characteristics table represents the active

l current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which incl udes programming data to the device and erasing sectors of

memory), the system must drive

to VIH. An erase operation can erase one sector,

multiple sectors, or the entire device. The Sector Address Tables indicate the address range that each sector occupies. A "sector address" consists of the address inputs required to uniquely select a sector. See the "Command Definitions" section for details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on I/O read cycle timings apply in this mode. Refer to the "Autoselect Mode" and "Autoselect Command Sequence" sections for more information.

CC2 in the DC Characteristics table represents the active

I current specification for the write mode. The "AC Characteristics" section contains timing specification tables and timing diagrams for write operations.

and CE to VIL, and

7 - I/O0. Standard

During an erase or program operation, the system may check the status of the operation by reading the status bits

7 - I/O0. Standard read cycle timings and ICC read

on I/O specifications apply. Refer to "Write Operation Status" for more information, and to each AC Characteristics section for timing diagrams.

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are

placed in the high impedance state, independent of the

input. The device enters the CMOS standby mode when the

RESET

more restricted voltage range than V the TTL standby mode when

RESET

standard access time (t

pins are both held at VCC ± 0.5V. (Note that this is a

IH.) The device enters

is held at VIH, while

is held at VCC±0.5V. The device requires the

CE) before it is ready to read data.

If the device is deselected during erasure or programming, the device draws active current until the operation is completed.

CC3 in the DC Characteristics tables represents the standby

I current specification.

Output Disable Mode

When the OE input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

RESET

The the device to reading array data. When the system drives the

RESET

immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for

the duration of the internal state machine to reading array data. The operation

that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.

The system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. Refer to the AC Characteristics tables for parameters and diagram.

: Hardware Reset Pin

RESET

pin provides a hardware method of resetting

pin low for at least a period of tRP, the device

pulse. The device also resets the

RESET

pin may be tied to the system reset circuitry. A

RESET

(July, 2004, Version 1.1) 5 AMIC Technology, Corp.

Page 7

A29800 Series

Table 2. A29800 Top Boot Block Sector Address Table

Address Range (in hexadecimal) Sector A18 A17 A16 A15 A14 A13 A12 Sector Size (Kbytes/ Kwords)

(x16)

(x8)

Address Range

SA0 0 0 0 0 X X X 64/32 00000h - 07FFFh 00000h - 0FFFFh

SA1 0 0 0 1 X X X 64/32 08000h - 0FFFFh 10000h - 1FFFFh

SA2 0 0 1 0 X X X 64/32 10000h - 17FFFh 20000h - 2FFFFh

SA3 0 0 1 1 X X X 64/32 18000h - 1FFFFh 30000h - 3FFFFh

SA4 0 1 0 0 X X X 64/32 20000h - 27FFFh 40000h - 4FFFFh

SA5 0 1 0 1 X X X 64/32 28000h - 2FFFFh 50000h - 5FFFFh

SA6 0 1 1 0 X X X 64/32 30000h - 37FFFh 60000h - 6FFFFh

SA7 0 1 1 1 X X X 64/32 38000h -3FFFFh 70000h -7FFFFh

SA8 1 0 0 0 X X X 64/32 40000h -47FFFh 80000h -8FFFFh

SA9 1 0 0 1 X X X 64/32 48000h -4FFFFh 90000h -9FFFFh

SA10 1 0 1 0 X X X 64/32 50000h - 57FFFh A0000h - AFFFFh

SA11 1 0 1 1 X X X 64/32 58000h - 5FFFFh B0000h - BFFFFh

Address Range

SA12 1 1 0 0 X X X 64/32 60000h - 67FFFh C0000h - CFFFFh

SA13 1 1 0 1 X X X 64/32 68000h - 6FFFFh D0000h - DFFFFh

SA14 1 1 1 0 X X X 64/32 70000h - 77FFFh E0000h - EFFFFh

SA15 1 1 1 1 0 X X 32/16 78000h - 7BFFFh F0000h - F7FFFh

SA16 1 1 1 1 1 0 0 8/4 7C000h - 7CFFFh F8000h - F9FFFh

SA17 1 1 1 1 1 0 1 8/4 7D000h - 7DFFFh FA000h - FBFFFh

SA18 1 1 1 1 1 1 X 16/8 7E000h - 7FFFFh FC000h - FFFFFh

Note:

Address range is A18: A-1 in byte mod and A18: A0 in word mode. See the “Word/Byte Configuration” section for more information.

(July, 2004, Version 1.1) 6 AMIC Technology, Corp.

Page 8

A29800 Series

Table 3. A29800 Bottom Boot Block Sector Address Table

Address Range Sector A18 A17 A16 A15 A14 A13 A12 Sector Size

(Kbytes /

Kwords)

SA0 0 0 0 0 0 0 X 16/8 00000h - 01FFFh 00000h - 03FFFh SA1 0 0 0 0 0 1 0 8/4 02000h - 02FFFh 04000h - 05FFFh SA2 0 0 0 0 0 1 1 8/4 03000h - 03FFFh 06000h - 07FFFh SA3 0 0 0 0 1 X X 32/16 04000h - 07FFFh 08000h - 0FFFFh SA4 0 0 0 1 X X X 64/32 08000h - 0FFFFh 10000h - 1FFFFh SA5 0 0 1 0 X X X 64/32 10000h - 17FFFh 20000h - 2FFFFh SA6 0 0 1 1 X X X 64/32 18000h - 1FFFFh 30000h - 3FFFFh SA7 0 1 0 0 X X X 64/32 20000h - 27FFFh 40000h - 4FFFFh SA8 0 1 0 1 X X X 64/32 28000h - 2FFFFh 50000h - 5FFFFh SA9 0 1 1 0 X X X 64/32 30000h - 37FFFh 60000h - 6FFFFh

SA10 0 1 1 1 X X X 64/32 38000h - 3FFFFh 70000h - 7FFFFh

(x 16)

Address Range

(x 8)

Address Range

SA11 1 0 0 0 X X X 64/32 40000h - 47FFFh 80000h - 8FFFFh SA12 1 0 0 1 X X X 64/32 48000h - 4FFFFh 90000h - 9FFFFh SA13 1 0 1 0 X X X 64/32 50000h - 57FFFh A0000h - AFFFFh SA14 1 0 1 1 X X X 64/32 58000h - 5FFFFh B0000h - BFFFFh SA15 1 1 0 0 X X X 64/32 60000h - 67FFFh C0000h - CFFFFh SA16 1 1 0 1 X X X 64/32 68000h - 6FFFFh D0000h - DFFFFh SA17 1 1 1 0 X X X 64/32 70000h - 77FFFh E0000h - EFFFFh SA18 1 1 1 1 X X X 64/32 78000h - 7FFFFh F0000h - FFFFFh

Note:

Address range is A18: A-1 in byte mode and A18: A0 in word mode. See the “Word/Byte Configuration” section for more information

(July, 2004, Version 1.1) 7 AMIC Technology, Corp.

Page 9

A29800 Series

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on I/O

7 - I/O0. This mode is primarily

intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires V

ID (11.5V to 12.5 V) on address pin A9. Address

pins A6, A1, and A0 must be as shown in Autoselect Codes (High Voltage Method) table. In addition, when verifying sector protection, the sector address must appear on the

Table 4. A29800 Autoselect Codes (High Voltage Method)

Description

Mode

Manufacturer ID: AMIC L L H X X VID X L X L L X 37h

A18

A12

A11

A10

appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows the remaining address bits that are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on I/O

7 - I/O0.

To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require V

ID. See "Command Definitions" for

details on using the autoselect mode.

A1 A0 I/O

I/O15

A9 A8

A6 A5

I/O7

I/O

Word B3h 0Eh Device ID: A29800

ID X L X L H

X 0Eh

(Top Boot Block)

L L H X X V

Byte

Word B3h 8Fh Device ID: A29800

ID X L X L H

X 8Fh

(Bottom Boot Block)

L L H X X V

Byte

Continuation ID L L H X X VID X L X H H X 7Fh

Sector Protection Verification L L H SA X VID X L X H L

01h

(protected)

00h

(unprotected)

L=Logic Low= VIL, H=Logic High=VIH, SA=Sector Address, X=Don’t Care.

(July, 2004, Version 1.1) 8 AMIC Technology, Corp.

Page 10

A29800 Series

Sector Protection/Unprotection

The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection must be implemented using programming equipment. The procedure requires a high voltage (V

ID) on address pin A9 and the control pins.

The device is shipped with all sectors unprotected. It is possible to determine whether a sector is protected or unprotected. See "Autoselect Mode" for details.

START

RESET = VID

(Note 1)

Hardware Data Protection

The requirement of command unlocking sequence for programming or erasing provides data protection against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during

CC power-up transitions, or from system noise. The device

V is powered up to read array data to avoid accidentally writing data to the array.

Write Pulse "Glitch" Protection

Noise pulses of less than 5ns (typical) on OE, CE or WE do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE=VIL,

= VIH or WE = VIH. To initiate a write cycle, CE and

must be a logical zero while OE is a logical one.

Power-Up Write Inhibit

= CE = VIL and OE = VIH during power up, the

device does not accept commands on the rising edge of

. The internal state machine is automatically reset to

reading array data on the initial power-up.

Perform Erase or

Program Operations

RESET = VIH

Temporary Sector

Unprotect

Completed (Note 2)

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once again.

Figure 1. Temporary Sector Unprotect Operation

Temporary Sector Unprotect

This feature allows temporary unprotection of previous protected sectors to change data in-system. The Sector

Unprotect mode is activated by setting the V

ID. During this mode, formerly protected sectors can be

RESET

programmed or erased by selecting the sector addresses. Once V

ID is removed from the

RESET

pin, all the previously protected sectors are protected again. Figure 1 shows the algorithm, and the Temporary Sector Unprotect diagram

shows the timing waveforms, for this feature.

(July, 2004, Version 1.1) 9 AMIC Technology, Corp.

pin to

Page 11

A29800 Series

Command Definitions

Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data.

All addresses are latched on the falling edge of whichever happens later. All data is latched on the rising

edge of appropriate timing diagrams in the "AC Characteristics"

section.

or CE, whichever happens first. Refer to the

or CE,

Reading Array Data

The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See "Erase Suspend/Erase Resume Commands" for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if I/O autoselect mode. See the "Reset Command" section, next. See also "Requirements for Reading Array Data" in the "Device Bus Operations" section for more information. The Read Operations table provides the read parameters, and Read Operation Timings diagram shows the timing diagram.

5 goes high, or while in the

Reset Command

Writing the reset command to the device resets the device to reading array data. Address bits are don't care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend).

5 goes high during a program or erase operation, writing

If I/O the reset command returns the device to reading array data (also applies during Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. The Command Definitions table shows the address and data requirements. This method is an alternative to that shown in the Autoselect Codes (High Voltage Method) table, which is intended for PROM programmers and requires V address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code and another read cycle at XX03h retrieves the continuation code. A read cycle at address XX01h in word mode (or 02h in byte mode) returns the device code. A read cycle containing a sector address (SA) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. Refer to the Sector Address tables for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data.

ID on

Word/Byte Program Command Sequence

The system may program the device by word or byte, depending on the state of the

four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verify the programmed cell margin. Table 5 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are longer latched. The system can determine the status of the

program operation by using I/O Operation Status” for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Not that a hardware reset immediately terminates the programming operation. The Byte Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set I/O5

to “1”, or cause the operation was successful. However, a succeeding read will show that the data is still “0”. Only erase operations can

convert a “0” to a “1”.

Polling algorithm to indicate the

Data

pin. Programming is a

BYTE

7, I/O6, or RY/

. See “White

(July, 2004, Version 1.1) 10 AMIC Technology, Corp.

Page 12

A29800 Series

START

Write Program

Command Sequence

Embedded

Program

algorithm in

progress

Data Poll

from System

Verify Data ?

Yes

Increment Address

Last Address ?

Yes

Programming

Completed

Note : See the appropriate Command Definitions table for program command sequence.

Figure 2. Program Operation

Chip Erase Command Sequence

Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The Command Definitions table shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Embedded Erase algorithm are ignored. The system can determine the status of the erase operation by using I/O "Write Operation Status" for information on these status bits.

7, I/O6, or I/O2. See

When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Figure 3 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in "AC Characteristics" for parameters, and to the Chip/Sector Erase Operation Timings for timing waveforms.

Sector Erase Command Sequence

Sector erase is a six-bus-cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. The Command Definitions table shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase timeout of 50µs begins. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50µs, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50µs, the system need not monitor I/O command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. The system can monitor I/O3 to determine if the sector erase timer has timed out. (See the " I/O

3: Sector Erase Timer"

section.) The time-out begins from the rising edge of the final

pulse in the command sequence.

Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using I/O

7, I/O6, or I/O2. Refer to "Write

Operation Status" for information on these status bits. Figure 3 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the "AC Characteristics" section for parameters, and to the Sector Erase Operations Timing diagram for timing waveforms.

3. Any

(July, 2004, Version 1.1) 11 AMIC Technology, Corp.

Page 13

A29800 Series

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are "don't cares" when writing the Erase Suspend command. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors produces status data on I/O

- I/O0. The system can use I/O7, or I/O6 and I/O2 together, to determine if a sector is actively erasing or is erasesuspended. See "Write Operation Status" for information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within nonsuspended sectors. The system can determine the status of the program operation using the I/O

7 or I/O6 status bits, just

as in the standard program operation. See "Write Operation Status" for more information. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See "Autoselect Command Sequence" for more information. The system must write the Erase Resume command (address bits are "don't care") to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing.

Note :

1. See the appropriate Command Definitions table for erase command sequences.

2. See "I/O

: Sector Erase Timer" for more information.

Figure 3. Erase Operation

START

Write Erase

Command Sequence

Data Poll

from System

Data = FFh ?

Yes

Erasure Completed

Embedded Erase algorithm in progress

(July, 2004, Version 1.1) 12 AMIC Technology, Corp.

Page 14

A29800 Series

Table 5. A29800 Command Definitions

Command Sequence

(Note 1)

Read (Note 6) 1 RA RD Reset (Note 7) 1 XXX F0

Manufacturer ID

Device ID, Top Boot Block

Device ID, Bottom Boot Block

Continuation ID

Autoselect (Note 8)

Sector Protect Verify

(Note 9)

Program

Chip Erase

Sector Erase Erase Suspend (Note 9) 1 XXX B0

Erase Resume (Note 10) 1 XXX 30

Word

Byte

Word

Byte

Word

Byte

Word Byte

Word

Byte Word

Byte

Word

Byte

Word

Byte

First Second Third Fourth Fifth Sixth

Cycles

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

555

AAA 555

AAA 555 2AA 555 X01

AAA 555

AAA

555

AAA 555 2AA

AAA

2AA 555 2AA

555

555 2AA 555 2AA

555

2AA 555

555

Bus Cycles (Notes 2 - 5)

555

90 X00 37

555

A0 PA PD

555

AAA

X01

X02

X03 X06

(SA)

X02

(SA)

X04

555 AAA 555 AAA

B30E

B38F

XX00 XX01

00 01

2AA

555 2AA 555

55 SA 30

555 AAA

Legend: X = Don't care RA = Address of the memory location to be read. RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the

whichever happens later.

PD = Data to be programmed at location PA. Data la tches on th e rising edge o f SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A18 - A12 select a unique sector.

Note:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all bus cycles are write operation.

4. Address bits A18 - A11 are don't cares for unlock and command cycles, unless SA or PA required.

5. No unlock or command cycles required when reading array data.

6. The Reset command is required to return to reading array data when device is in the autoselect mod e, or if I/O (while the device is providing status data).

7. The fourth cycle of the autoselect command sequence is a read cycle.

8. The data is 00h for an unprotected sector and 01h for a protected sector. See "Au toselect Command Seq uence" for more information.

9. The sy stem may read and p rogram in non-e rasing secto rs, o r en te r the au to select mode , w hen in the Era se Suspend mode .

10. The Erase Resume command is valid only during the Erase Suspend mode.

(July, 2004, Version 1.1) 13 AMIC Technology, Corp.

or CE pulse, whichever happens first.

or CE pulse,

5 goes high

Page 15

A29800 Series

Write Operation Status

Several bits, I/O2, I/O3, I/O5, I/O6, I/O7, RY/

are provided in

the A29800 to determine the status of a write operation. Table 6 and the following subsections describe the functions

of these status bits. I/O

7, I/O6 and RY/BY each offer a

method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first.

I/O7:

The

Polling

Data

Polling bit, I/O7, indicates to the host system

Data

whether an Embedded Algorithm is in progress or completed, or whether the device is in Erase Suspend.

Polling is valid after the rising edge of the final

pulse in

Data

the program or erase command sequence. During the Embedded Program algorithm, the device outputs

7 the complement of the datum programmed to I/O7.

on I/O This I/O

7 status also applies to programming during Erase

Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to I/O

The system must provide the program address to read valid status information on I/O

protected sector,

7. If a program address falls within a

Polling on I/O7 is active for

Data

approximately 2µs, then the device returns to reading array data.

During the Embedded Erase algorithm, produces a "0" on I/O

7. When the Embedded Erase algorithm

Data

Polling

is complete, or if the device enters the Erase Suspend mode,

Polling produces a "1" on I/O7.This is analogous to the

Data

complement/true datum output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to "1"; prior to this, the device outputs the "complement," or "0." The system must provide an address within any of the sectors selected for erasure to read valid status information on I/O

After an erase command sequence is written, if all sectors selected for erasing are protected,

Polling on I/O7 is

Data

active for approximately 100µs, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. When the system detects I/O complement to true data, it can read valid data at I/O on the following read cycles. This is because I/O change asynchronously with I/O

) is asserted low. The

(

7 has changed from the

7 - I/O0

7 may

0 - I/O6 while Output Enable

Polling Timings (During

Data

Embedded Algorithms) figure in the "AC Characteristics" section illustrates this. Table 6 shows the outputs for

Polling on I/O

7. Figure 4 shows the

Polling algorithm.

Data

START

Read I/O7-I/O

Address = VA

I/O7 = Data ?

Note :

1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address.

2. I/O

should be rechecked even if I/O5 = "1" because

I/O

may change simultaneously with I/O5.

I/O5 = 1?

Read I/O7 - I/O

Address = VA

I/O7 = Data ?

FAIL

Yes

PASS

Figure 4. Data Polling Algorithm

(July, 2004, Version 1.1) 14 AMIC Technology, Corp.

Page 16

A29800 Series

RY/

: Read/

Busy

The RY/BY is a dedicated, open-drain output pin that indicates whether an Embedded algorithm is in progress or

complete. The RY/ the final RY/

is an open-drain output, several RY/BY pins can be

status is valid after the rising edge of

pulse in the command sequence. Since

tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode.

Table 6 shows the outputs for RY/

. Refer to “

RESET

Timings”, “Timing Waveforms for Program Operation” and “Timing Waveforms for Chip/Sector Erase Operation” for more information.

I/O6: Toggle Bit I

Toggle Bit I on I/O6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge

of the final the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause I/O

(The system may use either OE or CE to control the read cycles.) When the operation is complete, I/O After an erase command sequence is written, if all sectors

selected for erasing are protected, I/O approximately 100µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use I/O whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), I/O device enters the Erase Suspend mode, I/O However, the system must also use I/O sectors are erasing or erase-suspended. Alternatively, the

system can use I/O Polling"). If a program address falls within a protected sector, I/O toggles for approximately 2µs after the program command sequence is written, then returns to reading array data. I/O

6 also toggles during the erase-suspend-program mode,

and stops toggling once the Embedded Program algorithm is complete. The Write Operation Status table shows the outputs for Toggle Bit I on I/O algorithm, and to the Toggle Bit Timings figure in the "AC Characteristics" section for the timing diagram. The I/O

6 figure shows the differences between I/O2 and I/O6 in

I/O graphical form. See also the subsection on " I/O II".

pulse in the command sequence (prior to

6 to toggle.

6 stops toggling.

6 toggles for

6 and I/O2 together to determine

6 toggles. When the

6 stops toggling.

2 to determine which

7 (see the subsection on " I/O7 :

6. Refer to Figure 5 for the toggle bit

2: Toggle Bit

Data

2 vs.

I/O2: Toggle Bit II

The "Toggle Bit II" on I/O2, when used with I/O6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the

rising edge of the final

pulse in the command

sequence.

2 toggles when the system reads at addresses within

I/O those sectors that have been selected for erasure. (The

system may use either cycles.) But I/O

2 cannot distinguish whether the sector is

actively erasing or is erase-suspended. I/O

to control the read

6, by comparison,

indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 6 to compare outputs for I/O

2 and I/O6.

Figure 5 shows the toggle bit algorithm in flowchart form, and the section " I/O also the " I/O

2: Toggle Bit II" explains the algorithm. See

6: Toggle Bit I" subsection. Refer to the Toggle

Bit Timings figure for the toggle bit timing diagram. The I/O vs. I/O

6 figure shows the differences between I/O2 and I/O6 in

graphical form.

Reading Toggle Bits I/O6, I/O2

Refer to Figure 5 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read

7 - I/O0 at least twice in a row to determine whether a

I/O toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on I/O read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of I/O on I/O

5). If it is, the system should then determine again

whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as I/O is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines

that the toggle bit is toggling and I/O system may continue to monitor the toggle bit and I/O through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure

5).

7 - I/O0 on the following

5 is high (see the section

5 went high. If the toggle bit

5 has not gone high. The

(July, 2004, Version 1.1) 15 AMIC Technology, Corp.

Page 17

A29800 Series

I/O5: Exceeded Timing Limits

I/O5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under thes e conditions I/O

5 produces a "1." This is a failure condition that

indicates the program or erase cycle was not successfully completed. The I/O

5 failure condition may appear if the system tries to

program a "1 "to a location that is previously programmed t o "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, I/O

produces a "1." Under both these conditions, the system must issue the reset command to return the device to reading array data.

I/O3: Sector Erase Timer

After writing a sector erase command sequence, the system may read I/O operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out is complete, I/O ignore I/O between additional sector erase commands will always be less than 50µs. See also the "Sector Erase Command Sequence" section. After the sector erase command sequence is written, the

system should read the status on I/O (Toggle Bit 1) to ensure the device has accepted the

command sequence, and then read I/O internally controlled erase cycle has begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If I/O accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of I/O subsequent sector erase command. If I/O second status check, the last command might not have been accepted. Table 6 shows the outputs for I/O

3 to determine whether or not an erase

3 switches from "0" to "1." The system may

3 if the system can guarantee that the time

7 (

3 is "0", the device will

3 prior to and following each

Polling) or I/O6

Data

3. If I/O3 is "1", the

3 is high on the

START

Read I/O7-I/O

Toggle Bit

= Toggle ?

I/O5 = 1?

Read I/O7 - I/O

Twice

Toggle Bit

= Toggle ?

Program/Erase

Operation Not

Commplete, Write

Reset Command

Yes

(Note 1)

(Notes 1,2)

Operation Complete

Program/Erase

Notes :

1. Read toggle bit twice to determine whether or not it is toggling. See text.

2. Recheck toggle bit because it may stop toggling as I/O changes to "1". See text.

Figure 5. Toggle Bit Algorithm

(July, 2004, Version 1.1) 16 AMIC Technology, Corp.

Page 18

A29800 Series

Table 6. Write Operation Status

Operation

I/O7 I/O6 I/O5 I/O3 I/O2

(Note 1) (Note 2) (No t e 1)

Standard Mode

Erase Suspend Mode

Embedded Program Algorithm

7I/O

Toggle 0 N/A No toggle 0

Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0 Reading within Erase

Suspended Sector Reading within Non-Erase

Suspend Sector Erase-Suspend-Program

1 No toggle 0 N/A Toggle 1

Data Data Data Data Data 1

7I/O

Toggle 0 N/A N/A 0

Notes:

1. I/O

7 and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

2. I/O

5 switches to “1” when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “I/O5: Exceeded Timing Limits” for more information.

Maximum Negative Input Overshoot

20ns 20ns

+0.8V

-0.5V

RY/

-2.0V

Maximum Positive Input Overshoot

VCC+2.0V

VCC+0.5V

2.0V

20ns

20ns20ns

(July, 2004, Version 1.1) 17 AMIC Technology, Corp.

Page 19

A29800 Series

DC Characteristics

TTL/NMOS Compatible Parameter

Symbol

Parameter Description

ILI Input Load Current

ILIT

ILO

A9, Output Leakage Current

RESET

Input Load Current

ICC1 VCC Active Re ad Current

(Notes 1, 2)

ICC2

VCC Active Write (Program/Erase)

Current (Notes 2, 3, 4)

ICC3

VCC Standby Current (Note 2)

VIL Input Low Level VIH Input High Level

VID

Voltage for Autoselect and

Temporary Unprotect Sector VOL Output Low Voltage VOH

Output High Voltage

CMOS Compatible

Parameter

Symbol

Parameter Description

ILI Input Load Current

ILIT

ILO

ICC1

A9,

Output Leakage Current

VCC Active Read Current

RESET

Input Load Current

(Notes 1,2) ICC2

VCC Active Program/Erase Current

(Notes 2,3,4) ICC3 VCC Standby Current (Notes 2, 5)

VIL Input Low Level VIH Input High Level

VID

Voltage for Autoselect and

Temporary Sector Unprotect VOL Output Low Voltage

VOH1 VOH2

Output High Voltage

Test Description

IN = VSS to VCC. VCC = VCC Max

VCC = VCC Max, A9, V

RESET

OUT = VSS to VCC. VCC = VCC Max

= VIL, OE = VIH

= VIL, OE =VIH

= VIH,

RESET

=12.5V

= VCC ± 0.5V

VCC = 5.25 V I

OL = 12mA, VCC = VCC Min

OH = -2.5 mA, VCC = VCC Min

Test Description

IN = VSS to VCC, VCC = VCC Max

V VCC = VCC Max, A9, V

RESET

OUT = VSS to VCC, VCC = VCC Max

= VIL, OE = VIH

RESET

= 12.5V

= VCC ± 0.5 V

Min.

Typ.

Max.

20 30 mA

-0.5

2.0

10.5

0.4

VCC+0.5 V

2.4

Min.

Typ.

Max. Unit

-0.5

0.7 x VCC

VCC+0.3

±1.0 µA

100

±1.0

40 mA

1.0 mA

0.8

12.5

0.45

±1.0

±1.0 µA

40 mA

0.8

VCC = 5.25 V 10.5 12.5 V

OL = 12.0 mA, VCC = VCC Min

OH = -2.5 mA, VCC = VCC Min

I I

OH = -100 µA. VCC = VCC Min

0.85 x VCC VCC-0.4

0.45

Unit

µA

V V

µA µA

µA

V V

V V V

Notes for DC characteristics (both tables):

1. The I

CC current listed includes both the DC operation current and the frequency dependent component (at 6 MHz).

The frequency component typically is less than 2 mA/MHz, withOEat VIH.

2. Maximum I

CC active while Embedded Algorithm (program or erase) is in progress.

3. I

CC specifications are tested with VCC = VCC max.

4. Not 100% tested.

5. For CMOS mode only, I

CC3 = 20µA max at extended temperatures (> +85°C).

(July, 2004, Version 1.1) 18 AMIC Technology, Corp.

Page 20

A29800 Series

AC Characteristics

Read Only Operations

Parameter Symbols Speed

JEDEC Std

tAVAV tRC Read Cycle Time (Note 2) Min. 55 70 90 ns tAVQV tACC Address to Output Delay

tELQV tCE Chip Enable to Output Delay

tGLQV tOE Output Enable to Output Delay Max. 30 30 35 ns

Output Enable Hold Time (Note 2)

tEHQZ tDF Chip Enable to Output High Z Max. 18 20 20 ns tGHQZ tDF Output Enable to Output High Z

(Notes 1,2)

tAXQX tOH

Notes:

1. Output driver disable time.

2. Not 100% tested.

Output Hold Time from Addresses,

or OE, Whichever Occurs First

Description Test Setup

-55 -70 -90

Max. 55 70 90 ns

Read Min. 0 0 0 ns tOEH

Toggle and

Polling

Data

= VIL

Min. 10 10 10 ns

18 20 20 ns

Min. 0 0 0 ns

Unit

(July, 2004, Version 1.1) 19 AMIC Technology, Corp.

Page 21

A29800 Series

Timing Waveforms for Read Only Operation

Addresses Addresses Stable

ACC

OEH

Output

RESET

RY/BY

AC Characteristics Hardware Reset (

Parameter

JEDEC Std

Note: Not 100% tested.

READY

t t

RESET

Algorithms) to Read or Write (See Note)

RESET

Algorithms) to Read or Write (See Note)

RESET RESET

RY/

High-Z

)

Description Test Setup All Speed Options Unit

Pin Low (During Embedded

Pin Low (Not During Embedded

Pulse Width High Time Before Read (See Note)

Recovery Time

Output Valid

Max 20

Max 500 ns

Min 500 ns Min 50 ns Min 0 ns

High-Z

µs

(July, 2004, Version 1.1) 20 AMIC Technology, Corp.

Page 22

A29800 Series

RESET

Timings

RY/BY

CE, OE

RESET

Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

Ready

RY/BY

CE, OE

RESET

~ ~

(July, 2004, Version 1.1) 21 AMIC Technology, Corp.

Page 23

A29800 Series

Temporary Sector Unprotect

Parameter

JEDEC Std

Note: Not 100% tested.

Temporary Sector Unprotect Timing Diagram

VIDR VID Rise and Fall Time (See Note) Min 500 ns

Setup Time for Temporary Sector

RESET

RY/BY

RSP

Unprotect

12V

0 or 5V

RESET

VIDR

Description All Speed Options Unit

Program or Erase Command Sequence

RSP

~ ~

Min 4

0 or 5V

VIDR

µs

AC Characteristics

Word/Byte Configuration (

Parameter All Speed Options

JEDEC Std

tELFL/tELFH tFLQZ

tFHQV

BYTE BYTE

)

BYTE

Description

Switching Low or High

BYTE

Switching Low to Output High-Z Switching High to Output Active

-55 -70 -90

Max 5 ns Max 20 20 20 ns

Min 55 70 90 ns

Unit

(July, 2004, Version 1.1) 22 AMIC Technology, Corp.

Page 24

A29800 Series

Timings for Read Operations

BYTE

Switching

from word to

byte mode

BYTE

Switching

from byte to

word mode

BYTE

I/O0-I/O

I/O

(A-1)

BYTE

I/O0-I/O

I/O

(A-1)

ELFL

ELFH

FLQZ

Data Output

(I/O

I/O

Output

-I/O14)

Data Output

(I/O

-I/O7)

Address Input

Data Output

(I/O

-I/O7)

Data Output

(I/O

-I/O14)

I/O

Address Input

FHQV

Output

Timings for Write Operations

BYTE

Note:

Refer to the Erase/Program Operations table for t

BYTE

The falling edge of the last WE signal

SET

(tAS)

AS and tAH specifications.

HOLD(tAH

)

(July, 2004, Version 1.1) 23 AMIC Technology, Corp.

Page 25

A29800 Series

AC Characteristics

Erase and Program Operations

Parameter Speed

JEDEC

tAVAV tAVWL tWLAX

tDVWH tWHDX

tGHWL

tELWL tCS

tWHEH tWLWH

Std

OES

GHWL

Write Cycle Time (Note 1) Address Setup Time

Address Hold Time

Data Setup Time Data Hold Time

Output Enable Setup Time

Read Recover Time Before Write

(

high to

Setup Time

Hold Time

Write Pulse Width

Description

low)

Min. Min. Min. Min. Min. Min.

Min.

Min. Min. Min.

-55 -70

45 25

Min.

tWHWL tWPH Write Pulse Width High

Max.

Byte Typ. 7

Word Typ. 12

tWHWH1 tWHWH1

Byte Programming Operation

(Note 2)

0 45 30

0 35 20 50

-90

45 45

Unit

ns ns ns ns ns ns

ns ns ns ns

µs

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ. 1 sec

vcs

BUSY

VCC Set Up Time (Note 1)

Recovery Time from RY/ Program/Erase Valid to RY/

Delay

Min.

Min Min

30 30 35

Notes:

1. Not 100% tested.

2. See the "Erase and Programming Performance" section for more information.

µs ns ns

(July, 2004, Version 1.1) 24 AMIC Technology, Corp.

Page 26

A29800 Series

Timing Waveforms for Program Operation

Addresses

Data

RY/BY

VCC

VCS

Program Command Sequence (last two cycles)

555h

GHWL

A0h PD

WPH

BUSY

Read Status Data (last two cycles)

WHWH1

Status

OUT

Note :

1. PA = program addrss, PD = program data, Dout is the true data at the program address.

2. Illustration shows device in word mode.

(July, 2004, Version 1.1) 25 AMIC Technology, Corp.

Page 27

A29800 Series

Timing Waveforms for Chip/Sector Erase Operation

Addresses

Data

RY/BY

VCC

VCS

Erase Command Sequence (last two cycles)

2AAh

GHWL

555h for chip erase

55h 30h

WPH

10h for chip erase

BUSY

WHWH2

Read Status Data

Progress

Complete

Note :

1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operaion Ststus").

2. Illustratin shows device in word mode.

(July, 2004, Version 1.1) 26 AMIC Technology, Corp.

Page 28

A29800 Series

Timing Waveforms for

Addresses

Polling (During Embedded Algorithms)

Data

OEH

ACC

VAVA VA

I/O

- I/O

BUSY

RY/BY

Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data read cycle.

Complement

Status Data

Complement True

Status Data True

Valid Data

High-Z

(July, 2004, Version 1.1) 27 AMIC Technology, Corp.

Page 29

A29800 Series

Timing Waveforms for Toggle Bit (During Embedded Algorithms)

Addresses

VAVA VA

ACC

OEH

I/O6 ,

I/O

RY/BY

BUSY

Valid Status

(first read) (second read) (stop togging)

Note: VA = Valid Address; not required for I/O

read cycle, and array data read cycle.

Valid Status Valid Status Valid Data

6. Illustration shows first two status cycle after command sequence, last status

(July, 2004, Version 1.1) 28 AMIC Technology, Corp.

Page 30

A29800 Series

Timing Waveforms for I/O2 vs. I/O6

Enter

Embedded

Erasing

I/O

Note : Both I/O6 and I/O2 toggle with OE or CE. See the text on I/O6 and I/O2 in the section "Write Operation Statue" for more information.

Erase

Suspend

Erase

and I/O6 toggle with OE and CE

Erase Suspend

Read

Enter Erase

Suspend Program

Erase

Suspend

Program

Resume

Erase Suspend

Read

Erase

AC Characteristics

Erase and Program Operations

Alternate

Controlled Writes

Erase

Complete

Parameter

JEDEC Std

tAVAV tWC Write Cycle Time (Note 1) Min. 55 70 90 ns tAVEL tAS Address Setup Time Min. 0 ns

tELAX tAH Address Hold Time Min. 40 45 45 ns tDVEH tDS Data Setup Time Min. 25 30 45 ns tEHDX tDH Data Hold T ime Min. 0 ns

tOES Output Enable Setup Time Min. 0 ns

tGHEL tGHEL

tWLEL tWS

tEHWH tWH

tELEH tCP

tEHEL tCPH

tWHWH1 tWHWH1

tWHWH2 tWHWH2

Notes:

1. Not 100% tested.

2. See the "Erase and Programming Performance" section for more information.

Read Recover Time Before Write

High to

(

Setup Time

Hold Time

Pulse Width

Pulse Width High

Programming Operation (Note 2)

Sector Erase Operation (Note 2) Typ. 1

Description

Low)

-55 -70 -90

Min. 0 ns

Min. 0 ns Min. 0 ns Min. 30 35 45 ns

Min. 20 20 20 ns

Byte Typ. 7

Word Typ. 12

Speed

Unit

µs

sec

(July, 2004, Version 1.1) 29 AMIC Technology, Corp.

Page 31

A29800 Series

Timing Waveforms for Alternate CE Controlled Write Operation (

RESET

=VIH on A29800)

Addresses

Data

RESET

tRH

555 for program

2AA for erase

tWC

tGHEL

tWS

A0 for program 55 for erase

PA for program SA for sector erase 555 for chip erase

tAS

tWH

tCP

tCPH

tDS

tDH

tAH

tBUSY

PD for program 30 for sector erase 10 for chip erase

Data P olling

tWHWH1 or 2

I/O7

OUT

RY/BY

Note :

1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O

2. Figure indicates the last two bus cycles of the command sequence.

7 = Co mplement o f Data Input, DOUT = Array Data.

Erase and Programming Performance

Parameter Typ. (Note 1) Max. (Note 2) Unit Comments

Sector Erase Time 1.0 8 sec Chip Erase Time (Note 3) 11 sec Byte Programming Time 35 300 Word Programming Time 60 500

Byte Mode 7.2 21.6 sec Chip Programming Time

(Note 3)

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 5.0V VCC, 10, 000 c ycles. Addition all y, progr amming typically assumes checkerboard pattern.

2. Under worst case conditions of 90°C, VCC = 4.5V (4.75V for -55), 100,000 cycles.

3. The typical chip programming time is considerabl y less than the maximum chip programming time listed, since most bytes program faster than the maximum byte program time listed. If the maxim um byte program time given is excee ded, only then does the device set I/O

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h befor e erasure.

5. System-level overhead is the time required to execute the four-bus-c ycle command sequence for pro gramming. See Table 4 for further information on command definitions.

6. The device has a guaranteed minimum erase and progra m cycle endurance of 100,000 cycles.

Word Mode 6.3 18.6 sec

5 = 1. See the section on I/O5 for further information.

µs µs

Excludes 00h programming prior to erasure (Note 4)

Excludes system-level overhead (Note 5)

(July, 2004, Version 1.1) 30 AMIC Technology, Corp.

Page 32

A29800 Series

Latch-up Characteristics

Description Min. Max.

Input Voltage with respect to VSS on all I/O pins

-1.0V

VCC+1.0V VCC Current Input voltage with respect to VSS on all pins except I/O pins

(including A9,

Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at time.

and

RESET

)

TSOP and SOP Pin Capacitance

Parameter Symbol

CIN Input Capacitance

COUT

CIN2

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

Output Capacitance Control Pin Capacitance

A = 25°C, f = 1.0MHz

Parameter Description

Test Setup

Data Retention

Parameter

Minimum Pattern Data Retention Time

Test Conditions

150°C 125°C

IN=0

OUT=0

IN=0

-100 mA

-1.0V

Typ.

8.5

7.5

Min

10 Years 20 Years

Max.

7.5 12

+100 mA

12.5V

Unit

pF pF pF

Unit

(July, 2004, Version 1.1) 31 AMIC Technology, Corp.

Page 33

A29800 Series

Test Conditions

Test Specifications

Test Condition -55 All others Unit

Output Load 1 TTL gate Output Load Capacitance, CL(including jig capacitance) 30 100 pF Input Rise and Fall Times 5 20 ns Input Pulse Levels 0.0 - 3.0 0.45 - 2.4 V Input timing measurement reference levels 1.5 0.8, 2.0 V Output timing measurement reference levels 1.5 0.8, 2.0 V

Test Setup

5.0 V

2.7 K

Ω

Device

Under

Test

6.2 K

Ω

Diodes = IN3064 or Equivalent

(July, 2004, Version 1.1) 32 AMIC Technology, Corp.

Page 34

A29800 Series

Ordering Information Top Boot Sector Flash

Part No.

A29800TM-55 44Pin SOP

A29800TV-55

A29800TM-70 44Pin SOP

A29800TM-70F 44Pin Pb-Free SOP

A29800TV-70 48Pin TSOP

A29800TV-70F

A29800TM-90 44Pin SOP

A29800TV-90

Access Time

(ns)

55 20 30 1

70 20 30 1

90 20 30 1

Active Read

Current

Typ. (mA)

Program/Erase

Current

Typ. (mA)

Standby Current

Typ. (µA)

Package

48Pin TSOP

48Pin Pb-Free TSOP

48Pin TSOP

Bottom Boot Sector Flash

Part No.

Access Time

(ns)

Active Read

Current

Typ. (mA)

Program/Erase

Current

Typ. (mA)

Standby Current

Typ. (µA)

Package

A29800UM-55 44Pin SOP

55 20 30 1

A29800UV-55

A29800UM-70 44Pin SOP

A29800UM-70F 44Pin Pb-Free SOP

70 20 30 1

A29800UV-70 48Pin TSOP

A29800UV-70F

A29800UM-90 44Pin SOP

90 20 30 1

A29800UV-90

48Pin TSOP

48Pin Pb-Free TSOP

48Pin TSOP

(July, 2004, Version 1.1) 33 AMIC Technology, Corp.

Page 35

A29800 Series

Package Information SOP 44L Outline Dimensions unit: inches/mm

Seating Plane

Gauge Plane

0.010"

Detail F

See Detail F

Symbol

A - - 0.118 - - 3.00 A1 0.004 - - 0.10 - A2 0.103 0.106 0.109 2.62 2.69 2.77

b 0.013 0.016 0.020 0.33 0.40 0.50

C 0.007 0.008 0.010 0.18 0.20 0.25

D - 1.122 1.130 - 28.50 28.70

E 0.490 0.496 0.500 12.45 12.60 12.70

e HE 0.620 0.631 0.643 15.75 16.03 16.33

L 0.024 0.032 0.040 0.61 0.80 1.02

L1 - 0.0675 - - 1.71 -

S - - 0.045 - - 1.14

y - - 0.004 - - 0.10

Dimensions in inches Dimensions in mm

Min Nom Max Min Nom Max

- 0.050 - - 1.27 -

0°

8° 0°

8°

Notes:

1. The maximum value of dimension D includes end flash.

2. Dimension E does not includ e resin fins.

3. Dimension S includes end flash.

(July, 2004, Version 1.1) 34 AMIC Technology, Corp.

Page 36

A29800 Series

Package Information TSOP 48L (Type I) Outline Dimensions unit: inches/mm

24 25

Detail "A"

Symbol

A - - 0.047 - - 1.20 A1 0.002 - 0.006 0.05 - 0.15 A2 0.037 0.039 0.042 0.94 1.00 1.06

b 0.007 0.009 0.011 0.18 0.22 0.27

c 0.004 - 0.008 0.12 - 0.20

D 0.779 0.787 0.795 19.80 20.00 20.20 D1 0.720 0.724 0.728 18.30 18.40 18.50

E - 0.472 0.476 - 12.00 12.10

e 0.020 BASIC 0.50 BASIC

L 0.016 0.020 0.024 0.40 0.50 0.60

S 0.011 Typ. 0.28 Typ.

y - - 0.004 - - 0.10

Dimensions in inches Dimensions in mm

Min Nom Max Min Nom Max

0° - 8° 0° - 8°

0.25 Detail "A"

Notes:

1. The maximum value of dimension D includes end flash.

2. Dimension E does not include resin fins.

3. Dimension S includes end flash.

(July, 2004, Version 1.1) 35 AMIC Technology, Corp.