Datasheet A26E001AX, A26E001AV Datasheet (AMICC)

A26E001A

2M and 256K MaskRAM

Document Title

2M and 256K MaskRAM

Revision History

Rev. No. History Issue Date Remark

2.0 Final spec release October 12, 1998 Final

2.1 Change tOE speed from 150ns to 200ns November 20, 1998

(November, 1998, Version 2.1) AMIC Technology, Inc.

A26E001A

2M and 256K MaskRAM

Features

n Power supply range: 1.8V to 3.3V
n Access time: 450 ns (max.)
n Current:

Low power version: Operating: 4mA (max.)

Standby: 10µA (max.)

n Full static operation, no clock or refreshing required
n All inputs and outputs are CMOS compatible
n Common I/O using three-state output
n Data retention voltage: 1.6V (min.)
n Available in 32-pin TSOP and sTSOP packages

n Extended operating temperature range: -25°C to 85°C

General Description

The A26E001A is a low operating current 262,144 x 8 bit
CMOS MASK ROM and 32,768 x 8 bit CMOS SRAM
integrated into one chip. It operates on a low power
supply voltage from 1.8V to 3.3V, with two chip selects
to enable the MASK ROM or SRAM independently.
Inputs and three-state outputs are CMOS compatible and
allow for direct interfacing with common system bus
structures.

Minimum standby power is drawn by this device when

ROMCE

and

RAMCE

of the other input levels.
Data retention is guaranteed at a power supply voltage
as low as 1.6V.

Pin Configuration Pin Description

~

A11

A13
A14
A17

RAMCE

VCC

WE
A16
A15
A12

A9 2
A8

A7
A6
A5
A4

1
3

4
5
6
7
8
9
10
11
12
13
14
15
16

A26E001AV

~

~

~

32

OE

31

A10

30

ROMCE

29

D7
D6

28
27

D5

26

D4

25

D3

24

GND

23

D2

22

D1

21

D0

20

A0

19

A1

18

A2

17

A3

Pin No. Symbol Description

1 - 6, 10 - 20, 31 A0 - A17 Address Inputs

7

9

21 - 23, 25 - 29 D0 - D7 Data Input/Outputs

30

are at a high level, independent

RAMCE

WE

ROMCE

SRAM Enable

Write Enable

ROM Enable

~

A11

A9 2

A8
A13
A14
A17

RAMCE

VCC

WE
A16
A15
A12

A7

A6

A5

A4

1
3

4
5
6
7
8
9
10
11
12
13
14
15
16

A26E001AX

~

~

~

32

OE

31

A10

30

ROMCE

29

D7
D6

28
27

D5

26

D4

25

D3

24

GND

23

D2

22

D1

21

D0

20

A0

19

A1

18

A2

17

A3

32

OE

Output Enable

8 VCC Power Supply

24 GND Ground

(November, 1998, Version 21) 1 AMIC Technology, Inc.

Block Diagram

ROMCE

RAMCE

OE

WE

A0 - A14

A15 - A17

D0 - D7

WE

OE

RAMCE

ROMCE

ADDRESS

BUFFER

DATA
BUFFER
CIRCUIT

CONTROL

CIRCUIT

A0-A14

D0-D7

D0-D7

A0-A14

A15-A17

RAM

ROM

A26E001A

VCC
GND

WE

OE

RAMCE

WE

OE

ROMCE

Truth Table

Mode

Standby H H X X High Z ISB, ISB1

Output Disable L H H X High Z ICCR

ROM Read L H L X DOUT ICCR

Output Disable H L H H High Z ICCS

SRAM Read H L L H DOUT ICCS

SRAM Write H L X L DIN ICCS

Notes:

1. X = H or L

2. A15 - A17 are only valid for ROM.

3. In case that

ROMCE

and

RAMCE

are "L" at the same time, both ROM and SRAM will be disabled.

D0 - D7 Supply Current

(November, 1998, Version 2.1) 2 AMIC Technology, Inc.

A26E001A

Recommended DC Operating Conditions (TA = -25°C to + 85°C)

Symbol Parameter Min. Typ. Max. Unit

VCC Supply Voltage 1.8 3.0 3.3 V

GND Ground 0 0 0 V

VIH Input High Voltage VCC x 0.7 - VCC + 0.3 V

VIL Input Low Voltage -0.3 - VCC x 0.3 V

Absolute Maximum Ratings*

VCC to GND . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V

IN, IN/OUT Volt to GND . . . . . . . . . . -0.5V to VCC + 0.5V

Operating Temperature, Topr . . . . . . . . . -25°C to +85°C

Storage Temperature, Tstg . . . . . . . . . . -55°C to +125°C

Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . . . 0.7W

Soldering Temp. & Time . . . . . . . . . . . . . . 260°C, 10 sec

*Comments

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.

DC Electrical Characteristics (TA = -25°C to + 85°C, VCC = 1.8V to 3.3V)

Symbol Parameter Min. Max. Unit Conditions

ILI

ILO

ICCR ROM Operating Current - 4 mA

ICCS SRAM Operating Current - 4 mA

Input Leakage Current - 1

Output Leakage Current - 1

µA

µA

VIN = GND to VCC

VI/O = GND to VCC

Min. Cycle, Duty = 100%

ROMCE

II/O = 0mA, VIN = VCC or GND

Min. Cycle, Duty = 100%

ROMCE

II/O = 0mA, VIN = VCC or GND

= VIL and

= VIH and

RAMCE

RAMCE

= VIH,

= VIL,

ISB - 50

ISB1

VOL Output Low Voltage - 0.4 V

VOH Output High Voltage VCC - 0.4 - V

(November, 1998, Version 2.1) 3 AMIC Technology, Inc.

Standby Supply Current

- 10

µA

µA

ROMCE

ROMCE
RAMCE

IOL = 200µA

IOH = -200µA

= VIH and

≥ VCC - 0.2V and

≥ VCC - o.2V

RAMCE

= VIH

A26E001A

Capacitance (TA = 25°C, f = 1.0MHz)

Symbol Parameter Min. Max. Unit Conditions

CI* Input Capacitance 6 pF

CO* Input/Output Capacitance 8 pF

* These parameters are sampled and not 100% tested.

TA = 25°C
f = 1.0MHz

AC Characteristics (ROM/SRAM Selection) (TA = -25°C to +85°C, VCC = 1.8V to 3.3V)

Symbol Parameter Min. Max. Unit

tRTS

tSTR

ROMCE

RAMCE

Disable to

Disable to

RAMCE

ROMCE

Enable Time

Enable Time

10 - ns

10 - ns

AC Characteristics (ROM Selected) (TA = -25°C to +85°C, VCC = 1.8V to 3.3V)

Symbol Parameter Min. Max. Unit

tRC Read Cycle Time 500 - ns

tAA Address Access Time - 450 ns

tACE

ROMCE

Chip Enable Access Time

- 450 ns

tOE Output Enable to Output Valid - 200 ns

tCLZ

tOLZ Output Enable to Output in Low Z 10 - ns

tCHZ

tOHZ Output Disable to Output in High Z - 100 ns

tOH Output Hold from Address Change 10 - ns

Notes: tCHZ, and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred

(November, 1998, Version 2.1) 4 AMIC Technology, Inc.

ROMCE

ROMCE

to output voltage levels.

Chip Enable to Output in Low Z

Chip Disable to Output in High Z

10 - ns

- 100 ns

A26E001A

AC Characteristics (SRAM Selected) (TA = -25°C to +85°C, VCC = 1.8V to 3.3V)

Symbol Parameter Min. Max. Unit

Read Cycle

tRC Read Cycle Time 500 - ns

tAA Address Access Time - 450 ns

tACE

tOE Output Enable to Output Valid - 200 ns

tCLZ

tOLZ Output Enable to Output in Low Z 10 - ns

tCHZ

tOHZ Output Disable to Output in High Z - 100 ns

tOH Output Hold from Address Change 10 - ns

Write Cycle

tWC Write Cycle Time 500 - ns

tCW

tAS Address Setup Time 0 - ns

tAW Address Valid to End of Write 220 - ns

RAMCE

RAMCE

RAMCE

RAMCE

Chip Enable Access Time

Chip Enable to Output in Low Z

Chip Disable to Output in High Z

Chip Enable to End of Write

- 450 ns

10 - ns

- 100 ns

220 - ns

tWP Write Pulse Width 200 - ns

tWR Write Recovery Time 0 - ns

tWHZ Write to Output in High Z - 100 ns

tDW Data to Write Time Overlap 100 - ns

tDH Data Hold from Write Time 0 - ns

tOW Output Active from End of Write 10 - ns

Notes: tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not

referred to output voltage levels.

(November, 1998, Version 2.1) 5 AMIC Technology, Inc.

Timing Waveforms (ROM/SRAM Selection)

A26E001A

ROMCE

RAMCE

t

RTS

Timing Waveforms (ROM Selected)

Read from Address (

ADDRESS

INPUTS

DATA OUT

ROMCE

= Active, OE= Active)

t

AA

t

STR

t

RC

t

OH

Read from

ROMCE

OE

DATA OUT

ROMCE

Chip Enable or Output Enable (Address Valid)

t

ACE

t

OE

t

OLZ

t

CLZ

t

CHZ

t

OHZ

(November, 1998, Version 2.1) 6 AMIC Technology, Inc.

Timing Waveforms (SRAM Selected)

A26E001A

Read Cycle 1

Address

RAMCE

D

Read Cycle 2

OE

OUT

(1)

(1, 2, 4)

t

RC

t

AA

t

OE

5

t

OLZ

t

ACE

5

t

CLZ

t

OH

5

t

OHZ

5

t

CHZ

Address

D

OUT

t

RC

t

AA

t

t

OH

OH

(November, 1998, Version 2.1) 7 AMIC Technology, Inc.

Timing Waveforms (SRAM Selected continued)

A26E001A

RAMCE

D

OUT

(1, 3, 4)

t

CLZ

Read Cycle 3

Notes: 1. WE is high for Read Cycle.

2. Device is continuously enabled,

3. Address valid prior to or coincident with

4. OE = VIL.

5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.

Write Cycle 1

(6)

(Write Enable Controlled)

t

ACE

5

RAMCE

= VIL.

RAMCE

transition low.

t

WC

5

t

CHZ

Address

RAMCE

WE

D

D

OUT

t

AW

5

t

CW

(4)

1

t

AS

IN

t

WHZ

2

t

WP

t

DW

7

3

t

WR

t

DH

7

t

OW

(November, 1998, Version 2.1) 8 AMIC Technology, Inc.

Timing Waveforms (SRAM Selected continued)

A26E001A

Write Cycle 2

(6)

(Chip Enable Controlled)

t

WC

Address

t

AW

5

t

CW

RAMCE

WE

D

D

OUT

t

IN

(4)

1

AS

2

t

WP

t

DW

7

t

WHZ

Notes: 1. tAS is measured from the address valid to the beginning of Write.

2. A Write occurs during the overlap (tWP) of a low

3. tWR is measured from the earliest of

4. If the

RAMCE

low transition occurs simultaneously with the WE low transition or after the WE transition,

RAMCE

or WE going high to the end of the Write cycle.

RAMCE

and a low WE .

outputs remain in a high impedance state.

5. tCW is measured from the later of

RAMCE

going low to the end of Write.

6. OE level is high or low.

7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.

3

t

WR

t

DH

(November, 1998, Version 2.1) 9 AMIC Technology, Inc.

AC Test Conditions

Input Pulse Levels 0V, VCC

Input Rise And Fall Time 3 ns

Input and Output Timing Reference Levels VCC/2

Output Load See Figure 1

C

L

30pF

* Including scope and jig.

Figure 1. Output Load

A26E001A

Data Retention Characteristics (TA = -25°C to 85°C)

Symbol Parameter Min. Max. Unit Conditions

VDR VCC for Data Retention 1.6 3.6 V

RAMCE

≥ VCC - 0.2V

VCC = 1.6V,

ICCDR Data Retention Current - 3

µA

RAMCE

≥ VCC - 0.2V

VIN ≥ 0V

tCDR Chip Disable to Data Retention Time 0 - ns

See Retention Waveform

tR Operation Recovery Time tRC - ns

Low VCC Data Retention Waveform

VCC

RAMCE

3.0V

t

CDR

V

IH

DATA RETENTION MODE

VDR ≥ 1.6V

RAMCE ≥ VDR - 0.2V

3.0V
t

R

V

IH

(November, 1998, Version 2.1) 10 AMIC Technology, Inc.

Ordering Information

A26E001A

Part No.

A26E001AV 450 4 10 32L TSOP

A26E001AX 450 4 10 32L sTSOP

Access Time

(ns)

Operation Current

Max. (mA)

Standby Current

Max. (µA)

Package

(November, 1998, Version 2.1) 11 AMIC Technology, Inc.

A26E001A

Package Information

TSOP 32L TYPE I (8 X 20mm) Outline Dimensions unit: inches/mm

D

e

A2

E

H

D

Detail "A"

y

D

c

A1

L

L

E

Detail "A"

S

b

A

θ

Dimensions in inches Dimensions in mm

Symbol

Min Nom Max Min Nom Max

A - - 0.047 - - 1.20
A
A

0.002 - 0.006 0.05 - 0.15

1

0.037 0.039 0.041 0.95 1.00 1.05

2

b 0.007 0.009 0.011 0.18 0.22 0.27

c 0.004 - 0.008 0.11 - 0.20

D 0.720 0.724 0.728 18.30 18.40 18.50

E - 0.315 0.319 - 8.00 8.10

e 0.020 BSC 0.50 BSC

HD 0.779 0.787 0.795 19.80 20.00 20.20

L 0.016 0.020 0.024 0.40 0.50 0.60
LE - 0.032 - - 0.80 -

S - - 0.020 - - 0.50

y - - 0.003 - - 0.08

θ 0°

-

5° 0°

-

5°

Notes:

1. The maximum value of dimension D includes end flash.

2. Dimension E does not include resin fins.

3. Dimension S includes end flash.

(November, 1998, Version 2.1) 12 AMIC Technology, Inc.

A26E001A

Package Information

sTSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions unit: inches/mm

e

0.076MM

D

SEATING PLANE

E

D

1

D

Detail "A"

A2

c

A1

L

L

E

Detail "A"

S

b

A

θ

Dimensions in inches Dimensions in mm

Symbol

A
A1 0.002

Min Nom Max Min Nom Max

- -

0.049

- -

- -

0.05

1.25

- -

A2 0.037 0.039 0.041 0.95 1.00 1.05

b 0.007 0.008 0.009 0.17 0.20 0.23

c 0.0056 0.0059 0.0062 0.142 0.150 0.158

E 0.311 0.315 0.319 7.90 8.00 8.10

e 0.020 TYP 0.50 TYP

D 0.520 0.528 0.535 13.20 13.40 13.60

D1 0.461 0.465 0.469 11.70 11.80 11.90

L 0.012 0.020 0.028 0.30 0.50 0.70
LE 0.0275 0.0315 0.0355 0.700 0.800 0.900

S 0.0109 TYP 0.278 TYP

θ 0° 3° 5° 0° 3° 5°

Notes:

1. The maximum value of dimension D1 includes end flash.

2. Dimension E does not include resin fins.

3. Dimension S includes end flash.

(November, 1998, Version 2.1) 13 AMIC Technology, Inc.