Datasheet A25L80P Datasheet (AMIC)

A25L80P Series

8 Mbit, Low Voltage, Serial Flash Memory

With 75 MHz SPI Bus Interface

Document Title
8 Mbit, Low Voltage, Serial Flash Memory With 75MHz SPI Bus Interface

Revision History

Rev. No.

History Issue Date Remark

0.0 Initial issue May 30, 2005 Preliminary

1.0 Change the package code of part number January 3, 2006 Final

Remove the speed code of part number

Final version release

1.1 Modify the electronic signature on page 1: April 19, 2006

1. Add the JEDEC two-byte signature 2014h

2. Add the RES signature 13h

Add QFN 8L (5 x 6mm) package type

1.2 Add the maximum clock rate of 3.0V~3.6V : 75MHz August 17, 2006

1.3 Add 8-pin DIP and 8-pin SOP(150mil) packages January 17, 2007

Erase 16-pin SOP package

1.4 Reduce the options of protected area size to all sectors March 8, 2007

1.5 Add transient voltage (<20ns) on any pin to ground potential spec. April 24, 2007

(April, 2007, Version 1.5) AMIC Technology Corp.

A25L80P Series

8 Mbit, Low Voltage, Serial Flash Memory

With 75 MHz SPI Bus Interface

FEATURES

 8 Mbit of Flash Memory
 Flexible Sector Architecture (4/4/8/16/32)KB/64x15 KB
 Bulk Erase (8 Mbit) in 10s (typical)
 Sector Erase (512 Kbit) in 1s (typical)
 Page Program (up to 256 Bytes) in 3ms (typical)
 2.7 to 3.6V Single Supply Voltage
 SPI Bus Compatible Serial Interface
 Clock Rate (maximum)

- 50MHz (2.7V~3.6V)

- 75MHz (3.0V~3.6V)

 Deep Power-down Mode 1µA (typical)
 Electronic Signature

- JEDEC Standard Two-Byte Signature (2014h)

- RES Instruction, One-Byte, Signature (13h)

 Package options

- 8-pin SOP (150mil or 209mil), 8-pin DIP (300mil) or 8-pin

QFN

- All Pb-free (Lead-free) products are RoHS compliant

Pin Configurations

GENERAL DESCRIPTION

The A25L80P is an 8 Mbit (1M x 8) Serial Flash Memory,
with advanced write protection mechanisms, accessed by a
high speed SPI-compatible bus.

The memory can be programmed 1 to 256 bytes at a time,
using the Page Program instruction.
The memory is organized as 16 sectors, each containing 256
pages. Each page is 256 bytes wide. Thus, the whole
memory can be viewed as consisting of 4096 pages, or
1,048,576 bytes.
The whole memory can be erased using the Bulk Erase
instruction, or a sector at a time, using the Sector Erase
instruction.

 SO8 Connections  DIP8 Connections  QFN8 Connections

W

V

S
Q

SS

A25L80P

1

8

2

7

3

6

4

5

V

CC

HOLD

C
D

S
Q

W

V

SS

A25L80P

1 8
2 7
3 6
4 5

V

CC

HOLD

C
D

S
Q

W

V

SS

A25L80P

1 8
2 7
3 6
4 5

V

CC

HOLD

C
D

(April, 2007, Version 1.5) 1 AMIC Technology Corp.

A25L80P Series

Block Diagram

HOLD

W

S

C

D

Q

Control Logic

Address register

and Counter

High Voltage

Generator

I/O Shift Register

256 Byte

Data Buffer

Status

Register

FFFFFh

Size of the

read-only

memory area

Pin Descriptions

Pin No. Description

C Serial Clock

D Serial Data Input

Q Serial Data Output

S

W

HOLD

Chip Select

Write Protect

Hold

Y Decoder

00000h

256 Byte (Page Size)

X Decoder

000FFh

Logic Symbol

W

HOLD

C

S

V

CC

A25L80P

QD

Vcc

Vss

Supply Voltage

Ground

V

SS

(April, 2007, Version 1.5) 2 AMIC Technology Corp.

A25L80P Series

SIGNAL DESCRIPTION

Serial Data Output (Q). This output signal is used to transfer

data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).

Serial Data Input (D). This input signal is used to transfer

data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are
latched on the rising edge of Serial Clock (C).

Serial Clock (C). This input signal provides the timing of the

serial interface. Instructions, addresses, or data present at
Serial Data Input (D) are latched on the rising edge of Serial
Clock (C). Data on Serial Data Output (Q) changes after the
falling edge of Serial Clock (C).

Chip Select (S). When this input signal is High, the device

is deselected and Serial Data Output (Q) is at high
impedance. Unless an internal Program, Erase or Write
Status Register cycle is in progress, the device will be in the
Standby mode (this is not the Deep Power-down mode).

SPI MODES

These devices can be driven by a microcontroller with its SPI
peripheral running in either of the two following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising
edge of Serial Clock (C), and output data is available from

Driving Chip Select (
the active power mode.

After Power-up, a falling edge on Chip Select (
prior to the start of any instruction.

Hold (

any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high
impedance, and Serial Data Input (D) and Serial Clock (C)
are Don’t Care. To start the Hold condition, the device must

be selected, with Chip Select (

Write Protect (W). The main purpose of this input signal is

to freeze the size of the area of memory that is protected
against program or erase instructions (as specified by the
values in the BP2, BP1 and BP0 bits of the Status Register).

the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 2,
is the clock polarity when the bus master is in Stand-by mode
and not transferring data:
– C remains at 0 for (CPOL=0, CPHA=0)

– C remains at 1 for (CPOL=1, CPHA=1)

HOLD

). The Hold (

) Low enables the device, placing it in

S

) is required

S

) signal is used to pause

HOLD

) driven Low.

S

(April, 2007, Version 1.5) 3 AMIC Technology Corp.

A25L80P Series

Figure 1. Bus Master and Memory Devices on the SPI Bus

SPI Interface with
(CPOL, CPHA)
= (0, 0) or (1, 1)

Bus Master

(ST6, ST7, ST9,

ST10, Other)

CS3 CS2 CS1

Note: The Write Protect (

W

SDO

SDI

SCK

) and Hold (

CQD

SPI Memory

Device

S W HOLD

) signals should be driven, High or Low as appropriate.

HOLD

CQD

SPI Memory

Device

S W HOLD

CQD

SPI Memory

Device

S W HOLD

Figure 2. SPI Modes Supported

CPOL CPHA

00

11

C

C

D

Q

MSB

MSB

(April, 2007, Version 1.5) 4 AMIC Technology Corp.

A25L80P Series

OPERATING FEATURES
Page Programming

To program one data byte, two instructions are required:
Write Enable (WREN), which is one byte, and a Page
Program (PP) sequence, which consists of four bytes plus
data. This is followed by the internal Program cycle (of
duration t
To spread this overhead, the Page Program (PP) instruction
allows up to 256 bytes to be programmed at a time (changing
bits from 1 to 0), provided that they lie in consecutive
addresses on the same page of memory.

PP

).

Sector Erase and Bulk Erase

The Page Program (PP) instruction allows bits to be reset
from 1 to 0. Before this can be applied, the bytes of memory
need to have been erased to all 1s (FFh). This can be
achieved, a sector at a time, using the Sector Erase (SE)
instruction, or throughout the entire memory, using the Bulk
Erase (BE) instruction. This starts an internal Erase cycle (of
duration t
The Erase instruction must be preceded by a Write Enable
(WREN) instruction.

or tBE).

SE

Polling During a Write, Program or Erase Cycle

A further improvement in the time to Write Status Register
(WRSR), Program (PP) or Erase (SE or BE) can be achieved
by not waiting for the worst case delay (t
The Write In Progress (WIP) bit is provided in the Status
Register so that the application program can monitor its
value, polling it to establish when the previous Write cycle,
Program cycle or Erase cycle is complete.

, tPP, tSE, or tBE).

W

Active Power, Stand-by Power and Deep
Power-Down Modes

When Chip Select (S) is Low, the device is enabled, and in
the Active Power mode.

When Chip Select (
could remain in the Active Power mode until all internal
cycles have completed (Program, Erase, Write Status

Register). The device then goes in to the Stand-by Power
mode. The device consumption drops to I
The Deep Power-down mode is entered when the specific
instruction (the Enter Deep Power-down Mode (DP)
instruction) is executed. The device consumption drops
further to I
specific instruction (the Release from Deep Power-down
Mode and Read Electronic Signature (RES) instruction) is
executed.
All other instructions are ignored while the device is in the
Deep Power-down mode. This can be used as an extra
software protection mechanism, when the device is not in
active use, to protect the device from inadvertent Write,
Program or Erase instructions.

CC2. The device remains in this mode until another

) is High, the device is disabled, but

S

CC1.

Status Register

The Status Register contains a number of status and control
bits that can be read or set (as appropriate) by specific
instructions.

WIP bit. The Write In Progress (WIP) bit indicates whether

the memory is busy with a Write Status Register, Program or
Erase cycle.

WEL bit. The Write Enable Latch (WEL) bit indicates the

status of the internal Write Enable Latch,

BP0 bits.

non-volatile. They define the size of the area to be software
protected against Program and Erase instructions.

SRWD bit. The Status Register Write Disable (SRWD) bit is

operated in conjunction with the Write Protect (
The Status Register Write Disable (SRWD) bit and Write

Protect (
Hardware Protected mode. In this mode, the non-volatile bits
of the Status Register (SRWD, BP2, BP1, BP0) become
read-only bits.

The Block Protect (BP2, BP1, BP0) bits are

) signal allow the device to be put in the

W

BP2, BP1, and

) signal.

W

Protection Modes

The environments where non-volatile memory devices are
used can be very noisy. No SPI device can operate correctly
in the presence of excessive noise. To help combat this, the
A25L80P boasts the following data protection mechanisms:

 Power-On Reset and an internal timer (t

protection against inadvertant changes while the power
supply is outside the operating specification.

 Program, Erase and Write Status Register instructions

are checked that they consist of a number of clock pulses
that is a multiple of eight, before they are accepted for
execution.

 All instructions that modify data must be preceded by a

Write Enable (WREN) instruction to set the Write Enable
Latch (WEL) bit. This bit is returned to its reset state by
the following events:

- Power-up

- Write Disable (WRDI) instruction completion

- Write Status Register (WRSR) instruction completion

- Page Program (PP) instruction completion

- Sector Erase (SE) instruction completion

- Bulk Erase (BE) instruction completion

 The Block Protect (BP2, BP1, BP0) bits allow part of the

memory to be configured as read-only. This is the
Software Protected Mode (SPM).

 The Write Protect (

(BP2, BP1, BP0) bits and Status Register Write Disable
(SRWD) bit to be protected. This is the Hardware
Protected Mode (HPM).

 In addition to the low power consumption feature, the

Deep Power-down mode offers extra software protection
from inadvertant Write, Program and Erase instructions,
as all instructions are ignored except one particular
instruction (the Release from Deep Power-down
instruction).

) signal allows the Block Protect

W

) can provide

PUW

(April, 2007, Version 1.5) 5 AMIC Technology Corp.

A25L80P Series

Table 1. Protected Area Sizes

Status Register Content Memory Content

BP2 Bit BP1 Bit BP0 Bit Protected Area Unprotected Area

0 0 0 none All sectors1 (sixteen sectors: 0 to 15)

1 1 1 All sectors (sixteen sectors: 0 to 15) none

Note: 1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.

2. The sector 0 include sector 0-0, sector 0-1, sector 0-2 and sector 0-3.

Hold Condition

The Hold (
communications with the device without resetting the

clocking sequence. However, taking this signal Low does not
terminate any Write Status Register, Program or Erase cycle
that is currently in progress.
To enter the Hold condition, the device must be selected,

with Chip Select (
The Hold condition starts on the falling edge of the Hold

(

HOLD

(C) being Low (as shown in Figure 3.).
The Hold condition ends on the rising edge of the Hold

(

HOLD

(C) being Low.
If the falling edge does not coincide with Serial Clock (C)
being Low, the Hold condition starts after Serial Clock (C)
next goes Low. Similarly, if the rising edge does not coincide

HOLD

) signal, provided that this coincides with Serial Clock

) signal, provided that this coincides with Serial Clock

) signal is used to pause any serial

) Low.

S

with Serial Clock (C) being Low, the Hold condition ends
after Serial Clock (C) next goes Low. This is shown in Figure

3.
During the Hold condition, the Serial Data Output (Q) is high
impedance, and Serial Data Input (D) and Serial Clock (C)
are Don’t Care.

Normally, the device is kept selected, with Chip Select (
driven Low, for the whole duration of the Hold condition. This

is to ensure that the state of the internal logic remains
unchanged from the moment of entering the Hold condition.

If Chip Select (S) goes High while the device is in the Hold
condition, this has the effect of resetting the internal logic of
the device. To restart communication with the device, it is

necessary to drive Hold (

Chip Select (
back to the Hold condition.

) Low. This prevents the device from going

S

) High, and then to drive

HOLD

Figure 3. Hold Condition Activation

C

)

S

HOLD

Hold

Condition

(standard use)

(April, 2007, Version 1.5) 6 AMIC Technology Corp.

Hold

Condition

(non-standard use)

A25L80P Series

MEMORY ORGANIZATION

The memory is organized as:

 1,048,576 bytes (8 bits each)
 16 sectors (one (4/4/8/16/32) Kbytes & 64x15 Kbytes

each)

 4096 pages (256 bytes each).

Table 2. Memory Organization

Sector Sector Size (Kbytes) Address Range

15 64 F0000h FFFFFh

14 64 E0000h EFFFFh

13 64 D0000h DFFFFh

12 64 C0000h CFFFFh

11 64 B0000h BFFFFh

10 64 A0000h AFFFFh

9 64 90000h 9FFFFh

8 64 80000h 8FFFFh

Each page can be individually programmed (bits are
programmed from 1 to 0). The device is Sector or Bulk
Erasable (bits are erased from 0 to 1) but not Page Erasable.

7 64 70000h 7FFFFh

6 64 60000h 6FFFFh

5 64 50000h 5FFFFh

4 64 40000h 4FFFFh

3 64 30000h 3FFFFh

2 64 20000h 2FFFFh

1 64 10000h 1FFFFh

0-4 32 08000h 0FFFFh

0-3 16 04000h 07FFFh

0-2 8 02000h 03FFFh

0-1 4 01000h 01FFFh

0-0 4 00000h 00FFFh

(April, 2007, Version 1.5) 7 AMIC Technology Corp.

A25L80P Series

INSTRUCTIONS

All instructions, addresses and data are shifted in and out of
the device, most significant bit first.
Serial Data Input (D) is sampled on the first rising edge of

Serial Clock (C) after Chip Select (
the one-byte instruction code must be shifted in to the device,
most significant bit first, on Serial Data Input (D), each bit

being latched on the rising edges of Serial Clock (C).
The instruction set is listed in Table 3.
Every instruction sequence starts with a one-byte instruction
code. Depending on the instruction, this might be followed by
address bytes, or by data bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read Data Bytes
at Higher Speed (Fast_Read), Read Status Register (RDSR)
or Release from Deep Power-down, Read Device
Identification and Read Electronic Signature (RES)
instruction, the shifted-in instruction sequence is followed by

a data-out sequence. Chip Select (

) is driven Low. Then,

S

) can be driven High

S

after any bit of the data-out sequence is being shifted out.
In the case of a Page Program (PP), Sector Erase (SE), Bulk
Erase (BE), Write Status Register (WRSR), Write Enable
(WREN), Write Disable (WRDI) or Deep Power-down (DP)

instruction, Chip Select (
byte boundary, otherwise the instruction is rejected, and is

not executed. That is, Chip Select (

when the number of clock pulses after Chip Select (
driven Low is an exact multiple of eight.

All attempts to access the memory array during a Write
Status Register cycle, Program cycle or Erase cycle are
ignored, and the internal Write Status Register cycle,
Program cycle or Erase cycle continues unaffected.

Table 3. Instruction Set

Instruction Description One-byte Instruction Code

) must be driven High exactly at a

S

) must driven High

S

Address

Bytes

Dummy

Bytes

Data Bytes

) being

S

WREN Write Enable 0000 0110 06h 0 0 0

WRDI Write Disable 0000 0100 04h 0 0 0

RDSR Read Status Register 0000 0101 05h 0 0 1 to ∞

WRSR Write Status Register 0000 0001 01h 0 0 1

READ Read Data Bytes 0000 0011 03h 3 0 1 to ∞

FAST_READ Read Data Bytes at Higher Speed 0000 1011 0Bh 3 1 1 to ∞

PP Page Program 0000 0010 02h 3 0 1 to 256

SE Sector Erase 1101 1000 D8h 3 0 0

BE Bulk Erase 1100 0111 C7h 0 0 0

DP Deep Power-down 1011 1001 B9h 0 0 0

RDID Read Device Identification 1001 1111 9Fh 0 0 1 to 4

Release from Deep Power-down,

RES

and Read Electronic Signature

Release from Deep Power-down

1010 1011 ABh

0 3 1 to ∞

0 0 0

(April, 2007, Version 1.5) 8 AMIC Technology Corp.

A25L80P Series

Write Enable (WREN)

The Write Enable (WREN) instruction (Figure 4.) sets the
Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set prior to every
Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and
Write Status Register (WRSR) instruction.

Figure 4. Write Enable (WREN) Instruction Sequence

S

01 23 45 6 7

C

Instruction

D

Q

High Impedance

The Write Enable (WREN) instruction is entered by driving
Chip Select (

driving Chip Select (

) Low, sending the instruction code, and then

S

) High.

S

Write Disable (WRDI)

The Write Disable (WRDI) instruction (Figure 5.) resets the

Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by driving

S

Chip Select (
driving Chip The Write Enable Latch (WEL) bit is reset under
the following conditions:

) Low, sending the instruction code, and then

Figure 5. Write Disable (WRDI) Instruction Sequence

S

01 23 45 6 7

C

Instruction

D

Q

High Impedance

﹣ Power-up

﹣ Write Disable (WRDI) instruction completion
﹣ Write Status Register (WRSR) instruction completion
﹣ Page Program (PP) instruction completion
﹣ Sector Erase (SE) instruction completion
﹣ Bulk Erase (BE) instruction completion

(April, 2007, Version 1.5) 9 AMIC Technology Corp.

A25L80P Series

Read Status Register (RDSR)

The Read Status Register (RDSR) instruction allows the
Status Register to be read. The Status Register may be read
at any time, even while a Program, Erase or Write Status
Register cycle is in progress. When one of these cycles is in
progress, it is recommended to check the Write In Progress
(WIP) bit before sending a new instruction to the device. It is
also possible to read the Status Register continuously, as
shown in Figure 6.

Table 4. Status Register Format

b0b7

SRWD 0 0 BP2 BP1 BP0 WEL WIP

Status Register

Write Protect

Block Protect Bits

Write Enable Latch Bit

Write In Progress Bit

The status and control bits of the Status Register are as
follows:

WIP bit. The Write In Progress (WIP) bit indicates whether

the memory is busy with a Write Status Register, Program or
Erase cycle. When set to 1, such a cycle is in progress, when
reset to 0 no such cycle is in progress.

WEL bit. The Write Enable Latch (WEL) bit indicates the

status of the internal Write Enable Latch. When set to 1 the
internal Write Enable Latch is set, when set to 0 the internal
Write Enable Latch is reset and no Write Status Register,
Program or Erase instruction is accepted.

BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits

are non-volatile. They define the size of the area to be
software protected against Program and Erase instructions.
These bits are written with the Write Status Register (WRSR)
instruction. When one or both of the Block Protect (BP2, BP1,
BP0) bits is set to 1, the relevant memory area (as defined in
Table 1.) becomes protected against Page Program (PP)
and Sector Erase (SE) instructions. The Block Protect (BP2,
BP1, BP0) bits can be written provided that the Hardware
Protected mode has not been set. The Bulk Erase (BE)
instruction is executed if, and only if, both Block Protect (BP2,
BP1, BP0) bits are 0.

SRWD bit. The Status Register Write Disable (SRWD) bit is

operated in conjunction with the Write Protect (
The Status Register Write Disable (SRWD) bit and Write

Protect (
Hardware Protected mode (when the Status Register Write

Disable (SRWD) bit is set to 1, and Write Protect (
driven Low). In this mode, the non-volatile bits of the Status
Register (SRWD, BP2, BP1, BP0) become read-only bits and
the Write Status Register (WRSR) instruction is no longer
accepted for execution.

) signal allow the device to be put in the

W

Figure 6. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence

S

) signal.

W

W

) is

01234567

C

Instruction

D

Q

High Impedance

810911121314 15

Status Register Out

5

67

MSB MSB

01

Status Register Out

345677

2

01234

(April, 2007, Version 1.5) 10 AMIC Technology Corp.

A25L80P Series

Write Status Register (WRSR)

The Write Status Register (WRSR) instruction allows new
values to be written to the Status Register. Before it can be
accepted, a Write Enable (WREN) instruction must
previously have been executed. After the Write Enable
(WREN) instruction has been decoded and executed, the
device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by

S

driving Chip Select (
and the data byte on Serial Data Input (D).
The instruction sequence is shown in Figure 7. The Write
Status Register (WRSR) instruction has no effect on b6, b5,
b1 and b0 of the Status Register. b6 and b5 are always read
as 0.

Chip Select (
the data byte has been latched in. If not, the Write Status
Register (WRSR) instruction is not executed. As soon as

Chip Select (
Register cycle (whose duration is t

S

S

) Low, followed by the instruction code

) must be driven High after the eighth bit of

) is driven High, the self-timed Write Status

) is initiated. While the

W

Write Status Register cycle is in progress, the Status
Register may still be read to check the value of the Write In
Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Write Status Register cycle, and is 0
when it is completed. When the cycle is completed, the Write
Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the
user to change the values of the Block Protect (BP2, BP1,
BP0) bits, to define the size of the area that is to be treated
as read-only, as defined in Table 1. The Write Status
Register (WRSR) instruction also allows the user to set or
reset the Status Register Write Disable (SRWD) bit in

accordance with the Write Protect (
Register Write Disable (SRWD) bit and Write Protect (

signal allow the device to be put in the Hardware Protected
Mode (HPM). The Write Status Register (WRSR) instruction
is not executed once the Hardware Protected Mode (HPM) is
entered.

Figure 7. Write Status Register (WRSR) Instruction Sequence

S

) signal. The Status

W

W

)

6

8109012345

7

C

Instruction

D

Q

High Impedance

MSB

11 121314 15

Status

Register In

5

6701

234

(April, 2007, Version 1.5) 11 AMIC Technology Corp.

A25L80P Series

Table 5. Protection Modes

W

Signal

1 0

0 0

1 1

0 1

Note: 1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 1.

Bit

Mode

Software

Protected

(SPM)

Hardware
Protected

(HPM)

SRWD

Write Protection of the

Status Register

Status Register is Writable (if
the WREN instruction has set
the WEL bit) The values in the
SRWD, BP2, BP1 and BP0 bits
can be changed

Status Register is Hardware
write protected The values in the
SRWD, BP2, BP1 and BP0 bits
cannot be changed

Protected Area

Protected against Page
Program, Sector Erase and
Bulk Erase

Protected against Page
Program, Sector Erase and
Bulk Erase

Memory Content

1

Unprotected Area

Ready to accept Page
Program and Sector Erase
instructions

Ready to accept Page
Program and Sector Erase
instructions

The protection features of the device are summarized in Table 5.
When the Status Register Write Disable (SRWD) bit of the
Status Register is 0 (its initial delivery state), it is possible to
write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable
(WREN) instr

(

) is driven High or Low.

W

When the Status Register Write Disable (SRWD) bit of the
Status Register is set to 1, two cases need to be considered,

depending on the state of Write Protect (

 If Write Protect (

to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write
Enable (WREN) instruction.

 If Write Protect (W) is driven Low, it is not possible to write

to the Status Register
(WEL) bit has previously been set by a Write Enable
(WREN) instruction. (Attempts to write to the Status
Register are rejected, and are not accepted for execution).

uction, regardless of the whether Write Protect

):

W

) is driven High, it is possible to write

W

even if the Write Enable Latch

As a consequence, all the data bytes in the memory area
that are software protected (SPM) by the Block Protect
(BP2, BP1, BP0) bits of the Status Register, are also

hardware protected against data modification.
Regardless of the order of the two events, the Hardware
Protected Mode (HPM) can be entered:

 by setting the Status Register Write Disable (SRWD) bit

after driving Write Protect (

 or by driving Write Protect (

Status Register Write Disable (SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM)

once entered is to pull Write Protect (

If Write Protect (
Protected Mode (HPM) can never be activated, and only the
Software Protected Mode (SPM), using the Block Protect
(BP2, BP1, BP0) bits of the Status Register, can be used.

) is permanently tied High, the Hardware

W

) Low

W

) Low after setting the

W

) High.

W

1

(April, 2007, Version 1.5) 12 AMIC Technology Corp.

A25L80P Series

Read Data Bytes (READ)

The device is first selected by driving Chip Select (S) Low.
The instruction code for the Read Data Bytes (READ)
instruction is followed by a 3-byte address (A23-A0), each bit
being latched-in during the rising edge of Serial Clock (C).
Then the memory contents, at that address, is shifted out on
Serial Data Output (Q), each bit being shifted out, at a
maximum frequency f
(C).
The instruction sequence is shown in Figure 8. The first byte
addressed can be at any location. The address is
automatically incremented to the next higher address after
each byte of data is shifted out. The whole memory can,

, during the falling edge of Serial Clock

R

therefore, be read with a single Read Data Bytes (READ)
instruction. When the highest address is reached, the
address counter rolls over to 000000h, allowing the read
sequence to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by

S

driving Chip Select (
High at any time during data output. Any Read Data Bytes
(READ) instruction, while an Erase, Program or Write cycle is
in progress, is rejected without having any effects on the
cycle that is in progress.

) High. Chip Select (S) can be driven

Figure 8. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence

S

810901234567

C

Instruction

D

Q

High Impedance

24-Bit Address

232221

MSB

28 29 30 313233 34 35 36 37 38 39

210

3

Data Out 1

7

MSB

54

32

10

Data Out 2

76

(April, 2007, Version 1.5) 13 AMIC Technology Corp.

A25L80P Series

Read Data Bytes at Higher Speed (FAST_READ)

The device is first selected by driving Chip Select (S) Low.
The instruction code for the Read Data Bytes at Higher
Speed (FAST_READ) instruction is followed by a 3-byte
address (A23-A0) and a dummy byte, each bit being
latched-in during the rising edge of Serial Clock (C). Then the
memory contents, at that address, is shifted out on Serial
Data Output (Q), each bit being shifted out, at a maximum
frequency f
The instruction sequence is shown in Figure 9. The first byte
addressed can be at any location. The address is
automatically incremented to the next higher address after
each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes at Higher

, during the falling edge of Serial Clock (C).

C

Speed (FAST_READ) instruction. When the highest address
is reached, the address counter rolls over to 000000h,
allowing the read sequence to be continued indefinitely.
The Read Data Bytes at Higher Speed (FAST_READ)

S

instruction is terminated by driving Chip Select (

S

Chip Select (
output. Any Read Data Bytes at Higher Speed (FAST_READ)
instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle
that is in progress.

) can be driven High at any time during data

) High.

Figure 9. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence an d Data-Out Sequence

S

810901234567

C

Instruction

24-Bit Address

28 29 30 31

D

Q

S

C

D

Q

Note: Address bits A23 to A20 are Don’t Care.

High Impedance

33 34 35 36 37 38 39

32

Dummy Byte

654

7 3

20

232221

MSB

40

41 42 43 44 45 46 47

1

Data Out 1

54

6

7

MSB

3

32

210

0

1

0

MSB

7

Data Out 2

54

6

32

0

1

7

MSB

(April, 2007, Version 1.5) 14 AMIC Technology Corp.

A25L80P Series

Page Program (PP)

The Page Program (PP) instruction allows bytes to be
programmed in the memory (changing bits from 1 to 0).
Before it can be accepted, a Write Enable (WREN)
instruction must previously have been executed. After the
Write Enable (WREN) instruction has been decoded, the
device sets the Write Enable Latch (WEL).

The Page Program (PP) instruction is entered by driving Chip

S

Select (
address bytes and at least one data byte on Serial Data Input
(D). If the 8 least significant address bits (A7-A0) are not all
zero, all transmitted data that goes beyond the end of the
current page are programmed from the start address of the
same page (from the address whose 8 least significant bits

(A7-A0) are all zero). Chip Select (
the entire duration of the sequence.
The instruction sequence is shown in Figure 10. If more than
256 bytes are sent to the device, previously latched data are
discarded and the last 256 data bytes are guaranteed to be

) Low, followed by the instruction code, three

S

) must be driven Low for

Figure 10. Page Program (PP) Instruction Sequence

S

programmed correctly within the same page. If less than 256
Data bytes are sent to device, they are correctly programmed
at the requested addresses without having any effects on the
other bytes of the same page.

Chip Select (
the last data byte has been latched in, otherwise the Page
Program (PP) instruction is not executed.

As soon as Chip Select (
Page Program cycle (whose duration is t
the Page Program cycle is in progress, the Status Register
may be read to check the value of the Write In Progress
(WIP) bit. The Write In Progress (WIP) bit is 1 during the
self-timed Page Program cycle, and is 0 when it is completed.
At some unspecified time before the cycle is completed, the
Write Enable Latch (WEL) bit is reset.

A Page Program (PP) instruction applied to a page which is
protected by the Block Protect (BP2, BP1, BP0) bits (see
Table 2 and Table 1) is not executed.

S

) must be driven High after the eighth bit of

S

) is driven High, the self-timed

) is initiated. While

PP

6

8109012345

7

C

Instruction

D

S

46454443424140

47

C

Data Byte 2

D

MSB

Note: Address bits A23 to A20 are Don’t Care.

54

6

7

32

1

0

7

MSB

24-Bit Address

232221

MSB

Data Byte 3

54

6

28 29 30 313233 34 35 36 37 38 39

Data Byte 1

210

51504948

3

32

MSB

5553 5452

0

1

7

MSB

54

6

7

2072

2073

Data Byte 256

54

6

2074

2075

1

32

2076

2077

2078

3210

03

2079

(April, 2007, Version 1.5) 15 AMIC Technology Corp.

A25L80P Series

Sector Erase (SE)

The Sector Erase (SE) instruction sets all bits to 1 (FFh).
Before it can be accepted, a Write Enable (WREN)
instruction must previously have been executed. After the
Write Enable (WREN) instruction has been decoded, the
device sets the Write Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip

S

Select (

Data Input (D). Chip Select (
entire duration of the sequence.
The instruction sequence is shown in Figure 11. Chip Select

S

(
code has been latched in, otherwise the Sector Erase

) Low, followed by the instruction code on Serial

S

) must be driven Low for the

) must be driven High after the eighth bit of the instruction

Figure 11. Sector Erase (SE) Instruction Sequence

S

6

C

Instruction

instruction is not executed. As soon as Chip Select (
driven High, the self-timed Sector Erase cycle (whose
duration is t
progress, the Status Register may be read to check the value
of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Sector Erase cycle, and is
0 when it is completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL) bit is reset.
The Sector Erase (SE) instruction is executed only if all
Block Protect (BP2, BP1, BP0) bits are 0. The Sector
Erase (SE) instruction is ignored if one, or more, sectors
are protected.

) is initiated. While the Sector Erase cycle is in

BE

8109012345

7

24-Bit Address

28 29 30 31

S

) is

23

22

D

23

MSB

21

3

210

0

Notes: Address bits A23 to A20 are Don’t Care.

(April, 2007, Version 1.5) 16 AMIC Technology Corp.

A25L80P Series

Bulk Erase (BE)

The Bulk Erase (BE) instruction sets all bits to 1 (FFh).
Before it can be accepted, a Write Enable (WREN)
instruction must previously have been executed. After the
Write Enable (WREN) instruction has been decoded, the
device sets the Write Enable Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip

S

Select (

Data Input (D). Chip Select (
entire duration of the sequence.
The instruction sequence is shown in Figure 12. Chip Select

S

(
code has been latched in, otherwise the Bulk Erase

) Low, followed by the instruction code on Serial

S

) must be driven Low for the

) must be driven High after the eighth bit of the instruction

Figure 12. Bulk Erase (BE) Instruction Sequence

S

1

0

2

C

instruction is not executed. As soon as Chip Select (
driven High, the self-timed Bulk Erase cycle (whose duration

) is initiated. While the Bulk Erase cycle is in progress,

is t

BE

the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit
is 1 during the self-timed Bulk Erase cycle, and is 0 when it is
completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
The Bulk Erase (BE) instruction is executed only if all
Block Protect (BP2, BP1, BP0) bits are 0. The Bulk Erase
(BE) instruction is ignored if one, or more, sectors are
protected.

3

456 7

S

) is

Instruction

D

Notes: Address bits A23 to A20 are Don’t Care.

(April, 2007, Version 1.5) 17 AMIC Technology Corp.

A25L80P Series

Deep Power-down (DP)

Executing the Deep Power-down (DP) instruction is the only
way to put the device in the lowest consumption mode (the
Deep Power-down mode). It can also be used as an extra
software protection mechanism, while the device is not in
active use, since in this mode, the device ignores all Write,
Program and Erase instructions.

S

Driving Chip Select (
the device in the Standby mode (if there is no internal cycle
currently in progress). But this mode is not the Deep
Power-down mode. The Deep Power-down mode can only
be entered by executing the Deep Power-down (DP)
instruction, to reduce the standby current (from I
as specified in DC Characteristics Table.).

Once the device has entered the Deep Power-down mode,
all instructions are ignored except the Release from Deep
Power-down and Read Electronic Signature (RES)
instruction. This releases the device from this mode. The
Release from Deep Power-down and Read Electronic
Signature (RES) instruction also allows the Electronic Signa­ture of the device to be output on Serial Data Output (Q).

) High deselects the device, and puts

to I

CC1

CC2

,

Figure 13. Deep Power-down (DP) Instruction Sequence

The Deep Power-down mode automatically stops at
Power-down, and the device always Powers-up in the
Standby mode.
The Deep Power-down (DP) instruction is entered by driving

S

Chip Select (

Serial Data Input (D). Chip Select (
the entire duration of the sequence. The instruction
sequence is shown in Figure 13.

Chip Select (
the instruction code has been latched in, otherwise the Deep
Power-down (DP) instruction is not executed. As soon as

Chip Select (
before the supply current is reduced to I
Power-down mode is entered.
Any Deep Power-down (DP) instruction, while an Erase,
Program or Write cycle is in progress, is rejected without
having any effects on the cycle that is in progress.

) Low, followed by the instruction code on

S

) must be driven Low for

S

) must be driven High after the eighth bit of

S

) is driven High, it requires a delay of tDP

and the Deep

CC2

S

t

1

0

C

D

3

2

4567

Instruction

DP

Stand-by Mode Deep Power-down Mode

(April, 2007, Version 1.5) 18 AMIC Technology Corp.

A25L80P Series

Read Device Identification (RDID)

The Read Identification (RDID) instruction allows the 8-bit
manufacturer identification code to be read, followed by two
bytes of device identification. The manufacturer identification
is assigned by JEDEC, and has the value 37h, plus the
continuation identification for AMIC Technology. The device
identification is assigned by the device manufacturer, and
indicates the memory in the first bytes (20h), and the
memory capacity of the device in the second byte (14h).

Any Read Identification (RDID) instruction while an Erase, or
Program cycle is in progress, is not decoded, and has no
effect on the cycle that is in progress.

S

The device is first selected by driving Chip Select (

) Low.

Then, the 8-bit instruction code for the instruction is shifted in.

Table. Read Identification (READ_ID) Data-Out Sequence

Manufacture Identification Device Identification

Continuation ID Manufacture ID Memory Type Memory Capacity

7Fh 37h 20h 14h

Figure 14. Read Identification (RDID) Data-Out Sequence

This is followed by the 32-bit device identification, stored in
the memory, being shifted out on Serial Data Output (Q),
each bit being shifted out during the falling edge of Serial
Clock (C).

The instruction sequence is shown in Figure 14. The Read
Identification (RDID) instruction is terminated by driving Chip

S

Select (

When Chip Select (

) High at any time during data output.

S

) is driven High, the device is put in the
Stand-by Power mode. Once in the Stand-by Power mode,
the device waits to be selected, so that it can receive,
decode and execute instructions.

S

810901 2 3 4 5 6 7 21 3022 23 24 25 26 29 31

C

Instruction

D

Q

High Impedance

313029

Continuation ID

13 1514 16 17 18 3332 34 3837 39

262524

232221

Manufacture ID Memory Type

181716

15 14 13 10 9 8

65 2107

Memory Capacity

(April, 2007, Version 1.5) 19 AMIC Technology Corp.

A25L80P Series

Release from Deep Power-down and Read
Electronic Signature (RES)

Once the device has entered the Deep Power-down mode,
all instructions are ignored except the Release from Deep
Power-down and Read Electronic Signature (RES)
instruction. Executing this instruction takes the device out of
the Deep Power-down mode.

The instruction can also be used to read, on Serial Data
Output (Q), the 8-bit Electronic Signature, whose value for

A25L80P is 13h.

the

Except while an Erase, Program or Write Status Register
cycle is in progress, the Release from Deep Power-down and
Read Electronic Signature (RES) instruction always provides
access to the 8-bit Electronic Signature of the device, and
can be applied even if the Deep Power-down mode has not
been entered.

Any Release from Deep Power-down and Read Electronic
Signature (RES) instruction while an Erase, Program or Write
Status Register cycle is in progress, is not decoded, and has
no effect on the cycle that is in progress.

S

The device is first selected by driving Chip Select (
The instruction code is followed by 3 dummy bytes, each bit
being latched-in on Serial Data Input (D) during the rising

) Low.

edge of Serial Clock (C). Then, the 8-bit Electronic Signature,
stored in the memory, is shifted out on Serial Data Output
(Q), each bit being shifted out during the falling edge of
Serial Clock (C).
The instruction sequence is shown in Figure 15.
The Release from Deep Power-down and Read Electronic
Signature (RES) instruction is terminated by driving Chip

Select (
at least once. Sending additional clock cycles on Serial Clock

(C), while Chip Select (
Electronic Signature to be output repeatedly.

When Chip Select (
Stand-by Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the Stand-by
Power mode is immediate. If the device was previously in the
Deep Power-down mode, though, the transition to the Stand-

by Power mode is delayed by t
must remain High for at least t
Characteristics Table . Once in the Stand-by Power mode,
the device waits to be selected, so that it can receive,
decode and execute instructions.

S

) High after the Electronic Signature has been read

S

) is driven Low, cause the

S

) is driven High, the device is put in the

, and Chip Select (S)

RES2

(max), as specified in AC

RES2

Figure 15. Release from Deep Power-down and Read Electronic Signature (RES) Instruction Sequence and
Data-Out Sequence

S

810901234567

C

Instruction

D

Q

Note: The value of the 8-bit Electronic Signature, for the A25L80P, is 13h.

High Impedance

3 Dummy Bytes

232221

MSB

28 29 30 313233 34 35 36 37 38

210

3

6

7

MSB

54

32

10

t

RES2

Stand-by ModeDeep Power-down Mode

(April, 2007, Version 1.5) 20 AMIC Technology Corp.

A25L80P Series

Figure 16. Release from Deep Power-down (RES) Instruction Sequence

S

t

1

C

D

Q

0

High Impedance

3

2

456 7

Instruction

RES1

Driving Chip Select (S) High after the 8-bit instruction byte
has been received by the device, but before the whole of the
8-bit Electronic Signature has been transmitted for the first
time (as shown in Figure 16.), still insures that the device is
put into Stand-by Power mode. If the device was not pre­viously in the Deep Power-down mode, the transition to the
Stand-by Power mode is immediate. If the device was

previously in the Deep Power-down mode, though, the
transition to the Stand-by Power mode is delayed by t

and Chip Select (
as specified in AC Characteristics Table. Once in the
Stand-by Power mode, the device waits to be selected, so
that it can receive, decode and execute instructions.

Stand-by ModeDeep Power-down Mode

S

) must remain High for at least t

RES1

,

RES1

(max),

(April, 2007, Version 1.5) 21 AMIC Technology Corp.

A25L80P Series

POWER-UP AND POWER-DOWN

At Power-up and Power-down, the device must not be

S

selected (that is Chip Select (
applied on V

 V

CC

 V

SS

) until VCC reaches the correct value:

CC

(min) at Power-up, and then for a further delay of t

at Power-down

Usually a simple pull-up resistor on Chip Select (

) must follow the voltage

VSL

S

) can be
used to insure safe and proper Power-up and Power-down.
To avoid data corruption and inadvertent write operations
during power up, a Power On Reset (POR) circuit is included.
The logic inside the device is held reset while V
than the POR threshold value, V

– all operations are

WI

is less

CC

disabled, and the device does not respond to any instruction.
Moreover, the device ignores all Write Enable (WREN), Page
Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write
Status Register (WRSR) instructions until a time delay of

has elapsed after the moment that VCC rises above the

t

PUW

VWI threshold. However, the correct operation of the device
is not guaranteed if, by this time, V

is still below VCC(min).

CC

No Write Status Register, Program or Erase instructions
should be sent until the later of:

Figure 17. Power-up Timing

V

CC

 t

after VCC passed the VWI threshold

PUW

afterVCC passed the VCC(min) level

- t

VSL

These values are specified in Table 6.
If the delay, t

(min), the device can be selected for READ instructions

V

CC

even if the t

L, has elapsed, after V

VS

delay is not yet fully elapsed.

PUW

has risen above

CC

At Power-up, the device is in the following state:

 The device is in the Standby mode (not the Deep

Power-down mode).

 The Write Enable Latch (WEL) bit is reset.

Normal precautions must be taken for supply rail decoupling,
to stabilize the V
have the V

CC

feed. Each device in a system should

CC

rail decoupled by a suitable capacitor close to

the package pins. (Generally, this capacitor is of the order of

0.1µF).
At Power-down, when V
to below the POR threshold value, V

drops from the operating voltage,

CC

, all operations are

WI

disabled and the device does not respond to any instruction.
(The designer needs to be aware that if a Power-down
occurs while a Write, Program or Erase cycle is in progress,
some data corruption can result.)

VCC(max)

VCC(min)

t

PU

Full Device Access

time

(April, 2007, Version 1.5) 22 AMIC Technology Corp.

A25L80P Series

Table 6. Power-Up Timing

Symbol Parameter Min. Max. Unit

VCC(min) VCC (minimum) 2.7 V

tPU VCC (min) to device operation 10 ms

Note: These parameters are characterized only.

INITIAL DELIVERY STATE

The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register
contains 00h (all Status Register bits are 0).

(April, 2007, Version 1.5) 23 AMIC Technology Corp.

A25L80P Series

Absolute Maximum Ratings*

Storage Temperature (TSTG) . . . . . . . . . . . . -65°C to + 150°C

Lead Temperature during Soldering (Note 1)

D.C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.6V to VCC+0.6V

Transient Voltage (<20ns) on Any Pin to Ground Potential . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VCC+2.0V

Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . -0.6V to +4.0V

Electrostatic Discharge Voltage (Human Body model) (VESD)

(Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . -2000V to 2000V

Notes:

1. Compliant with JEDEC Std J-STD-020B (for small body,

Sn-Pb or Pb assembly).

2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500

R2=500

Ω)

*Comments

Stressing the device above the rating listed in the Absolute
Maximum Ratings" table may cause permanent damage to the
device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated
in the Operating sections of this specification is not implied.
Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to
the AMIC SURE Program and other relevant quality docu­ments.

Ω ,

DC AND AC PARAMETERS

This section summarizes the operating and measurement
conditions, and the DC and AC characteristics of the device.
The parameters in the DC and AC Characteristic tables that
follow are derived from tests performed under the

Measurement Conditions summarized in the relevant tables.
Designers should check that the operating conditions in their
circuit match the measurement conditions when relying on
the quoted parameters.

Table 7. Operating Conditions

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 2.7 3.6 V

TA Ambient Operating Temperature –40 85 °C

(April, 2007, Version 1.5) 24 AMIC Technology Corp.

A25L80P Series

Table 8. Data Retention and Endurance

Parameter Condition Min. Max. Unit

Erase/Program Cycles At 85°C 100,000 Cycles per sector

Data Retention At 85°C 20 Years

Note: 1. This is preliminary data

Table 9. Capacitance

Symbol Parameter Test Condition Min. Max. Unit

C

Output Capacitance (Q) V

OUT

CIN Input Capacitance (other pins) V

Note: Sampled only, not 100% tested, at TA=25°C and a frequency of 33 MHz.

OUT

= 0V

IN

= 0V

8 pF

6 pF

(April, 2007, Version 1.5) 25 AMIC Technology Corp.

A25L80P Series

Table 10. DC Characteristics

Symbol Parameter Test Condition Min. Max. Unit

ILI Input Leakage Current ± 2 µA

ILO Output Leakage Current ± 2 µA

I

Standby Current

CC1

I

Deep Power-down Current

CC2

I

Operating Current (READ)

CC3

I

Operating Current (PP)

CC4

I

Operating Current (WRSR)

CC5

I

Operating Current (SE)

CC6

I

Operating Current (BE)

CC7

VIL Input Low Voltage –0.5 0.3VCC V

VIH Input High Voltage 0.7VCC VCC+0.4 V

VOL Output Low Voltage IOL = 1.6mA 0.4 V

C= 0.1VCC / 0.9.VCC at 50MHz, Q = open 8 mA

C= 0.1V

S

= VCC, VIN = VSS or VCC

S

= VCC, VIN = VSS or VCC

/ 0.9.VCC at 33MHz, Q = open 4 mA

CC

S

= VCC

S

= VCC

S

= VCC

S

= VCC

50 µA

10 µA

15 mA

15 mA

15 mA

15 mA

VOH Output High Voltage IOH = –100µA VCC–0.2 V

Note: 1. This is preliminary data at 85°C

Table 11. Instruction Times

Symbol Alt. Parameter Min. Typ. Max. Unit

tW Write Status Register Cycle Time 5 15 ms

tPP Page Program Cycle Time 3 5 ms

tSE Sector Erase Cycle Time 1 3 s

tBE Bulk Erase Cycle Time 4.5 10 s

Note: 1. At 85°C

2. This is preliminary data

Table 12. AC Measurement Conditions

Symbol Parameter Min. Max. Unit

CL Load Capacitance 30 pF

Input Rise and Fall Times 5 ns

Input Pulse Voltages 0.2VCC to 0.8VCC V

Input Timing Reference Voltages 0.3VCC to 0.7VCC V

Output Timing Reference Voltages VCC / 2 V

Note: Output Hi-Z is defined as the point where data out is no longer driven.

(April, 2007, Version 1.5) 26 AMIC Technology Corp.

A25L80P Series

Figure 18. AC Measurement I/O Waveform

Input Levels Input and Output

0.8V

CC

0.2V

CC

Timing Reference Levels

0.7V

CC

0.5V

CC

0.3V

CC

(April, 2007, Version 1.5) 27 AMIC Technology Corp.

A25L80P Series

Table 13. AC Characteristics

Symbol

fC f

Alt. Parameter Min.

Clock Frequency for the following instructions: FAST_READ,

C

PP, SE, BE, DP, RES, RDID, WREN, WRDI, RDSR, WRSR
(2.7V~3.6V) / (3V~3.6V)

fR Clock Frequency for READ instructions D.C. 33 MHz

tCH 1

tCL 1

t

2

CLCH

t

2

CHCL

t

t

SLCH

t

CHSL

t

DVCH

t

tDH Data In Hold Time 5 ns

CHDX

t

CHSH

t

SHCH

t

t

SHSL

t

2

SHQZ

t

t

CLQV

t

tHO Output Hold Time 0 ns

CLQX

t

HLCH

t

CHHH

t

HHCH

t

HOLD Hold Time (relative to C) 5 ns

CHHL

t

2

HHQX

t

2

HLQZ

4

t

WHSL

t

4

SHWL

tDP 2

t

2

RES1

t

2

RES2

t

Clock High Time 7 ns

CLH

t

Clock Low Time 6 ns

CLL

Clock Rise Time3 (peak to peak)

Clock Fall Time3 (peak to peak)

CSS

t

DSU

CSH

t

DIS

V

S

Active Setup Time (relative to C)

S

Not Active Hold Time (relative to C)

Data In Setup Time 5 ns

S

Active Hold Time (relative to C)

S

Not Active Setup Time (relative to C)

S

Deselect Time

Output Disable Time 8 ns

Clock Low to Output Valid 8 ns

Setup Time (relative to C)

HOLD

Hold Time (relative to C)

HOLD

HOLD Setup Time (relative to C) 5 ns

t

HOLD to Output Low-Z 7 ns

LZ

t

HZ

Write Protect Setup Time 20 ns

to Output High-Z

HOLD

Write Protect Hold Time 100 ns

S

High to Deep Power-down Mode

S

High to Standby Mode without Electronic Signature Read

S

High to Standby Mode with Electronic Signature Read

tW Write Status Register Cycle Time 5 15 ms

tpp Page Program Cycle Time 3 5 ms

tSE Sector Erase Cycle Time 1 3 s

tBE Bulk Erase Cycle Time 10 40 s

Note: 1. tCH + tCL must be greater than or equal to 1/ fC

2. Value guaranteed by characterization, not 100% tested in production.

3. Expressed as a slew-rate.

4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.

5

Typ. Max.

D.C. 50/75 MHz

0.1 V/ns

0.1 V/ns

5 ns

5 ns

5 ns

5 ns

100 ns

5 ns

5 ns

8 ns

3 µs

30 µs

30 µs

5

Unit

(April, 2007, Version 1.5) 28 AMIC Technology Corp.

A25L80P Series

Figure 19. Serial Input Timing

S

tSLCHtCHSL

C

tDVCH

tCHDX

D

Q

High Impedance

tCHSH

tCLCH

LSB INMSB IN

Figure 20. Write Protect Setup and Hold Timing during WRSR when SRWD=1

W

tWHSL

tSHSL

tSHCH

tCHCL

tSHWL

S

C

D

Q

High Impedance

(April, 2007, Version 1.5) 29 AMIC Technology Corp.

A25L80P Series

Figure 21. Hold Timing

S

C

D

Q

HOLD

Figure 22. Output Timing

tCHHL

tHLQZ

tHLCH

tHHCH

tCHHH

tHHQX

S

tCH

C

ADDR.LSB IN

D

tCLQV

tCLQX

Q

tCLQX

tCLQV

tCL

LSB OUT

tQLQH
tQHQL

tSHQZ

(April, 2007, Version 1.5) 30 AMIC Technology Corp.

A25L80P Series

Part Numbering Scheme

A25

XXX XXX

X

X

Package Material
Blank: normal
F: PB free

Temperature*

Package
M = 209 mil SOP 8
O = 150 mil SOP 8
Q = QFN 8

Device Version*

Device Function
P = Page Program &

Sector Erase

Device Density
05 = 512 Kbit

40 = 4 Mbit
80 = 8 Mbit
16 = 16 Mbit

Device Voltage
L = 2.7-3.6V

Device Type
A25 = AMIC Serial Flash

* Optional

(April, 2007, Version 1.5) 31 AMIC Technology Corp.

A25L80P Series

Ordering Information

Part No.

A25L80P 8 Pin DIP (300mil)

A25L80P-F 8 Pin Pb-Free DIP (300mil)

A25L80P-U 8 Pin DIP (300mil)

A25L80P-UF

A25L80PM 8 Pin SOP (209mil)

A25L80PM-F 8 Pin Pb-Free SOP (209mil)

A25L80PM-U 8 Pin SOP (209mil)

A25L80PM-UF

A25L80PO 8 Pin SOP (150mil)

A25L80PO-F 8 Pin Pb-Free SOP (150mil)

A25L80PO-U 8 Pin SOP (150mil)

Speed (MHz)
(2.7V~3.6V) /

(3.0V~3.6V)

50/75 8 15 50

50/75 8 15 50

50/75 8 15 50

Active Read

Current

Typ. (mA)

Program/Erase

Current

Typ. (mA)

Standby

Current

Typ. (μA)

Package

8 Pin Pb-Free DIP (300mil)

8 Pin Pb-Free SOP (209mil)

A25L80PO-UF

A25L80PQ 8 Pin QFN

A25L80PQ-F 8 Pin Pb-Free QFN

50/75 8 15 50

A25L80PQ-U 8 Pin QFN

A25L80PQ-UF

8 Pin Pb-Free SOP (150mil)

8 Pin Pb-Free QFN

-U is for industrial operating temperature range: -40°C ~ +85°C

(April, 2007, Version 1.5) 32 AMIC Technology Corp.

A25L80P Series

Package Information
P-DIP 8L Outline Dimensions

unit: inches/mm

Dimensions in inches Dimensions in mm

Symbol

A - - 0.180 - - 4.57

A1 0.015 - - 0.38 - ­A2 0.128 0.130 0.136 3.25 3.30 3.45

B 0.014 0.018 0.022 0.36 0.46 0.56

B1 0.050 0.060 0.070 1.27 1.52 1.78
B2 0.032 0.039 0.046 0.81 0.99 1.17

C 0.008 0.010 0.013 0.20 0.25 0.33

D 0.350 0.360 0.370 8.89 9.14 9.40

E 0.290 0.300 0.315 7.37 7.62 8.00

E1 0.254 0.260 0.266 6.45 6.60 6.76

e1 - 0.100 - - 2.54 -

L 0.125 - - 3.18 - -

EA 0.345 - 0.385 8.76 - 9.78

S 0.016 0.021 0.026 0.41 0.53 0.66

Min Nom Max Min Nom Max

Notes:

1. Dimension D and E1 do not include mold flash or protrusions.

2. Dimension B

3. Tolerance:

(April, 2007, Version 1.5) 33 AMIC Technology Corp.

1 does not include dambar protrusion.

±0.010” (0.25mm) unless otherwise specified.

A25L80P Series

Package Information
SOP 8L (150mil) Outline Dimensions

e

b

D

unit: mm

E

HE

A

A1

L

°° 8~0

Symbol

A 1.35~1.75

A1

b 0.33~0.51

D 4.7~5.0

E 3.80~4.00

e 1.27 BSC

HE 5.80~6.20

L 0.40~1.27

Dimensions in mm

0.10~0.25

Notes:

1. Maximum allowable mold flash is 0.15mm.

2. Complies with JEDEC publication 95 MS –012 AA.

3. All linear dimensions are in millimeters (max/min).

4. Coplanarity: Max. 0.1mm

(April, 2007, Version 1.5) 34 AMIC Technology Corp.

A25L80P Series

Package Information
SOP 8L (209mil) Outline Dimensions

85

1

D

e

b

unit: mm

E

4

A

A2

GAGE PLANE

A1

SEATING PLANE

0.25

E1

C

θ

L

Symbol

A

A1 0.05
A2 1.70 1.80 1.91

b 0.35 0.42 0.48

C 0.19 0.20 0.25

D

E 7.70 7.90 8.10

E1 5.18 5.28 5.38

e 1.27 BSC

L 0.50 0.65 0.80

θ

Dimensions in mm

Min Nom Max

1.75 1.95

0.15 0.25

5.13

0°

5.23 5.33

-

2.16

8°

Notes:

Maximum allowable mold flash is 0.15mm at the package
ends and 0.25mm between leads

(April, 2007, Version 1.5) 35 AMIC Technology Corp.

A25L80P Series

Package Information

QFN 8L (6 X 5 X 0.8mm) Outline Dimensions unit: mm/mil

0.25 C

14

D

Pin1 ID Area

58

E

0.25 C

D2

e

1432

C0.30

8

b

L

567

E2

A1

Seating Plane

Symbol

A 0.700 0.750 0.800 27.6 29.5 31.5

A1 0.000 0.020 0.050 0.0 0.8 2.0
A3 0.203 REF 8.0 REF

b 0.350 0.400 0.480 13.8 15.8 18.9

D 5.900 6.000 6.100 232.3 236.2 240.2

D2 3.200 3.400 3.600 126.0 133.9 141.7

E 4.900 5.000 5.100 192.9 196.9 200.8

E2 3.800 4.000 4.200 149.6 157.5 165.4

L 0.500 0.600 0.750 19.7 23.6 29.5

e

y 0 - 0.080 0 - 3.2

Note:

1. Controlling dimension: millimeters

2. Leadframe thickness is 0.203mm (8mil)

0.10// C

A

y C

A3

Dimensions in mm Dimensions in mil

Min Nom Max Min Nom Max

1.270 BSC 50.0 BSC

(April, 2007, Version 1.5) 36 AMIC Technology Corp.