Datasheet A1185, A1186 Datasheet (ALLEGRO)

A1185 and A1186

Ultrasensitive T wo-Wire Field-Programmable

Chopper-Stabilized Unipolar Hall-Effect Switches

Features and Benefits

▪ Chopper stabilization

▫ Low switchpoint drift over operating

temperature range

▫ Low sensitivity to stress
▪ Field programmable for optimized switchpoints
▪ On-chip protection

▫ Supply transient protection

▫ Reverse-battery protection

▫ On-board voltage regulator

▫ 3.5 to 24 V operation

Packages: 3 pin SOT23W (suffix LH), and
3 pin SIP (suffix UA)

Description

The A1185 and A1186 are ultrasensitive, two-wire, unipolar
Hall effect switches. The operate point, BOP, can be field­programmed, after final packaging of the sensor and
placement into the application. This advanced feature allows
the optimization of the sensor switching performance, by
effectively accounting for variations caused by mounting
tolerances for the device and the target magnet.

This family of devices are produced on the Allegro
MicroSystems new DABIC5 BiCMOS wafer fabrication
process, which implements a patented, high-frequency, chopper­stabilization technique that achieves magnetic stability and
eliminates the offsets that are inherent in single-element devices
exposed to harsh application environments. Commonly found
in a number of automotive applications, the A1185 and A1186
devices are utilized to sense: seat track position, seat belt buckle
presence, hood/trunk latching, and shift selector position.

Two-wire unipolar switches are particularly advantageous
in price-sensitive applications, because they require one less
wire than the more traditional open-collector output switches.

Not to scale

V+

VCC

0.01 uF

Continued on the next page…

Functional Block Diagram

Program/Lock

Dynamic Offset

Cancellation

Programming

Logic

Clock/Logic

Amp

Offset
Adjust

Low-Pass
Filter

Sample and Hold

Regulator

To all
subcircuits

GND

Package UA Only

GND

A1185-DS, Rev. 2

A1185 and

Ultrasensitive T wo-Wire Field-Programmable

A1186

Chopper-Stabilized Unipolar Hall Effect Switches

Description (continued)

Additionally, the system designer gains inherent diagnostics
because output current normally flows in either of two narrowly­specified ranges. This provides distinct current ranges for I
and I

. Any output current level outside of these two ranges

OUT(L)

OUT(H)

is a fault condition.

Other features of the A1185 and A1186 devices include on-chip
transient protection and a Zener clamp on the power supply to protect
against overvoltage conditions on the supply line.

present. The A1185 has an inverted output current level: switching

LOW in the presence of a south polarity magnetic field of sufficient

strength, and HIGH otherwise.

Both devices are offered in two package styles: LH, a SOT-23W
miniature low-profile package for surface-mount applications, and
UA, a three-lead ultramini Single Inline Package (SIP) for through­hole mounting. Each package is available in a lead (Pb) free version

(suffix, –T) with 100% matte tin plated leadframe.

The output current of the A1186 switches
a south polarity magnetic field of sufficient strength; and switches

LOW otherwise, including when there is no significant magnetic field

HIGH in the presence of

Factory-programmed versions are also available. Refer to: A1145
and A1146.

Selection Guide

Part Number Pb-free

A1185ELHLT-T Yes 7-in. reel, 3000 pieces/reel Surface mount

A1185EUA-T Yes Bulk, 500 pieces/bag 4-pin SIP through hole

A1185LLHLT-T Yes 7-in. reel, 3000 pieces/reel Surface mount

A1185LUA-T Yes Bulk, 500 pieces/bag 4-pin SIP through hole

A1186ELHLT-T Yes 7-in. reel, 3000 pieces/reel Surface mount

A1186EUA-T Yes Bulk, 500 pieces/bag 4-pin SIP through hole

A1186LLHLT-T Yes 7-in. reel, 3000 pieces/reel Surface mount

A1186LUA-T Yes Bulk, 500 pieces/bag 4-pin SIP through hole

1

Pb-based variants are being phased out of the product line. Certain variants cited in this footnote are in production but have been determined to be NOT FOR NEW
DESIGN. This classification indicates that sale of this device is currently restricted to existing customer applications. The device should not be purchased for new design
applications because obsolescence in the near future is probable. Samples are no longer available. Status change: May 1, 2006. These variants include: A1185ELHLT,
A1185EUA, A1185LLHLT, A1185LUA, A1186ELHLT, A1186EUA, A1186LLHLT, and A1186LUA.

2

Contact Allegro for additional packing options.

3

South (+) magnetic fields must be of sufficient strength.

1

Packing

2

Mounting

Ambient, T

–40 to 85

–40 to 150

–40 to 85

–40 to 150

(°C)

A

Output

South (+) Field

Low

High

Supply Current at Low

3

Output, I

5 to 6.9

(mA)

CC(L)

Absolute Maximum Ratings

Characteristic Symbol Notes Rating Units

Supply Voltage V

Reverse Supply Voltage V

Magnetic Flux Density B Unlimited G

Operating Ambient Temperature T

Maximum Junction Temperature T

Storage Temperature T

CC

RCC

A

(max) 165 ºC

J

stg

Range E –40 to 85 ºC

Range L –40 to 150 ºC

28 V

–18 V

–65 to 170 ºC

Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com

2

A1185 and

Ultrasensitive T wo-Wire Field-Programmable

A1186

Chopper-Stabilized Unipolar Hall Effect Switches

ELECTRICAL CHARACTERISTICS over the operating voltage and temperature ranges, unless otherwise specified

Characteristic Symbol Test Conditions Min. Typ. Max. Units

= I

1

2

4

5

6,7

CCL(max)

+ 3 mA.

V

CC

I

CC(L)

I

CC(H)

ZSupplyICC

3

I

ZSupply

RCC

Device powered on 3.5 – 24 V

B >BOP for A1185; B <BRP for A1186 5 – 6.9 mA

B >BOP for A1186; B <BRP for A1185 12 – 17 mA

= I

CC(L)(Max)

V

= 28 V – – 9.9 mA

Supply

V

= –18 V – – 1.6 mA

RCC

+ 3 mA; TA = 25°C 28 – 40 V

No bypass capacitor; capacitance of the

di/dt

oscilloscope performing the measurement

– 36 – mA/μs

= 20 pF

C

t

on

After factory trimming; with and without
bypass capacitor (C

POS ton ≤ t

on(max)

= 0.01 μF)

BYP

; V

slew rate > 25 mV/μs – HIGH – –

CC

– 200 – kHz

––25μs

Supply Voltage

Supply Current

Supply Zener Clamp Voltage V

Supply Zener Clamp Current

Reverse Supply Current I

Output Slew Rate

Chopping Frequency f

Power-On Time

Power-On State

1

VCC represents the generated voltage between the VCC pin and the GND pin.

2

Relative values of B use the algebraic convention, where positive values indicate south magnetic polarity, and negative values indicate north magnetic

polarity; therefore greater B values indicate a stronger south polarity field (or a weaker north polarity field, if present).

3

I

ZSUPPLY(max)

4

Measured without bypass capacitor between VCC and GND. Use of a bypass capacitor results in slower current change.

5Measured with and without bypass capacitor of 0.01 μF. Adding a larger bypass capacitor causes longer Power-On Time.

6

POS is defined as true only with a VCC slew rate of 25 mV / μs or greater. Operation with a VCC slew rate less than 25 mV / μs can permanently harm

device performance.

7

POS is undefined for t > ton or BRP < B < BOP .

MAGNETIC CHARACTERISTICS

1

over the operating voltage and temperature ranges, unless otherwise specified

Characteristic Symbol Test Conditions Min. Typ. Max. Units

Programmable Operate Point Range B

Initial Operate Point Range B

Switchpoint Step Size

2

OPrange

OPinitVCC

B

RES

ICC = I
ICC = I

VCC = 5 V, TA = 25°C 2 4 6 G

for A1185

CC(L)

CC(H)

for A1186

10 – 60 G

= 12 V – –10 10 G

Switchpoint setting – 5 – Bit

Number of Programming Bits

Temperature Drift of B

OP

Hysteresis B

1

Relative values of B use the algebraic convention, where positive values indicate south magnetic polarity, and negative values indicate north magnetic

polarity; therefore greater B values indicate a stronger south polarity field (or a weaker north polarity field, if present).

2

The range of values specified for B

is a maximum, derived from the cumulative programming bit errors.

RES

ΔB

–

Programming locking – 1 – Bit

OP

HYS

B

HYS

= BOP – B

RP

– – ±20 G

51530G

Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com

3

A1185 and

Ultrasensitive T wo-Wire Field-Programmable

A1186

10

8

6

(mA)

4

CC(L)

I

2

0

-50 0 50 100 150 200

70

60

50

40

30

(G)

20

OP

B

10

0

–10

–20

01234 65

Chopper-Stabilized Unipolar Hall Effect Switches

Characteristic Data

I

versus Ambient Temperature

CC(L)

at Various Levels of V

CC

(A1185 and A1186)

20

(mA)

CC(H)

I

18

16

14

12

10

VCC(V)

3.5

12.0

24.0

Ambient Temperature, TA(°C) Ambient Temperature, TA(°C)

BOPSet by Specific Programming Bit

V

=12V TA= 25°C

CC

(A1185 and A1186)

(G)

HYS

B

Bit Number

I

versus Ambient Temperature

CC(H)

at Various Levels of V

(A1185 and A1186)

-50 0 50 100 150 200

Hysteresis versus Ambient Temperature

at Various Levels of V

(A1185 and A1186)

40

35

30

25

20

15

10

5

-50 0 50 100 150 200

Ambient Temperature, TA(°C)

CC

VCC(V)

3.5

12.0

24.0

CC

VCC(V)

3.5

12.0

24.0

Device Qualification Program

Contact Allegro for information.

EMC (Electromagnetic Compatibility) Requirements

Contact your local representative for EMC results.

Test Name Reference Specification

ESD – Human Body Model AEC-Q100-002

ESD – Machine Model AEC-Q100-003

Conducted Transients ISO 7637-2

Direct RF Injection ISO 11452-7

Bulk Current Injection ISO 11452-4

TEM Cell ISO 11452-3

Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com

4

A1185 and

Ultrasensitive T wo-Wire Field-Programmable

A1186

Chopper-Stabilized Unipolar Hall Effect Switches

THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information

Characteristic Symbol Test Conditions* Value Units

Package LH, 1-layer PCB with copper limited to solder pads 228 ºC/W

Package Thermal Resistance

R

θJA

Package LH, 2-layer PCB with 0.463 in.
connected by thermal vias

Package UA, 1-layer PCB with copper limited to solder pads 165 ºC/W

*Additional thermal information available on Allegro Web site.

Power Derating Curve

25
24
23
22
21

(V)

20

CC

19
18
17
16

15
14
13
12
11
10

9

Maximum Allowable V

8
7
6
5
4
3
2

2-layer PCB, Package LH
(R

= 110 ºC/W)

θJA

1-layer PCB, Package UA
(R

= 165 ºC/W)

θJA

1-layer PCB, Package LH
(R

= 228 ºC/W)

θJA

20 40 60 80 100 120 140 160 180

Temperature (ºC)

2

of copper area each side

V

CC(max)

V

CC(min)

110 ºC/W

Power Dissipation versus Ambient Temperature

1900
1800
1700
1600
1500
1400
1300

(mW)

D

Power Dissipation, P

1200
1100
1000

900
800
700
600
500
400
300
200

2-layer PCB, Package LH

(R

θJA

= 110 ºC/W)

1-layer

(R

PCB, Pa

θ

JA

= 165 ºC/W)

1-lay

e

rP

(R

θ

J

=

A

22

ckage

UA

CB, Package LH

8ºC

/

W

)

100

0

20 40 60 80 100 120 140 160 180

Temperature (°C)

Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com

5

A1185 and

Ultrasensitive T wo-Wire Field-Programmable

A1186

Chopper-Stabilized Unipolar Hall Effect Switches

Functional Description

Operation

The output, I

field at the Hall sensor exceeds the operate point threshold, BOP.

When the magnetic field is reduced to below the release point

threshold, BRP, the device output goes high. The differences

between the magnetic operate and release point is called the

, of the A1185 switches low after the magnetic

CC

hysteresis of the device, B

. This built-in hysteresis allows

HYS

clean switching of the output even in the presence of external

mechanical vibration and electrical noise. The A1186 device

switches with opposite polarity for similar B

and BRP values,

OP

in comparison to the A1185 (see figure 1).

I

I+

CC

Switch to Low

Switch to High

0

B–

B

RP

B

HYS

B

OP

B+

I

CC(H)

I

CC(L)

(A) A1185

Figure 1. Alternative switching behaviors are available in the A118x device family. On the horizontal axis, the B+ direction indicates
increasing south polarity magnetic field strength, and the B– direction indicates decreasing south polarity field strength (including the
case of increasing north polarity).

I

I+

CC

I

B+

CC(H)

I

CC(L)

Switch to Low

Switch to High

0

B–

B

RP

B

HYS

B

OP

(B) A1186

Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com

6

A1185 and

Ultrasensitive T wo-Wire Field-Programmable

A1186

Chopper-Stabilized Unipolar Hall Effect Switches

Chopper Stabilization Technique

A limiting factor for switchpoint accuracy when using Hall
effect technology is the small signal voltage developed across
the Hall element. This voltage is proportionally small relative to
the offset that can be produced at the output of the Hall sensor
device. This makes it difficult to process the signal and maintain
an accurate, reliable output over the specified temperature and
voltage range.

Chopper stabilization is a unique approach used to minimize
Hall offset on the chip. The Allegro patented technique, dynamic
quadrature offset cancellation, removes key sources of the output
drift induced by temperature and package stress. This offset
reduction technique is based on a signal modulation-demodula­tion process. The undesired offset signal is separated from the
magnetically induced signal in the frequency domain through
modulation. The subsequent demodulation acts as a modulation
process for the offset causing the magnetically induced signal
to recover its original spectrum at base band while the dc offset
becomes a high frequency signal. Then, using a low-pass filter,
the signal passes while the modulated dc offset is suppressed.

The chopper stabilization technique uses a 200 kHz high fre­quency clock. For demodulation process, a sample-and-hold

technique is used, where the sampling is performed at twice
the chopper frequency (400KHz). The sampling demodulation
process produces higher accuracy and faster signal processing
capability. Using this chopper stabilization approach, the chip is
desensitized to the effects of temperature and stress. This tech­nique produces devices that have an extremely stable quiescent
Hall output voltage, is immune to thermal stress, and has precise
recoverability after temperature cycling. This technique is made
possible through the use of a BiCMOS process which allows the
use of low-offset and low-noise amplifiers in combination with
high-density logic integration and sample-and-hold circuits.

The repeatability of switching with a magnetic field is slightly
affected using a chopper technique. The Allegro high frequency
chopping approach minimizes the affect of jitter and makes it
imperceptible in most applications. Applications that may notice
the degradation are those that require the precise sensing of alter­nating magnetic fields such as ring magnet speed sensing. For
those applications, Allegro recommends the “low jitter” family
of digital sensors.

Regulator

Clock/Logic

Low-Pass

Hall Element

Amp

Figure 2. Chopper stabilization circuit (dynamic quadrature offset cancellation)

Filter

Hold

Sample and

Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com

7

A1185 and

Ultrasensitive T wo-Wire Field-Programmable

A1186

Chopper-Stabilized Unipolar Hall Effect Switches

Application Information

For additional general application information, visit the Allegro
Web site at www. allegromicro.com.

Typical Application and Programming Circuit

The A118x family of devices MUST be protected by an exter­nal bypass capacitor, C
VCC, and the ground pin, GND, of the device. C
both external noise and the noise generated by the chopper-sta­bilization function. As shown in figure 3, a 0.01 μF capacitor
is typical. (For programming the device, a 0.1 μF capacitor is
recommended for proper fuse blowing.)

Installation of C

BYP

it to the A118x pins are no greater than 5 mm in length. (For
programming the device, the capacitor may be further away from
the device, including mounting on the board used for program­ming the device.)

C

serves only to protect the A118x internal circuitry. All

BYP

high-frequency interferences conducted along the supply lines

, connected between the supply pin,

BYP

reduces

BYP

must ensure that the traces that connect

are passed directly to the load through C

. As a result, the

BYP

load ECU (electronic control unit) must have sufficient protec­tion, other than C

A series resistor on the supply side, R
tion with C

BYP

When determining the minimum V
device, the voltage drops across R

, must be taken into consideration. The typical value for

R

SENSE

R

is approximately 100 Ω. (All programming, including

SENSE

, installed in parallel with the A118x.

BYP

(not shown), in combina-

S

, creates a filter for EMI pulses.

requirement of the A118x

CC

and the ECU sense resistor,

S

code and lock-bit programming, should be done with direct
connections to VCC and GND, with the use of a 0.1uF bypass
capacitor. Programming across the series resistor or sense resis­tor may not allow enough energy to properly blow the fuses
in the device, as required for proper programming. The result
would be incorrect switchpoints.

V+

VCC

A118x

ECU

R

GND

A

B

SENSE

GND

A

Figure 3. Typical application circuit

B

C

BYP

0.01 uF

B

Package UA Only

Maximum separation 5 mm

Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com

8

A1185 and

Ultrasensitive T wo-Wire Field-Programmable

A1186

Chopper-Stabilized Unipolar Hall Effect Switches

Power Derating

The device must be operated below the maximum junction
temperature of the device, T

. Under certain combinations of

J(max)

peak conditions, reliable operation may require derating sup­plied power or improving the heat dissipation properties of the
application. This section presents a procedure for correlating
factors affecting operating TJ. (Thermal data is also available on
the Allegro MicroSystems Web site.)

The Package Thermal Resistance, R

, is a figure of merit sum-

θJA

marizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity,
K, of the printed circuit board, including adjacent devices and
traces. Radiation from the die through the device case, R
relatively small component of R

. Ambient air temperature,

θJA

θJC

, is

TA, and air motion are significant external factors, damped by
overmolding.

The effect of varying power levels (Power Dissipation, PD), can
be estimated. The following formulas represent the fundamental
relationships used to estimate TJ, at PD.

PD = VIN × I

ΔT = PD × R

IN

(2)

θJA

(1)

Example: Reliability for V

at TA = 150°C, package UA, using

CC

minimum-K PCB.

Observe the worst-case ratings for the device, specifically:
R

165°C/W, T

θJA =

I

CC(max) = 17

mA.

Calculate the maximum allowable power level, P

J(max) =

165°C, V

CC(max) =

24 V, and

D(max)

. First,

invert equation 3:

ΔT

max

= T

– TA = 165 °C – 150 °C = 15 °C

J(max)

This provides the allowable increase to TJ resulting from internal
power dissipation. Then, invert equation 2:

P

D(max)

= ΔT

max

÷ R

= 15°C ÷ 165 °C/W = 91 mW

θJA

Finally, invert equation 1 with respect to voltage:

V

CC(est)

= P

D(max)

÷ I

= 91 mW ÷ 17 mA = 5 V

CC(max)

The result indicates that, at TA, the application and device can
dissipate adequate amounts of heat at voltages ≤V

Compare V
able operation between V
R

. If V

θJA

V

is reliable under these conditions.

CC(max)

CC(est)

CC(est)

to V

≥ V

. If V

CC(max)

CC(est)

CC(max)

CC(est)

and V

CC(max)

, then operation between V

≤ V

CC(max)

requires enhanced

.

CC(est)

, then reli-

CC(est)

and

TJ = TA + ΔT (3)

For example, given common conditions such as: T

V

= 12 V, I

CC

P

= VCC × I

D

ΔT = PD × R

= 4 mA, and R

CC

= 12 V × 4 mA = 48 mW

CC

= 48 mW × 140 °C/W = 7°C

θJA

θJA

= 140 °C/W, then:

TJ = TA + ΔT = 25°C + 7°C = 32°C

A worst-case estimate, P
able power level (V
at a selected R

and TA.

θJA

CC(max)

, represents the maximum allow-

D(max)

, I

), without exceeding T

CC(max)

= 25°C,

A

J(max)

,

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115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com

9

A1185 and

Ultrasensitive T wo-Wire Field-Programmable

A1186

Chopper-Stabilized Unipolar Hall Effect Switches

Programming Protocol

The operate switchpoint, B

, can be field-programmed. To do

OP

so, a coded series of voltage pulses through the VCC pin is used
to set bitfields in onboard registers. The effect on the device
output can be monitored, and the registers can be cleared and
set repeatedly until the required BOP is achieved. To make the
setting permanent, bitfield-level solid state fuses are blown, and
finally, a device-level fuse is blown, blocking any further cod­ing. It is not necessary to program the release switchpoint, BRP ,
because the difference between BOP and BRP , referred to as the
hysteresis, B

The range of values between B

HYS

, is fixed.

OP(min)

and B

OP(max)

is scaled to
31 increments. The actual change in magnetic flux (G) repre­sented by each increment is indicated by B

(see the Operating

RES

Characteristics table; however, testing is the only method for
verifying the resulting B

). For programming, the 31 incre-

OP

ments are individually identified using 5 data bits, which are
physically represented by 5 bitfields in the onboard registers.
By setting these bitfields, the corresponding calibration value is
programmed into the device.

Three voltage levels are used in programming the device: a low
voltage, V

, a minimum required to sustain register settings; a

PL

mid-level voltage, VPM , used to increment the address counter
in the device; and a high voltage, VPH , used to separate sets of
VPM pulses (when short in duration) and to blow fuses (when
long in duration). A fourth voltage level, essentially 0 V, is used
to clear the registers between pulse sequences. The pulse values
are shown in the Programming Protocol Characteristics table and
in figure 4.

V+

V

PH

V

PM

V

PL

T

0

T

d(1)

Figure 4. Pulse amplitudes and durations

d(P)

T

d(0)

t

Additional information on device programming and program­ming products is available on www. allegromicro.com. Program­ming hardware is available for purchase, and programming
software is available free of charge.

Code Programming. Each bitfield must be individually set. To

do so, a pulse sequence must be transmitted for each bitfield that
is being set to 1. If more than one bitfield is being set to 1, all
pulse sequences must be sent, one after the other, without allow­ing VCC to fall to zero (which clears the registers).

The same pulse sequence is used to provisionally set bitfields as
is used to permanently set bitfield-level fuses. The only differ­ence is that when provisionally setting bitfields, no fuse-blowing
pulse is sent at the end of the pulse sequence.

PROGRAMMING PROTOCOL CHARACTERISTICS, over operating temperature range, unless otherwise noted

Characteristic Symbol Test Conditions Min. Typ. Max. Units

V

Programming Voltage

1

V

V

Programming Current

2

t

Pulse Width

t

t

Pulse Rise Time t

Pulse Fall Time t

1

Programming voltages are measured at the VCC pin.

2

A bypass capacitor with a minimum capacitance of 0.1 μF must be connected from VCC to the GND pin of the A118x device in order to

Minimum voltage range during programming 4.5 5.0 5.5 V

PL

PM

PH

I

tr = 11 μs; 5 V → 26 V; C

PP

OFF time between programming bits 20 - - μs

d(0)

Pulse duration for enable and addressing

d(1)

sequences

Pulse duration for fuse blowing 100 300 - μs

d(P)

VPL to VPM; VPL to V

r

VPM to VPL; VPH to V

f

PH

= 0.1 μF - 190 - mA

BYP

PL

11.5 12.5 13.5 V

25 26 27 V

20 - - μs

5-20μs

5 - 100 μs

provide the current necessary to blow the fuse.

Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com

10

A1185 and

Ultrasensitive T wo-Wire Field-Programmable

A1186

Chopper-Stabilized Unipolar Hall Effect Switches

The pulse sequences consist of the following groups of pulses:

1. An enable sequence.

2. A bitfield address sequence.

3. When permanently setting the bitfield, a long V

fuse-blow-

PH

ing pulse. (Note: Blown bit fuses cannot be reset.)

4. When permanently setting the bitfield, the level of VCC must

be allowed to drop to zero between each pulse sequence, in
order to clear all registers. However, when provisionally set­ting bitfields, V

must be maintained at VPL between pulse

CC

sequences, in order to maintain the prior bitfield settings while
preparing to set additional bitfields.

Bitfields that are not set are evaluated as zeros. The bitfield-level
fuses for 0 value bitfields are never blown. This prevents inad-

V+

V

PH

vertently setting the bitfield to 1. Instead, blowing the device­level fuse protects the 0 bitfields from being accidentally set in
the future.

When provisionally trying the calibration value, one pulse
sequence is used, using decimal values. The sequence for setting
the value 5

is shown in figure 5.

10

When permanently setting values, the bitfields must be set indi­vidually, and 510 must be programmed as binary 101. Bit 3 is
set to 1 (0001002, which is 410), then bit 1 is set to 1 (0000012,
which is 1

). Bit 2 is ignored, and so remains 0.Two pulse

10

sequences for permanently setting the calibration value 5 are
shown in figure 6. The final V

pulse is maintained for a longer

PH

period, enough to blow the corresponding bitfield-level fuse.

V

PM

V

PL

0

Enable Address Clear

Try 5

10

Figure 5. Pulse sequence to provisionally try calibration value 5.

V+

V

PH

V

PM

V

PL

0

Enable

Figure 6. Pulse sequence to permanently encode calibration value 5 (101 binary, or

bitfield address 3 and bitfield address 1).

Address

Encode 001002 (410)

Optional

Monitoring

t

Blow BlowEnable

Encode 00001

Address

(110)

2

t

Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com

11

A1185 and

Ultrasensitive T wo-Wire Field-Programmable

A1186

Chopper-Stabilized Unipolar Hall Effect Switches

Enabling Addressing Mode. The first segment of code is a

keying sequence used to enable the bitfield addressing mode. As
shown in figure 7, this segment consists of one short VPH pulse,
one VPM pulse, and one short VPH pulse, with no supply inter­ruptions. This sequence is designed to prevent the device from
being programmed accidentally, such as by noise on the supply
line.

Address Selection. After addressing mode is enabled, the

target bitfield address, is indicated by a series of VPM pulses, as
shown in figure 8.

V+

V

PH

V

PM

V

PL

0

t

Figure 7. Addressing mode enable pulse sequence

V+

V

PH

V

PM

V

PL

Address 1

Address 2

Address n ( ≤ 127)

Lock Bit Programming. After the desired B

calibration value

OP

is programmed, and all of the corresponding bitfield-level fuses
are blown, the device-level fuse should be blown. To do so, the
lock bit (bitfield address 32) should be encoded as 1 and have
its fuse blown. This is done in the same manner as permanently
setting the other bitfields, as shown in figure 9.

0

Figure 8. Pulse sequence to select addresses

V+

V

PH

V

PM

V

PL

0

Falling edge of final BOP address digit

128 pulses

Enable

Address Blow

Encode Lock Bit

Figure 9. Pulse sequence to encode lock bit

t

t

Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com

12

A1185 and

Ultrasensitive T wo-Wire Field-Programmable

A1186

A
B

Chopper-Stabilized Unipolar Hall Effect Switches

Package LH, 3-Pin (SOT-23W)

Preliminary dimensions, for reference only
Dimensions in millimeters
U.S. Customary dimensions (in.) in brackets, for reference only
(reference JEDEC TO-236 AB, except case width and terminal tip-to-tip)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown

Hall element (not to scale)
Active Area Depth 0.28 [.011]

3X

C0.10 [.004]

0.50

.020

3X

0.30

.012

0.20 [.008] M C A B

0.95 .037

3.04

.120

2.80

.110

3

1.90 .075

3.00

.118

2.70

.106

0.15 [.006] M C A B
A

1.49

.059

NOM

A

A

A

21

0.96
NOM

0.15

0.00

2.10

1.85
.038

B

.083
.073

SEATING
PLANE

1.17

0.75
.006

.000

.046
.030

B

C

8º
0º

0.20

.008

0.08

.003

0.60

.024

0.25

.010

0.25 .010

SEATING PLANE

GAUGE PLANE

1. VCC

2. No connection

3. GND

Package LH, 3-pin SOT

3

NC

Pin-out Drawings

1. VCC

2. GND

3. GND

Package UA, 3-pin SIP

1 2 3

Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com

13

A1185 and

Ultrasensitive T wo-Wire Field-Programmable

A1186

Chopper-Stabilized Unipolar Hall Effect Switches

Package UA, 3-Pin SIP

.164

4.17

.159

4.04

C

D

.0805

.122
.117

3.10

2.97

.640
.600

16.26

15.24

.0565
NOM

.085
MAX

1.44

2.16

2.04

NOM

D

A

D

B

.062
.058

.031
REF

.017
.014

1.57

1.47

0.79

0.44

0.35

231

.019

0.48

.014

0.36

.050

1.27

NOM

Dimensions in inches
Metric dimensions (mm) in brackets, for reference only

A

Dambar removal protrusion (6X)

B

Ejector mark on opposite side

C

Active Area Depth .0195 [0.50] NOM

D

Hall element (not to scale)

The products described herein are manufactured under one or more of the following U.S. patents: 5,045,920; 5,264,783; 5,442,283; 5,389,889;
5,581,179; 5,517,112; 5,619,137; 5,621,319; 5,650,719; 5,686,894; 5,694,038; 5,729,130; 5,917,320; and other patents pending.

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to
permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.

Allegro products are not authorized for use as critical components in life-support devices or sys tems without express written approval.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its

use; nor for any in fringe ment of patents or other rights of third parties which may result from its use.
Copyright © 2004, 2006 Allegro MicroSystems, Inc.

Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com

14