Datasheet 9403APC Datasheet (Fairchild Semiconductor)

9403A
First-In First-Out (FIFO) Buffer Memory

9403A First-In First-Out (FIFO) Buffer Memory

April 1989
Revised June 1999

General Description

The 9403A is an expandable fall-through type high-speed
First-In First-Out (FIFO) B uffer Memory optimized for high
speed disk or tape co ntrollers and communication buffer
applications. It is organized as 16 -wor ds by 4 -bit s and may
be expanded to any number of words or any number of bits
in multiples of four. Data may be entered or extracted asyn­chronously in serial or par allel, allowing econ omical i mple­mentation of buffer memories.

The 9403A has 3-STATE outputs which provide added ver­satility and is fully compatible with all TTL families.

Features

■ Serial or parallel input

■ Serial or parallel output

■ Expandable without external logic

■ 3-STATE outputs

■ Fully compatible with all TTL families

■ Slim 24-pin package

Ordering Code:

Order Number Package Number Package Description

9403APC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.400 Wide

Devices also availab le in Tape and Reel. Specify by appending the suffix letter “X” to the o rdering code.

Logic Symbol Connection Diagram

© 1999 Fairchild Semiconductor Corporation DS010193.prf www.fairchildsemi.com

Unit Loading/Fan Out

9403A

Block Diagram

Pin Names Description U.L. Input IIH/I

HIGH/LOW Output IOH/I

D0–D

8

D

S

P

L

CPSI
IES
TTS
OES
TOS
TOP Transfer Out Parallel 2.0/0.667 40 µA/400 µA
MR
OE
CPSO

- Q

Q

0

Q

S

IRF
ORE

Parallel Data Inputs 2.0/0.667 40 µA/400 µA
Serial Data Input 2.0/0.667 40 µA/400 µA
Parallel Load Input 2.0/0.667 40 µA/400 µA
Serial In put Clock 2.0/0.667 40 µA/400 µA
Serial In put Enable 2.0/0.66 7 40 µA/400 µA
Transfer to Stack Input 2.0/0.667 40 µA/400 µA
Serial Output Enable 2.0/0.667 40 µA/400 µA
Transfer Out Serial 2.0/0.667 40 µA/400 µA

Master Reset 2.0/0.667 40 µA/400 µA
Output Enable 2.0/0.667 40 µA/400 µA
Serial Output Clock 2.0/0.667 40 µA/400 µA
Parallel Data Outputs 285/26.7 5.7 mA/16 mA

3

Serial Data Output 285/26.7 5.7 mA/16 mA
Input Register Full 20/13.3 −400 µA/8 mA
Output Register Empty 20/13.3 −400 µA/8 mA

IL

OL

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Functional Description

As shown in the block diagram the 49403A consists of
three sections:

1. An Input Register with parallel and serial data inputs as
well as control inputs and outputs for input handshak­ing and expansion.

2. A 4-bit wi de, 1 4-word deep fall- throu gh sta ck with se lf­contained control logic.

3. An Output Register with parallel and serial data outputs
as well as control inputs and ou tputs for output hand­shaking and expansion.

Since these three sections operate asynchronously and
almost independently, they will be described separately
below.

INPUT REGISTER (DATA ENTRY)

The Input Register can receive data in either bit-serial or in
4-bit parallel form. It stores this data until it is sent to the
fall-through stack and generates the necessa ry status a nd
control signals.

Figure 1 is a conceptual logic dia gram of th e inpu t section.
As described later, this 5-bit register is initialized by setting

the F

flip-flop and res ettin g t he oth er fl ip- flops. The Q out-

3

put of the last flip-fl op (FC) is brought out as the “Inpu t
Register Full” output (IRF

). After initialization this output is

HIGH.

Parallel Entry—A HIGH on the PL input loads the D

0-D3

inputs into the F0-F3 flip-flops and sets the FC flip-flop. This
forces the IRF

is full. During parallel entry, the CPSI
parallel expansi on is not be ing implem ented, IES

output LOW indicating that the input register

input must be LOW. If

must be

LOW to establish row mastership (see Expansion section).
Serial Entry—Data on the D

, F2, F1, F0, FC shift register on ea ch HIGH-to -LOW

the F

3

transition of the CPS I

input is serially entered into

S

clock input, provided IES a nd P L are

LOW.
After the fourth clock transition, the four data bits are

located in the four flip-flops, F
forcing the IRF

output LOW and interna lly inhibiting CPSI

. The FC flip-flop is set,

0-F3

clock pulses from affecting the reg ister, Figure 2 illustrates
the final positions in a 94 03A resulting fr om a 64-bit seri al
bit train. B

is the first bit, B63 the last bit.

0

9403A

FIGURE 1. Conceptual Input Section

FIGURE 2. Final Positions in a 9403A Resulting from a 64-Bit Serial Train

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Transfer to the Stack—The outputs of Flip-Flops F0-F
feed the stack. A LO W level on the TTS input initiates a

“fall-through” action. If the top location of the stack is

9403A

empty, data is loaded into the stack and the input register is
re-initialized. Note that this initialization is postponed until
PL is LOW again. Thus, automatic FIFO action is achieved
by connecting the IRF

output to the TTS input.

An RS Flip-Flop (the Request Initialization Flip-Flop sho wn
in Figure 10) in the c ontrol section records the fact that
data has been transferred to the stack. This prevents multi­ple entry of the same word into the stac k despite the fact

and TTS may still be LOW. The Request Initializa-

the IRF
tion Flip-Flop is not cleared until PL goes LOW. Once in the

stack, data falls throu gh the stack automatically, pausing

3

only when it is necessary to wait for an empty next location.
In the 9403A as in most modern FIFO designs, the M R
input only initializes the stack contro l section and does not
clear the data.

OUTPUT REGISTER (DATA EXTRACTION)

The Output Register receives 4-bit data words from the
bottom stack location, stores it and outputs data on a 3­STATE 4-bit parallel data bus or on a 3- STATE serial data
bus. The output section generates and receives the neces­sary status and cont rol signals. Figure 3 is a conceptual
logic diagram of the output section.

FIGURE 3. Conceptual Output Section

Parallel Data Extraction—When the FIFO is empty after a
LOW pulse is applied to MR

) output is LOW. After data has been en ter ed in to th e

(ORE

, the Output Register Empty

FIFO and has fallen through to the bottom stack location, it

is transferred into th e Output Register provid ed the “Trans­fer Out Parallel” (TOP) input is HIGH. As a result of the
data transfer O RE

goes HIGH, indicating valid da ta on the
data outputs (provided the 3-STATE buffer is enabled).
TOP can now be used to clock out the next word. When
TOP goes LOW, ORE

will go LOW indicating that the out­put data has been extracted, bu t the data itself rem ains on
the output bus until the next HIGH level at TOP permits the
transfer of the next wo rd (if a vailab le) in to the Ou tput Reg ­ister. During parallel data extraction CPSO

should be LOW.
TOS should be grounded for single slice operati on or con ­nected to the appropriate ORE

for expanded operation

(see Expansion section).
TOP is not edge triggered. Ther efore, if TOP goes HIGH

before data is available from the stack, but data does
become available befo re TOP goes LOW again , that data
will be transferred into the Output Register. However, inter­nal control circuitry prevents the same data from being

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transferred twice. If TOP goes HIGH and retur ns to LOW
before data is available fr om the sta ck, ORE

remains LOW

indicating that there is no valid data at the outputs.

Serial Data Extraction—When the FIFO is empty after a
LOW pulse is applied to MR

) output is LOW. After data has bee n e nte red into the

(ORE

, the Output Register Empty

FIFO and has fallen through to the bottom stack location, it
is transferred into the Output Register provided TOS

is

LOW and TOP is HIGH. As a result of the data trans fer

goes HIGH indicating valid data in the register. The 3-

ORE
STATE Serial Data Output, Q

, is automatically enabled

S

and puts the first data bit on the output bus. Data is serially
shifted out on the HIGH-to-LOW transition of CPSO
prevent false shifting, CPSO

should be LOW when the new

. To

word is being loaded into the Output Regist er. The fourth
transition empties the shift register, forces ORE
LOW and disables the serial output, Q

For serial operation the ORE

output may be tied to the TOS

(refer to Figure 3).

S

output

input, requesting a new word from the stack as soon as the
previous one has been shifted out.

EXPANSION

Vertical Expansion—The 9403A may be vertically
expanded to store more words w ithout external par ts. The
interconnection is necessary to form a 46-word by 4-bit
FIFO are shown in Figur e 4. Using the same technique,
and FIFO of (15n + 1 )-word s by 4- bits can be constr ucted,
where n is the number of devices. Note that expansion

does not sacrifice any of the 9403A’s flexibility for serial/
parallel input and output.

FIGURE 4. A Vertical Expansion Scheme

Horizontal Expansion—The 9403A can also be horizon­tally expanded to store long words (in multiples of four bits)
without external logic. The interconnections necessar y to
form a 16-word by 12-bit FIFO are shown in Figure 5.
Using the same technique, any FIFO of 16 words by 4n bits
can be constructed, where n is the num ber of dev ices. T he

output of the right most device (most significant device)

IRF
is connected to the TTS

output of the most significan t device is connected to

ORE

inputs of all devices. As in the vertical expansion

the TOS
scheme, horizontal expansion does not sacrifice a ny of the

9403A’s flexibility for serial/parallel input and output.

inputs of all devices. Similarly, the

Horizontal and Vertical Expansion—The 9403A can be
expanded in both the horizontal and vertical directions
without any external pa rts and wi thou t sacrifici ng any of its

FIFO’s flexibility for serial/parallel input and output. The
interconnections necessary to form a 31-word by 16-bit
FIFO are shown in Figure 6 . Using the same technique,
any FIFO of (15m + 1)-words by (4n)-bits can be con­structed, where m is the number of device s in a column
and n is the number of devices in a row. Figure 7 and Fig­ure 8 show the timing d iagrams for serial data en try and
extraction for the 31-w ord by 16-bit FIFO show n in Figure

6. The final positio n o f dat a af ter serial insertion of 49 6 bi t s
into the FIFO array of Figure 6 is shown in Figure 9.

Interlocking Circuitry—Most conventual FIFO designs
provide status signal s analogous to IRF
ever, when these devices are operated in arrays, variations
in unit to unit o perating speed require externa l gating to
assure all devices have completed an operation. The

9403A incorporates simple but effective “master/slave”
interlocking circuitry to elimin ate the ne ed for ext ernal gat­ing.

In the 9403A array of Figure 6 device s 1 and 5 a re defined
as “row masters” and the other devices are slaves to the
master in their row. No slave in a given row will initialize its
Input Register until it has received LOW on its IE S
from a row master or a slave of higher priority.

In a similar fash ion, the ORE
HIGH until their OES
locking scheme ensures that new input data may be
accepted by the array when the IRF
slave in that row goe s HIGH and that output data for the
array may be extracted when the ORE
the output row goes HIGH.

The row master is estab lished by connecting its IES
to ground while a slave receives it IES
output of the next higher prior ity device. When an ar ray of
9403A FIFOs is initialized with a LOW on the MR
all devices, the IRF outputs of all devices will be HIGH.
Thus, only the row master receives a LOW on the IES
during initialization. Figure 10 is a conceptual logic diagram
of the internal circuitry which determines master/slave
operation. Whenever MR
Latch is set. Whenever TTS
ization Flip-Flop will be set. If the Master Latch is HIGH, the
input Register will be immediately initialized and the
Request Initialization Flip-Flop reset. If the Mast er Latch is
reset, the Input Register is not initialized until IES
LOW. In array operation, activ ating the TTS
ple input register i nitialization from the row master to the
last slave.

A similar operation takes place for the output register.
Either a TOS
ation and sets the ORE
Latch is set, the last Output Register Flip-Fl op is set and
ORE
put will be LOW until an OES

or TOP input initiates a load-from-stack oper-

goes HIGH. If the Master latch is reset, the ORE out-

outputs of slaves will not go

inputs have gone HIGH. This inter-

and IES are LOW, the Master

goes LOW the Request Initial-

Request Flip-Flop. If the Master

input is received.

and ORE. How-

input

output of the final
of the final slave in

input

input from the IRF

inputs of

input

goes

initiates a rip-

9403A

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9403A

FIGURE 5. A Horizontal Expansion Scheme

FIGURE 6. A 31x16 FIFO Array

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FIGURE 7. Serial Data Entry for Array of Figure 6

9403A

FIGURE 8. Serial Data Extraction for Array of Figure 6

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9403A

FIGURE 9. Final Position of a 496-Bit Serial Input

FIGURE 10. Conceptual Diagram, Interlocking Circuitry

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Absolute Maximum Ratings(Note 1) Recommended Operating

Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +175°C

Pin Potential to Ground Pin −0.5V to +7.0V

V

CC

Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Output

in HIGH State (with V

CC

= 0V)
Standard Output −0.5V to V
3-STATE Output −0.5V to +5.5V

Current Applied to Output

in LOW State (Max) twice the rated I

OL

Conditions

Free Air Ambient Temperature 0°C to +70°C
Supply Voltage +4.5V to +5.5V

Note 1: Absolute maximum ratings are values beyon d which the device
may be damaged or have its useful life impaired . Functional operation

CC

under these condit ions is not implied.
Note 2: Either voltage limit or curren t limit is sufficient to protec t in puts.

(mA)

DC Electrical Characteristics

Symbol Parameter

V
V
V
V

V

I
I
I
I
I
I
I
I

IH
IL
CD
OH

OL

IH
BVI
IL
OZH
OZL
OS
CEX
CC

Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
Input LOW Voltage 0.8 V Recognized as a LOW Signal
Input Clamp Diode Voltage −1.5 V Min IIN = −18 mA
Output HIGH 10% V
Voltage 10% V
Output LOW 10% V
Voltage 10% V
Input HIGH Current 40 µAMaxVIN = 2.7V
Input HIGH Current Breakdown Test 100 µAMaxVIN = 7.0V
Input LOW Current −0.45 mA Max VIN = 0.4V
Output Leakage Current 100 µAMaxV
Output Leakage Current −100 µAMaxV
Output Short-Circuit Current −30 −130 mA Max V
Output HIGH Leakage Current 250 µAMaxV
Power Supply Current 170 mA Max VO = LOW

Min

Typ Max

CC
CC
CC
CC

2.4 V Min IOH = −400 µA (IRF, ORE)

2.4 IOH = −5.7 mA (Qn, Qs)

0.5 IOL = 16 Ma (Qn, Qs)

Units

0.5 V Min IOL = 8 mA (IRF, ORE)

V

CC

OUT
OUT
OUT
OUT

= 2.4V
= 0.5V
= 0V
= V

CC

9403A

Conditions

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AC Electrical Characteristics

9403A

Symbol Parameter

t

PHL

t

PLH

t

PLH

t

PHL

t

PLH
PHL

t

PHL

t

PHL

t

PLH

t

PLH

t

PLH

t

PLH

Propagation Delay, 1.5 20.0 1.5 21.0
Negative-Going
CPSI to IRF Output Figure 11
Propagation Delay, 1.5 36.0 1.5 38.0 Figure 12
Negative-Going
TTS to IRF
Propagation Delay, 1.5 28.0 1.5 29.0
Negative-Going 1.5 28.0 1.5 29.0 Figure 14
CPSO to QS Output
Propagation Delay, 1.5 46.0 1.5 48.0
Positive-Going 1.5 46.0 1.5 48.0 Figure 15
TOP to Outputs Q0-Q

3

Propagation Delay, 1.5 35.0 1.5 37.0
Negative-Going Figure 14
CPSO to ORE
Propagation Delay, 1.5 37.0 1.5 39.0
Negative-Going
TOP to ORE
Propagation Delay, 1.5 47.0 1.5 49.0
Positive-Going
TOP to ORE
Propagation Delay, 1.5 42.5 1.5 45.0 ns Figure 13
Negative-Going Figure 14
TOS to Positive Going ORE
Propagation Delay, 1.5 28.0 1.5 29.0 ns
Positive-Going
PL to Negative-Going IRF Figure 17
Propagation Delay, 1.5 24.0 1.5 25.0 Figure 18
Negative-Going
PL to Positive-Going IRF

TA = +25°CT

= 0°C to 70°C

A

VCC = +5.0V VCC = +5.0V

CL = 50 pF CL = 50 pF

Min Max Min Max

Units

ns

ns

nst

ns

ns

Figure

Number

Figure 13

Figure 13

Figure 15

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AC Electrical Characteristics

Symbol Parameter

t

t

t

t

t
t
t
t
t
t

t
t

t
t
t
t

t

t

PLH

PLH

PLH

PHL

PZH
PZL
PHZ
PLZ
PZH
PZL

PHZ
PLZ

PZH
PZL
DFT
AP

AS

DBU

Propagation Delay, 1.5 39.5 1.5 41.0

OES to ORE
Propagation Delay, 1.5 20.0 1.5 21.0

IES to Positive-Going IRF
Propagation Delay, 1.5 20.0 1.5 20.0
MR to IRF
Propagation Delay, 1.5 33.0 1.5 35.0
MR to ORE
Propagation Delay, 1.5 14.0 1.5 14.0
OE to Q0, Q1, Q2, Q

3

Propagation Delay, 1.5 14.0 1.5 14.0
OE to Q0, Q1, Q2, Q

3

Propagation Delay, 1.5 16.5 1.5 17.0
Negative-Going 1.5 17.0 1.5 17.0
OES to Q

S

Propagation Delay, 1.5 14.0 1.5 14.0
Negative-Going 1.5 14.0 1.5 14.0
OES to Q

S

Turn On Time 1.5 60.0 1.5 60.0
TOS to Q

S

Fall Through Time 500 500 ns Figure 16
Parallel Appearance Time, −19.0 6.5 −20.0 7.0
ORE to Q0-Q

3

Serial Appearance Time, −9.5 14.5 −10.0 15.0
ORE to Q

S

Bubble-Up Time 470 500 ns

TA = +25°CT

= 0°C to +70°C

A

VCC = +5.0V VCC = +5.0V

CL = 50 pF CL = 50 pF

Min Max Min Max

1.5 14.0 1.5 14.0

1.5 14.0 1.5 14.0

1.5 60.0 1.5 60.0

Units

nsPositive-Going

ns Figure 18Positive-Going

ns

ns

ns

ns

ns

ns

9403A

Figure

Number

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AC Operating Requirements

9403A

Symbol Parameter

tS (H) Setup Time, HIGH or LOW 15.5 16.0
tS (L) DS to Negative CPSI 15.5 16.0 Figure 11
tH (H) Hold Time, HIGH or LOW 2.0 2.0 Figure 12
tH (L) DS to CPSI 2.0 2.0
tS (L) Set-Time, LOW 18.0 18.0

tS (L) Set-Up Time, LOW 65.0 70.0

tS (H) Set-Up time, HIGH or LOW 0 0
tS (L) Parallel Inputs to PL 0 0
tH (H) Hold Time, HIGH or LOW 0 0
tH (L) Parallel Inputs to PL 0 0
tW(H) CPSI Pulse Width 30 32
tW(L) HIGH or LOW 20 20 Figure 12
tW(H) PL Pulse Width, HIGH 16.5 17.0

tW(L) TTS Pulse Width, LOW 16.0 17.0

tW(L) MR Pulse Width, LOW 15.0 15.0 ns Figure 16
tW(H) TOP Pulse Width 15.0 17.0
tW(L) HIGH or LOW 15.0 15.0
tW(H) CPSO Pulse Width 17.0 17.0
tW(L) HIGH or LOW 17.0 18.0 Figure 14
t

REC

Negative-Going IES to CPSI

Negative-Going TTS to CPSI

Serial or Parallel Mode Figure 12

Recovery Time 16.5 19.0
MR to Any Input

TA = +25°CT

VCC = +5.0V VCC = +5.0V

Min Max Min Max

= 0°C to +70°C

A

Units

ns

ns Figure 12

ns Figure 12

ns

ns

ns

ns

ns Figure 15

ns

ns Figure 16

Figure

Number

Figure 11

Figure 17
Figure 18
Figure 11

Figure 13
Figure 14

Figure 13

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Timing Waveforms

Conditions: stack not full, IES, PL LOW

FIGURE 11. Serial Input, Unexpanded or Master Operation

9403A

Conditions: stack not full, IES

Conditions: data in stack, TOP HIGH, IES

HIGH when initiated, PL LOW

FIGURE 12. Serial Input, Expanded Slave Operation

FIGURE 13. Serial Output, Unexpanded or Master Operation

LOW when initiated, OES LOW

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Timing Waveforms (Continued)

9403A

Conditions: data in stack, TOP HIGH, IES

FIGURE 14. Serial Output, Slave Operation

Conditions: IES

LOW when initiated, OE, CPSO LOW; data available in stack

FIGURE 15. Parallel Output, 4-Bit Word or Master in Parallel Expansion

HIGH when initiated

Conditions: TTS

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connected to IRF, TOS connected to ORE, IES, OES, OE, CPSO LOW, TOP HIGH

FIGURE 16. Fall Through Time

Timing Waveforms (Continued)

9403A

Conditions: stack not full, IES

FIGURE 17. Parallel Load Mode, 4-Bit Word (Unexpanded) or Master in Parallel Expansion

Conditions: stack not full, device initialized (Note 3) with IES

Note 3: Initialization requires a master reset to oc c ur after power has bee n applied.
Note 4: TTS
Note 5: If stack if full, IRF

normally connected to IRF.

LOW when initialized

HIGH

FIGURE 18. Parallel Load, Slave Mode

will stay LOW.

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Physical Dimensions inches (millimeters) unless otherwise noted

9403A First-In First-Out (FIFO) Buffer Memory

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.400 Wide

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea­sonably expected to result in a significan t injury to the
user.

Package Number N24E

2. A critical component in any compon ent of a lif e supp ort
device or system whose failu re to perform can be rea­sonably expected to ca use the fa i lure of the li fe su pp ort
device or system, or to affect its safety or effectiveness.

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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.