Page 1
DATASHEET
High Definition Interface
DSP
SPDIF
Ports
Port A
Port B
Port C
Port D
Port E
Port F
SPDIF Out 1
SPDIF Out 2
Port G
Port H
Port I
SPDIF In
TEN CHANNEL HD AUDIO CODEC
Description
The 92HD73C codec is a low power optimized, high fidelity,
6-channel audio codec compatible with Intel’s High
Definition (HD) Audio Interface. The 92HD73C codec
provides stereo 24-bit resolution with sample rates up to
192kHz. Dual SPDIF provides connectivity to consumer
electronic equipment that is WLP compliant. The 92HD73C
provides high quality, HD Audio capability to multimedia
notebook and desktop PC applications.
Features
• 6 Channels (3 stereo DACs and 2 stereo ADCs) with
24-bit resolution
• Supports 5.1 audio
• Microsoft WLP 3/4 premium logo compliant, as
defined in WLP 3.09
• Optimized and flexible power management with
pop/click mitigation
• 2 independent S/PDIF Output converters for WLP
compliant HDMI/SPDIF support.
92HD73C
• Support for 1.5V and 3.3V HDA signaling with
runtime selection
• Digital microphone input (mono, stereo, or quad
array)
• 4 adjustable VREF Out pins for microphone bias
• High performance analog mixer
• 9 stereo analog ports with presence detect
c a pa b i l i ty
• Two-pin volume up/down control
• Digital and Analog PC Beep to all outputs
• Integrated headphone amps (3)
• Sample rates up to 192kHz
• +3.3 V, +4 V, +4.75 V and +5 V analog power supply
options
• Package Options
• 48-pin QFP RoHS package
• 48-pin QFP RoHS package INDUSTRIAL TEMP
Block Diagram
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Software Support
• Intuitive graphical user interface that allows configurability and preference settings
• SKPI (Kernel Processing Interface)
• Enables plug-ins that can operate globally on all audio streams of the system
• 12 band fully parametric equalizer (SKPI plug-in)
• Constant, system-level effects tuned to optimize a particular platform can be combined with
user-mode “presets” tailored for specific acoustical environments and applications
• System-level effects automatically disabled when external audio connections made
• Dynamics Processing (SKPI plug-in)
• Enables improved voice articulation
• Compressor/limiter allows higher average noise level without resonances or damage to
speakers.
• TSI Vista APO wrapper
• Enables multiple APOs to be used with the TSI Driver
• Microphone Beam Forming, Acoustic Echo Cancellation, and Noise Suppression
• Dynamic Stream Switching
• Improved multi-streaming user experience with less support calls
• Dolby PC Entertainment Experience Logo Program
• Dolby Master Studio ™ (MS)
• Dolby Home Theater™ (HT)
• Dolby Sound Room™
• Dolby Technologies
• Dolby Headphone™, Dolby Virtual Speaker™
• Dolby ProLogic II™, Dolby ProLogic IIx™
• Dolby Digital Live™
• Maxx Player™
•WOW
TM
from Waves
and Tru SurroundTM from SRS
(SR)
(DDL)
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TABLE OF CONTENTS
1. DESCRIPTION ........................................................................................................................ 11
1.1. Overview ..........................................................................................................................................11
1.2. Orderable Part Numbers .................................................................................................................. 11
1.3. Block Diagram .................................................................................................................................12
1.4. Detailed Description .........................................................................................................................13
1.4.1. Port Functionality ...............................................................................................................13
1.4.2. Port Characteristics ............................................................................................................13
1.4.3. Jack Detect ........................................................................................................................14
1.4.4. SPDIF Output .....................................................................................................................14
1.4.5. SPDIF Input .......................................................................................................................16
1.4.6. Analog Mixer ......................................................................................................................16
1.4.7. Input Multiplexers ...............................................................................................................17
1.4.8. ADC Multiplexers ...............................................................................................................17
1.4.9. Power Management ...........................................................................................................17
1.4.10. Low-voltage HDA Signaling .............................................................................................19
1.4.11. Multi-channel capture .......................................................................................................19
1.4.12. EAPD ...............................................................................................................................21
1.4.13. Digital Microphone Support ..............................................................................................23
1.4.14. PC-Beep ..........................................................................................................................28
1.4.15. Headphone Drivers ..........................................................................................................28
1.4.16. GPIO ................................................................................................................................29
1.4.17. External Volume Control ..................................................................................................30
2. CHARACTERISTICS ............................................................................................................... 32
2.1. Electrical Specifications ...................................................................................................................32
2.1.1. Absolute Maximum Ratings ...............................................................................................32
2.1.2. Recommended Operating Conditions ................................................................................32
2.2. 92HD73C 5V, 4.75V, and 3.3V Analog Performance Characteristics ..............................................33
3. PORT CONFIGURATIONS ..................................................................................................... 39
4. FUNCTIONAL BLOCK DIAGRAMS ....................................................................................... 40
5. WIDGET INFORMATION AND SUPPORTED COMMAND VERBS ....................................... 41
5.1. Widget List ......................................................................................................................................42
5.2. Pin Configuration Default Register Settings .....................................................................................43
6. WIDGET INFORMATION ........................................................................................................ 44
6.1. Root Node (NID = 00) ......................................................................................................................44
6.1.1. Root VendorID ...................................................................................................................44
6.1.2. Root RevID ........................................................................................................................45
6.2. AFG Node (NID = 01 .......................................................................................................................46
6.2.1. AFG Reset .........................................................................................................................46
6.2.2. AFG NodeInfo ....................................................................................................................46
6.2.3. AFG FGType ......................................................................................................................46
6.2.4. AFG AFGCap .....................................................................................................................47
6.2.5. AFG PCMCap ....................................................................................................................48
6.2.6. AFG StreamCap ................................................................................................................49
6.2.7. AFG InAmpCap ..................................................................................................................49
6.2.8. AFG PwrStateCap .............................................................................................................50
6.2.9. AFG GPIOCnt ....................................................................................................................50
6.2.10. AFG OutAmpCap .............................................................................................................51
6.2.12. AFG UnsolResp ...............................................................................................................52
6.2.11. AFG PwrState ..................................................................................................................52
6.2.13. AFG GPIO ........................................................................................................................53
6.2.14. AFG GPIOEn ...................................................................................................................54
6.2.15. AFG GPIODir ...................................................................................................................55
6.2.16. AFG GPIOWakeEn ..........................................................................................................56
6.2.17. AFG GPIOUnsol ..............................................................................................................58
6.2.18. AFG GPIOSticky ..............................................................................................................59
6.2.19. AFG SubID .......................................................................................................................60
6.2.20. AFG GPIOPlrty ................................................................................................................61
6.2.21. AFG GPIODrive ...............................................................................................................62
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6.2.22. AFG DMic ........................................................................................................................63
6.2.23. AFG AnaBeep ..................................................................................................................64
6.3. Port A Node (NID = 0A) ...................................................................................................................64
6.3.1. PortA WCap .......................................................................................................................64
6.3.2. PortA PinCap .....................................................................................................................65
6.3.3. PortA ConLst ......................................................................................................................66
6.3.4. PortA ConLstEntry0 ...........................................................................................................67
6.3.5. PortA ConSelectCtrl ...........................................................................................................67
6.3.6. PortA PinWCntrl .................................................................................................................68
6.3.7. PortA UnsolResp ...............................................................................................................68
6.3.8. PortA ChSense ..................................................................................................................69
6.3.9. PortA InAmpLeft .................................................................................................................70
6.3.10. PortA InAmpRight ............................................................................................................70
6.3.11. PortA ConfigDefault .........................................................................................................70
6.4. PortB Node (NID = 0B) ....................................................................................................................72
6.4.1. PortB WCap .......................................................................................................................72
6.4.2. PortB PinCap .....................................................................................................................73
6.4.3. PortB ConLstEntry0 ...........................................................................................................74
6.4.4. PortB ConLstEntry0 ...........................................................................................................74
6.4.5. PortB ConSelectCtrl ...........................................................................................................75
6.4.6. PortB PinWCntrl .................................................................................................................75
6.4.7. PortB UnsolResp ...............................................................................................................76
6.4.8. PortB ChSense ..................................................................................................................77
6.4.9. PortB InAmpLeft .................................................................................................................77
6.4.10. PortD InAmpRight ............................................................................................................78
6.4.11. PortB ConfigDefault .........................................................................................................78
6.5. Port C Node (NID = 0C) ...................................................................................................................79
6.5.1. PortC WCap .......................................................................................................................79
6.5.2. PortC PinCap .....................................................................................................................81
6.5.3. PortC ConLst .....................................................................................................................82
6.5.4. PortC ConLstEntry0 ...........................................................................................................82
6.5.5. PortC ConSelectCtrl ...........................................................................................................83
6.5.6. PortC PinWCntrl .................................................................................................................83
6.5.7. PortC UnsolResp ...............................................................................................................84
6.5.8. PortC ChSense ..................................................................................................................84
6.5.9. PortC InAmpLeft ................................................................................................................85
6.5.10. PortC InAmpRight ............................................................................................................85
6.5.11. PortC ConfigDefault .........................................................................................................86
6.6. Port D Node (NID = 0D) ...................................................................................................................87
6.6.1. PortD WCap .......................................................................................................................87
6.6.2. PortD
PinCap
6.6.3. PortD ConLst .....................................................................................................................90
6.6.4. PortD ConLstEntry0 ...........................................................................................................90
6.6.5. PortD ConSelectCtrl ...........................................................................................................91
6.6.6. PortD PinWCntrl .................................................................................................................91
6.6.7. PortD UnsolResp ...............................................................................................................92
6.6.8. PortD ChSense ..................................................................................................................92
6.6.9. PortD InAmpLeft ................................................................................................................93
6.6.10. PortD InAmpRight ............................................................................................................93
6.6.11. PortD ConfigDefault .........................................................................................................94
6.7. PortE Node (NID = 0E) ....................................................................................................................95
6.7.1. PortE WCap .......................................................................................................................95
6.7.2. PortE PinCap .....................................................................................................................96
6.7.3. PortE ConLst ......................................................................................................................97
6.7.4. PortE ConLstEntry0 ...........................................................................................................98
6.7.5. PortE ConSelectCtrl ...........................................................................................................98
6.7.6. PortE PinWCntrl .................................................................................................................99
6.7.7. PortE UnsolResp ...............................................................................................................99
6.7.8. PortE ChSense ................................................................................................................100
.....................................................................................................................89
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6.7.9. PortE InAmpLeft ...............................................................................................................101
6.7.10. PortE InAmpRight ..........................................................................................................101
6.7.11. PortE ConfigDefault .......................................................................................................101
6.8. PortF Node (NID = 0F) ...................................................................................................................103
6.8.1. PortF WCap .....................................................................................................................103
6.8.2. PortF PinCap ...................................................................................................................104
6.8.3. PortF ConLst ....................................................................................................................105
6.8.4. PortF ConLstEntry0 ......................................................................................................... 105
6.8.5. PortF ConSelectCtrl .........................................................................................................106
6.8.6. PortF PinWCntrl ...............................................................................................................106
6.8.7. PortF UnsolResp ..............................................................................................................107
6.8.8. PortF ChSense ................................................................................................................107
6.8.9. PortF InAmpLeft ...............................................................................................................108
6.8.10. PortF InAmpRight ..........................................................................................................108
6.9. PortG Node (NID = 10) ..................................................................................................................109
6.9.1. PortG WCap .....................................................................................................................109
6.9.2. PortG PinCap ...................................................................................................................110
6.9.3. PortG ConLst ...................................................................................................................111
6.9.4. PortG ConLstEntry0 .........................................................................................................112
6.9.5. PortG ConSelectCtrl ........................................................................................................112
6.9.6. PortG PinWCntrl ..............................................................................................................113
6.9.7. PortG UnsolResp .............................................................................................................113
6.9.8. PortG ChSense ................................................................................................................114
6.9.9. PortG InAmpLeft ..............................................................................................................114
6.9.10. PortG InAmpRight ..........................................................................................................115
6.9.11. PortG ConfigDefault .......................................................................................................116
6.10. PortH Node (NID = 11) ................................................................................................................117
6.10.1. PortH WCap ...................................................................................................................117
6.10.2. PortH PinCap .................................................................................................................118
6.10.3. PortH ConLst .................................................................................................................119
6.10.4. PortH ConLstEntry0 .......................................................................................................120
6.10.5. PortH ConSelectCtrl .......................................................................................................120
6.10.6. PortH PinWCntrl .............................................................................................................121
6.10.7. PortH UnsolResp ...........................................................................................................121
6.10.8. PortH ChSense ..............................................................................................................122
6.10.9. PortH InAmpLeft ............................................................................................................122
6.10.10. PortH InAmpRight ........................................................................................................123
6.10.11. PortH ConfigDefault .....................................................................................................124
6.11. PortI Node (NID = 12) ..................................................................................................................125
6.11.1. PortI WCap ....................................................................................................................125
6.11.2. PortI PinCap ...................................................................................................................126
6.11.3. PortI PinWCntrl ..............................................................................................................127
6.11.4. PortI UnsolResp .............................................................................................................127
6.11.5. PortI ChSense ................................................................................................................128
6.11.6. PortI ConfigDefault .........................................................................................................128
6.12. DMic0 Node (NID = 13) ...............................................................................................................130
6.12.1. DMic0 WCap ..................................................................................................................130
6.12.2. DMic0 PinCap ................................................................................................................131
6.12.3. DMic0 PinWCntrl ............................................................................................................132
6.12.4. DMic0 InAmpLeft ...........................................................................................................132
6.12.5. DMic0 InAmpRight ......................................................................................................
6.12.6. DM
ic0 ConfigDefault
6.13. DMic1 Node (NID = 14) ...............................................................................................................134
6.13.1. DMic1 WCap ..................................................................................................................134
6.13.2. DMic1 PinCap ................................................................................................................136
6.13.3. DMic1 PinWCntrl ............................................................................................................137
6.13.4. DMic1 InAmpLeft ...........................................................................................................137
6.13.5. DMic1 InAmpRight .........................................................................................................137
6.13.6. DMic1 ConfigDefault ......................................................................................................138
......................................................................................................133
...133
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6.14. DAC0 Node (NID = 15) ................................................................................................................139
6.14.1. DAC0 WCap ..................................................................................................................139
6.14.2. DAC0 Cnvtr ....................................................................................................................140
6.14.3. DAC0 OutAmpLeft .........................................................................................................141
6.14.4. DAC0 OutAmpRight .......................................................................................................142
6.14.5. DAC0 PwrState ..............................................................................................................142
6.14.6. DAC0 CnvtrID ................................................................................................................143
6.14.7. DAC0 LR ........................................................................................................................143
6.15. DAC1 Node (NID = 16) ................................................................................................................144
6.15.1. DAC1 WCap ..................................................................................................................144
6.15.2. DAC1 Cnvtr ....................................................................................................................145
6.15.3. DAC1 OutAmpLeft .........................................................................................................146
6.15.4. DAC1 OutAmpRight .......................................................................................................147
6.15.5. DAC1 PwrState ..............................................................................................................147
6.15.6. DAC1 CnvtrID ................................................................................................................148
6.15.7. DAC1 LR ........................................................................................................................148
6.16. DAC2 Node (NID = 17) ................................................................................................................149
6.16.1. DAC2 WCap ..................................................................................................................149
6.16.2. DAC2 Cnvtr ....................................................................................................................150
6.16.3. DAC2 OutAmpLeft .........................................................................................................151
6.16.4. DAC2 OutAmpRight .......................................................................................................152
6.16.5. DAC2 PwrState ..............................................................................................................152
6.16.6. DAC2 CnvtrID ................................................................................................................153
6.16.7. DAC2 LR ........................................................................................................................153
6.17. Reserved (NID = 18) ....................................................................................................................154
6.18. Reserved (NID = 19) ....................................................................................................................154
6.19. ADC0 Node (NID = 1A) ................................................................................................................154
6.19.1. ADC0 WCap ..................................................................................................................154
6.19.2. ADC0 ConLst .................................................................................................................155
6.19.3. ADC0 ConLstEntry0 .......................................................................................................156
6.19.4. ADC0 Cnvtr ....................................................................................................................156
6.19.5. ADC0 ProcState .............................................................................................................157
6.19.6. ADC0 PwrState ..............................................................................................................158
6.19.7. ADC0 CnvtrID ................................................................................................................158
6.20. ADC1 Node (NID = 1B) ................................................................................................................159
6.20.1. ADC1 WCap ..................................................................................................................159
6.20.2. ADC1 ConLst .................................................................................................................160
6.20.3. ADC1 ConLstEntry0 .......................................................................................................161
6.20.4. ADC1 Cnvtr ....................................................................................................................161
6.20.5. ADC1 ProcState .............................................................................................................162
6.20.6. ADC1 PwrState ..............................................................................................................163
6.20.7. ADC1 CnvtrID ................................................................................................................163
6.21. DigBeep Node (NID = 1C) ...........................................................................................................164
6.21.1. DigBeep WCap ..............................................................................................................164
6.21.2. DigBeep OutAmpCap ....................................................................................................164
6.21.3. DigBeep OutAmpLeft .....................................................................................................165
6.21.4. DigBeep Gen .................................................................................................................166
6.22. Mixer Node (NID = 1D) ................................................................................................................166
6.22.1. Mixer WCap ...................................................................................................................166
6.22.2. Mixer ConLst ...........................................................................................................
6.22.3. Mixer ConLstEntry0 .......................................................................................................168
6.22.4. Mixer InAmpCap ............................................................................................................169
6.22.5. Mixer InAmpLeft0 ...........................................................................................................169
6.22.6. Mixer InAmpRight0 ........................................................................................................170
6.22.7. Mixer InAmpLeft1 ...........................................................................................................170
6.22.8. Mixer InAmpRight1 ........................................................................................................171
6.22.9. Mixer InAmpLeft2 ...........................................................................................................171
6.22.10. Mixer InAmpRight2 ......................................................................................................172
6.22.11. Mixer InAmpLeft3 .........................................................................................................172
....168
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6.22.12. Mixer InAmpRight3 ......................................................................................................173
6.22.13. Mixer InAmpLeft4 .........................................................................................................173
6.22.14. Mixer InAmpRight4 ......................................................................................................174
6.23. MixerOutVol Node (NID = 1E) .....................................................................................................174
6.23.1. MixerOutVol WCap ........................................................................................................174
6.23.2. MixerOutVol ConLst .......................................................................................................176
6.23.3. MixerOutVol ConLstEntry0 ............................................................................................176
6.23.4. MixerOutVol OutAmpCap ..............................................................................................177
6.23.5. MixerOutVol OutAmpLeft ...............................................................................................177
6.23.6. MixerOutVol OutAmpRight0 ...........................................................................................178
6.24. VolumeKnob Node (NID = 1F) .....................................................................................................178
6.24.1. VolumeKnob WCap .......................................................................................................178
6.24.2. VolumeKnob VolKnobCap .............................................................................................179
6.24.3. VolumeKnob ConLst ......................................................................................................179
6.24.4. VolumeKnob ConLstEntry0 ............................................................................................180
6.24.5. VolumeKnob UnsolResp ................................................................................................180
6.24.6. VolumeKnob Cntrl ..........................................................................................................181
6.24.7. VolumeKnob VS .............................................................................................................181
6.25. ADC0Mux Node (NID = 20) .........................................................................................................182
6.25.1. ADC0Mux WCap ............................................................................................................182
6.25.2. ADC0Mux ConLst ..........................................................................................................183
6.25.3. ADC0Mux ConLstEntry0 ................................................................................................184
6.25.4. ADC0Mux ConSelectCtrl ...............................................................................................184
6.25.5. ADC0Mux LR .................................................................................................................185
6.25.6. ADC0Mux OutAmpCap ..................................................................................................185
6.25.7. ADC0Mux OutAmpLeft ..................................................................................................186
6.25.8. ADC0Mux OutAmpRight ................................................................................................187
6.26. ADC1Mux Node (NID = 21) .........................................................................................................187
6.26.1. ADC1Mux WCap ............................................................................................................187
6.26.2. ADC1Mux ConLst ..........................................................................................................188
6.26.3. ADC1Mux ConLstEntry0 ................................................................................................189
6.26.4. ADC1Mux ConSelectCtrl ...............................................................................................189
6.26.5. ADC1Mux LR .................................................................................................................190
6.26.6. ADC1Mux OutAmpCap ..................................................................................................190
6.26.7. ADC1Mux OutAmpLeft ..................................................................................................191
6.26.8. ADC1Mux OutAmpRight ................................................................................................192
6.27. Dig0Pin Node (NID = 22) .............................................................................................................192
6.27.1. Dig0Pin WCap ...............................................................................................................192
6.27.2. Dig0Pin PinCap ..............................................................................................................193
6.27.3. Dig0Pin ConLst ..............................................................................................................194
6.27.4. Dig0Pin ConLstEntry0 ....................................................................................................195
6.27.5. Dig0Pin ConSelectCtrl ...................................................................................................195
6.27.6. Dig0Pin PinWCntrl .........................................................................................................196
6.27.7. Dig0Pin ConfigDefault ....................................................................................................196
6.28. Dig1Pin Node (NID = 23) .............................................................................................................198
6.28.1. Dig1Pin WCap ...............................................................................................................198
6.28.2. Dig1Pin PinCap ..............................................................................................................199
6.28.3. Dig1Pin ConLst ..............................................................................................................200
6.28.4. Dig1Pin ConLstEntry0 ...............................
6.28.5. Dig1Pin ConSelectCtrl ...................................................................................................201
6.28.6. Dig1Pin PinWCntrl .........................................................................................................201
6.28.7. Dig1Pin ConfigDefault ....................................................................................................202
6.29. Dig2Pin Node (NID = 24) .............................................................................................................203
6.29.1. Dig2Pin WCap ...............................................................................................................203
6.29.2. Dig2Pin PinCap ..............................................................................................................205
6.29.3. Dig2Pin PinWCntrl .........................................................................................................206
6.29.4. Dig2Pin UnsolResp ........................................................................................................206
6.29.5. Dig2Pin ChSense ...........................................................................................................207
6.29.6. Dig2Pin PwrState ...........................................................................................................207
..................................................................200
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6.29.7. Dig2Pin EAPD ................................................................................................................208
6.29.8. Dig2Pin ConfigDefault ....................................................................................................208
6.30. SPDIFOut0 Node (NID = 25) .......................................................................................................210
6.30.1. SPDIFOut0 WCap ..........................................................................................................210
6.30.2. SPDIFOut0 PCMCap .....................................................................................................211
6.30.3. SPDIFOut0 StreamCap .................................................................................................212
6.30.4. SPDIFOut0 Cnvtr ...........................................................................................................213
6.30.5. SPDIFOut0 CnvtrID .......................................................................................................214
6.30.6. SPDIFOut0 DigCnvtr ......................................................................................................214
6.30.7. SPDIFOut0 OutAmpCap ................................................................................................215
6.30.8. SPDIFOut0 OutAmpLeft ................................................................................................216
6.30.9. SPDIFOut0 OutAmpRight ..............................................................................................216
6.31. SPDIFOut1 Node (NID = 26) .......................................................................................................216
6.31.1. SPDIFOut1 WCap ..........................................................................................................216
6.31.2. SPDIFOut1 PCMCap .....................................................................................................218
6.31.3. SPDIFOut1 StreamCap .................................................................................................219
6.31.4. SPDIFOut1 Cnvtr ...........................................................................................................219
6.31.5. SPDIFOut1 CnvtrID .......................................................................................................220
6.31.6. SPDIFOut1 DigCnvtr ......................................................................................................221
6.31.7. SPDIFOut1 OutAmpCap ................................................................................................222
6.31.8. SPDIFOut1 OutAmpLeft ................................................................................................222
6.31.9. SPDIFOut1 OutAmpRight ..............................................................................................223
6.32. SPDIFIn Node (NID = 27) ............................................................................................................223
6.32.1. SPDIFOut1 WCap ..........................................................................................................223
6.32.2. SPDIFInCnvtr .................................................................................................................225
6.32.3. SPDIFIn PCMCap ..........................................................................................................226
6.32.4. SPDIFIn StreamCap ......................................................................................................227
6.32.5. SPDIFIn ConLst .............................................................................................................227
6.32.6. SPDIFIn ConLstEntry0 ...................................................................................................228
6.32.7. SPDIFIn CnvtrID ............................................................................................................228
6.32.8. SPDIFIn DigCnvtr ..........................................................................................................229
6.32.9. SPDIFIn OutAmpCap .....................................................................................................230
6.32.10. SPDIFIn InAmpLeft ......................................................................................................230
6.32.11. SPDIFIn InAmpRight ....................................................................................................231
6.32.12. SPDIFIn VS ..................................................................................................................231
6.32.13. SPDIFIn Status ............................................................................................................232
6.33. InPort0Mux Node (NID = 28) .......................................................................................................235
6.33.1. InPort0Mux WCap ..........................................................................................................235
6.33.2. InPort0Mux ConLst ........................................................................................................236
6.33.3. InPort0Mux ConLstEntry0 ..............................................................................................236
6.33.4. InPort0Mux ConSelectCtrl .............................................................................................237
6.34. InPort1Mux Node (NID = 29) .......................................................................................................237
6.34.1. InPort1Mux WCap ..........................................................................................................237
6.34.2. InPort1Mux ConLst ........................................................................................................239
6.34.3. InPort1Mux ConLstEntry0 ..............................................................................................239
6.34.4. InPort1Mux ConSelectCtrl .............................................................................................240
6.35. InPort2Mux Node (NID = 2A) .......................................................................................................240
6.35.1. InPort2Mux WCap ..........................................................................................................240
6.35.2. InPort2Mux ConLst ........................................................................................................241
6.35.3. InPort2Mux ConLstEntry0 ..............................................................................................242
6.35.4. InPort1Mux ConSelectCtrl .............................................................................................242
6.36. InPort3Mux Node (NID = 2B) .......................................................................................................243
6.36.1. InPort3Mux WCap .......................................................................................................
Port3Mux ConLst ........................................................................................................244
6.36.2. I
6.36.3. InPort3Mux ConLstEntry0 ..............................................................................................245
6.36.4. InPort3Mux ConSelectCtrl .............................................................................................245
7. DISCLAIMER ......................................................................................................................... 246
8. PINOUTS ............................................................................................................................... 247
8.1. Pin Assignment ..............................................................................................................................247
n
...243
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8.2. Pin Tables for 48-pin QFP ............................................................................................................248
9. PACKAGE OUTLINE AND PACKAGE DIMENSIONS ......................................................... 251
9.1. 48-Pin QFP Package ....................................................................................................................251
10. SOLDER REFLOW PROFILE ............................................................................................. 252
10.1. Standard Reflow Profile Data ......................................................................................................252
10.2. Pb Free Process - Package Classification Reflow Temperatures ..............................................253
11. REVISION HISTORY .........................................................................................................253
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LIST OF FIGURES
Figure 1. 92HD73C Block Diagram ................................................................................................................12
Figure 2. System Diagram ............................................................................................................................12
Figure 3. Multi-channel capture ......................................................................................................................20
Figure 4. Multi-channel timing diagram ..........................................................................................................20
Figure 5. EAPD ..............................................................................................................................................23
Figure 6: Mono Digital Microphone (data is ported to both left and right channels ........................................25
Figure 7: Stereo Digital Microphone Configuration ........................................................................................26
Figure 8: Quad Digital Microphone Configuration ..........................................................................................27
Figure 9: External Volume Control Circuit ......................................................................................................31
Figure 10. Port Configuration .........................................................................................................................39
Figure 11. Functional Block Diagram .............................................................................................................40
Figure 12. Widget Diagram ............................................................................................................................41
Figure 13. Pin Assignment ...........................................................................................................................253
Figure 14. 48-pin QFP Package Drawing ....................................................................................................257
Figure 15. Solder Reflow Profile ..................................................................................................................258
LIST OF TABLES
Table 1. Port Functionality .............................................................................................................................13
Table 2. Analog I/O Port Behavior .................................................................................................................14
Table 4. SPDIF OUT 0 (Pin 48) Behavior ......................................................................................................15
Table 5. SPDIF OUT 1 (Pin 40) Behavior ......................................................................................................15
Table 6. Input Multiplexers .............................................................................................................................17
Table 7. Function state vs. AFG power state .................................................................................................17
Table 10. EAPD Behavior ..............................................................................................................................22
Table 11. Valid Digital Mic Configurations .....................................................................................................24
Table 12. DMIC_CLK and DMIC_0,1 Operation During Power States ..........................................................24
Table 13. GPIO Pin mapping .........................................................................................................................29
Table 14. Electrical Specification: Maximum Ratings ...................................................................................32
Table 15. Recommended Operating Conditions ............................................................................................32
Table 16. 92HD73D 5V, 4.75V, and 3.3V Analog Performance Characteristics ............................................33
Table 17. High Definition Audio Widget .........................................................................................................42
Table 18. Pin Configuration Default Settings .................................................................................................43
Table 19. Command Format for Verb with 4-bit Identifier ..............................................................................45
Table 20. Command Format for Verb with 12-bit Identifier ............................................................................45
Table 21. Solicited Response Format ............................................................................................................45
Table 22. Unsolicited Response Format ........................................................................................................45
Table 23. Digital Pins ...................................................................................................................................254
Table 24. Analog Pins ..................................................................................................................................254
Table 25. Power Pins ...................................................................................................................................255
Table 26. Standard Reflow Profile ...............................................................................................................258
Table 27. Pb-Free Process Reflow ..............................................................................................................259
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1. DESCRIPTION
1.1. Overview
The 92HD73C is a high fidelity, 6-channel audio codec compatible with the Intel High Definition (HD)
Audio Interface. The 92HD73C codec provides high quality, HD Audio capability to desktop and
multi-media notebook.
The 92HD73C is designed to meet or exceed premium logo requirements for Microsoft’s Windows
Logo Program (WLP) 3.09 and revisions 4 as indicated in WLP 3.09.
The 92HD73C provides stereo 24-bit, full duplex resolution supporting sample rates up to 192kHz by
the DAC and ADC. 92HD73C SPDIF outputs support sample rates of 192kHz, 176.4kHz, 96kHz,
88.2kHz, 48kHz, and 44.1kHz. 92HD73C SPDIF input supports sample rates of 96kHz, 88.2kHz,
48kHz, and 44.1kHz. Additional sample rates are supported by the driver software.
The 92HD73C supports a wide range of desktop and consumer 8 channel configurations. The 2
independent SPDIF output interfaces provides connectivity to Consumer Electronic equipment like
Dolby Digital decoders, powered speakers, mini disk drives or to a home entertainment system.
Simultaneous HDMI and SPDIF output is possible.
MIC inputs can be programmed with 0/10/20/30dB boost. For more advanced configurations, the
92HD73C has 8 General Purpose I/O (GPIO).
The port presence detect capabilities allow the codecs to detect when audio devices are connected
to the codec. Load impedance sensing helps identify attached peripherals for easy set-up and a better user experience. The fully parametric TSI SoftEQ can be initiated upon headphone jack insertion
and removal for protection of notebook speakers.
The 92HD73C operates with a 3.3V digital supply and either 3.3V, or 5V analog supply. It can also
work with 1.5V and 3.3V HDA signaling; the correct signalling level is selected dynamically based on
the power supply voltage on the DVDD-IO pin.
The 92HD73C1X is available in a 48-pin LQFP Environmental (ROHS) package.
The 92HD73C1T is available in a 48-pin LQFP Environmental (ROHS) INDUSTRIAL Temperature
package.
Additional products with the same features as the 92HD73C are the 10-channel 92HD73E and the
8-channel 92HD73D.
1.2. Orderable Part Numbers
92HD73C1X5PRGXyyX 6 channel, 5V, 48QFP
92HD73C1T5PRGIyyX 6 channel, 5V, 48QFP i-temp
yy = silicon stepping/revision, contact sales for current data.
Add an “8” to the end for tape and reel delivery. Min/Mult order quantity 2ku.
Contact TSI if interested in 3.3V Analog version.
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92HD73C
High Definition Interface
DSP
SPDIF
Ports
Port A
Port B
Port C
Port D
Port E
Port F
SPDIF Out 1
SPDIF Out 2
Port G
Port H
Port I
SPDIF In
I/O Controller Hub (ICH) CODEC
HD Audio Bus
Head Phone
Speakers
Sub Woofer
Line In
Microphone
Six channel hd audio codec, Premium WLP 3/4 Compliant
1.3. Block Diagram
Figure 1. 92HD73C Block Diagram
Figure 2. System Diagram
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1.4. Detailed Description
1.4.1. Port Functionality
Multi-function (Input / output) ports allow for the highest possible flexibility. 8 bi-directional ports (3
headphone capable) support a wide variety of consumer desktop and mobile system use models.
Table 1. Port Functionality
Pins Port Input Output Headphone
39/41 A Yes Yes Yes Yes Yes
21/22 B Yes Yes Yes Yes Yes
23/24 C Yes Yes Yes Yes
35/36 D Yes Yes Yes Yes
14/15 E Yes Yes Yes Yes
16/17 F Yes Yes Yes
43/44 G Yes Yes Yes
45/46 H Yes Yes Yes
18/19/20 CD (Port I) Yes Yes
48 SPDIF_OUT0 Yes
40 SPDIF_OUT1 Yes
47 SPDIF_IN Yes
4 (CLK=2) DMIC0 Yes Yes
30 (CLK=2) DMIC1 Yes Yes
1
: 40dB boost requires using the TSI driver. When the 40dB mic boost feature is enabled, addi-
Note
Mic Bias
(Vref pin)
Input
boost amp
1
(pseudo differential)
tional gain increases greater than 6dB may result in significant audio quality degradation of the
microphone audio input. In particular, when the 40dB MIC boost is active, the SNR, THD+N and DC
offset will significantly degrade regardless of the input signal level.
CD
1.4.2. Port Characteristics
Universal (Bi-directional) jacks are supported on all ports except the CD input. Ports A, B, and D are
designed to drive a set of 32 ohm (nominal) headphones or a 10K (nominal) load with on board
shunt resistance as low as 20K ohms (typical - used to maintain coupling CAP bias.) Line Level outputs are intended to drive an external 10K speaker load (nominal) and an on board shunt resistor of
20K-47K (nominal). However, applications may support load impedances of 5K ohms and above.
Input ports are 47K (nominal) at the pin.
DAC full scale output and intended full scale input levels are 1V rms. Line output ports and Headphone output ports on 92HD73C may be configured for +3dBV full scale output levels by using a
vendor specific verb.
Output ports are always on to prevent pops/clicks associated with charging and discharging output
coupling capacitors. This maintains proper bias on output coupling caps even in D3 as long as AVDD
is available. Unused ports should be left unconnected. When updating existing designs to use the
92HD73C, ensure that there are no conflicts between the output ports on 92HD73C and existing circuitry.
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AFG Power
State
D0-D2
D3 - -
Input Enable Output Enable Mute Port Behavior
1 1 - Not allowed. Port becomes input.
1 0 - Active - port enabled as input
0 1 0 Active - port enabled as output
0 1 1 Mute - port enabled as output but drives silence
00-
1.4.3. Jack Detect
Plugs inserted to a jack on Ports A, B, C, & D are detected using SENSE_A. Plugs inserted to a jack
on Ports E, F, G, and H are detected using SENSE_B. The following table summarizes the proper
resistor tolerances for different analog supply voltages.
SENSE_C, is different from SENSE_A and SENSE_B. Because SENSE_C only determines the
presence of a plug for the CD port (port I), SENSE_C is a simple digital input pin referenced to the
analog supply. An internal pull-up resistor is provided. No external resistors are needed (jack switch
shorts to ground when a plug is inserted.) If external components are added, or if the pin is driven by
a logic gate, care should be taken to ensure that the pin voltage is above 70% of AVDD when no
plug is in the jack and less than 30% AVDD when a plug is inserted
Inactive - Port keeps coupling caps charged (same
as mute.)
Inactive (lower power) - Port keeps output coupling
caps charged but consumes less power.
AVdd Nominal
Voltage (+/- 5%)
5V 1% 1% 1% 1%
4.75V 1% 1% 1% 1%
4V 0.50% 1% 0.50% 1%
3.3V 0.10% 1% 0.10% 1%
Resistor Tolerance
(If port D used)
See reference design for more information on Jack Detect implementation.
1.4.4. SPDIF Output
All SPDIF Outputs can operate at 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4KHz, and 192KHz as
defined in the Intel High Definition Audio Specification with resolutions up to 24 bits. This insures
compatibility with all consumer audio gear and allows for convenient integration into home theater
systems and media center PCs.
A second independant SPDIF Output is provided as an option for WLP compliant HDMI and SPDIF
outputs. Its function is identical to the primary SPDIF output.
Note: Peak to peak jitter is currently limited to less than 4.5nS (half of the internal master clock cycle)
which does not meet the IEC-60958-3 0.05UI requirement at 192KHz.
SENSE_A
Resistor Tolerance
SENSE_A
(If port D is not used)
Resistor Tolerance
SENSE_B
(If port H used)
Resistor Tolerance
SENSE_B
(If port H is not used)
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The two SPDIF ouput converters can not be aligned in phase with the DACs. Even when attached to
the same stream, the two SPDIF output converters may be misaligned with respect to their frame
boundaries.
SPDIF Outputs on pins 48 and 40 are outlined in tables below. Pin 47 behavior table resides in the
EAPD section
AFG Power
State
D0-D3 Asserted (Low) - - -
D0
D1-D2
D3 De-Asserted (High) - - - Hi-Z (internal pull-down enabled)
AFG Power
State
D0-D3Asserted (Low)----
D0-D3 De-Asserted (High) Enabled - - -
De-Asserted (High) Disabled Disabled - - Hi-Z (internal pull-down enabled)
De-Asserted (High) Disabled Enabled Disabled -
D0
De-Asserted (High) Disabled Enabled Enabled 0
De-Asserted (High) Disabled Enabled Enabled 1-15
RESET# Output Enable
De-Asserted (High) Disabled - - Hi-Z (internal pull-down enabled)
De-Asserted (High) Enabled Disabled -
De-Asserted (High) Enabled Enabled 0
De-Asserted (High) Enabled Enabled 1-15
De-Asserted (High) Disabled - - Hi-Z (internal pull-down enabled)
De-Asserted (High) Enabled - -
RESET#
GPIO 3
Enable
Converter Dig
Output
Enable
Enable
Converter
Dig Enable
Stream ID Pin Behavior
Hi-Z (internal pull-down enabled)
immediately after power on,
otherwise the previous state is
retained until the rising edge of
RESET#
Active - Pin drives 0 (internal
pull-down NA)
Active - Pin drives SPDIF-format,
but data is zeroes (internal
pull-down NA)
Active - Pin drives SPDIFOut0
data (internal pull-down NA)
Active - Pin drives 0 (internal
pull-down NA)
Stream ID Pin Behavior
Hi-Z (internal pull-down enabled)
immediately after power on,
otherwise the previous state is
retained until the rising edge of
RESET#
Active - Pin reflects GPIO7
configuration (internal pull-up
enabled)
Active - Pin drives 0 (internal
pull-down enabled)
Active - Pin drives SPDIF-format,
but data is zeroes (internal
pull-down enabled)
Active - Pin drives SPDIFOut1
data (internal pull-down enabled)
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AFG Power
State
D1-D2
D3 De-Asserted (High) Disabled - - - Hi-Z (internal pull-down enabled)
RESET#
De-Asserted (High) Disabled Disabled - - Hi-Z (internal pull-down enabled)
De-Asserted (High) Disabled Enabled - -
GPIO 3
Enable
Output
Enable
Converter
Dig Enable
Stream ID Pin Behavior
Active - Pin drives 0 (internal
pull-down NA)
1.4.5. SPDIF Input
SPDIF IN can operate at 44.1 KHz, 48 KHz, 88.2 KHz or 96 KHz, and implements internal Jack
Sensing.
A sophisticated digital PLL allows automatic rate detection and accurate data recovery. The ability to
directly accept consumer SPDIF voltage levels eliminates the need for costly external receiver ICs.
Advanced features such as record-slot-select and SPDIF_IN routing to the DAC allow for simultaneous record and play.
1.4.6. Analog Mixer
An analog mixer is available on the 92HD73C. The mixer supports independent gain (-34.5 to
+12dB in 1.5dB steps) on each input as well as independent mutes on each input. A master volume
follows mixing and provides gain from -46.5dB to 0dB in 1.5dB steps.
The following inputs are available:
•CD
• Analog PC_Beep
• Inport0_Mux
• Inport1_Mux
• Inport2_Mux
• Inport3_mux
1.4.7. Input Multiplexers
92HD73C implements 4 port input multiplexers. These multiplexers allow a preselection of one of
four possible inputs:
Inport0_Mux Inport1_Mux Inport2_Mux Inport3_mux
Port APort APort BDAC 0
Port B Port E Port C DAC 1
Port D Port G Port G DAC 2
Port F Port H Port H DAC 3
Table 2. Input Multiplexers
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1.4.8. ADC Multiplexers
92HD73C implements 2 ADC input multiplexers. These multiplexers incorporate the ADC record
gain function (0 to +22.5dB gain in 1.5dB steps) as an output amp and allow a preselection of one of
12 possible inputs:
•DMIC 0
•DMIC 1
• Mixer output
• CD input
•Ports A - H
1.4.9. Power Management
The HD Audio specification defines power states, power state widgets, and power state verbs.
Power management is implemented at several levels. The Audio Function Group (AFG) and all converter widgets support the power state verb F05/705 (as well as the pin widget associated with pin
47.) Converter widgets are active in D0 and inactive in D1-D3.
The following table describes what functionality is active in each power state supported by the AFG.
Table 3. Function state vs. AFG power state
Function D0
SPDIF Outputs On Off Off Off -
SPDIF Inputs On Off Off Off -
Digital Microphone inputs On Off Off Off -
DAC On Off Off Off -
D2S On Off Off Off -
ADC On Off Off Off -
ADC Volume Control On Off Off Off -
Ref ADC On Off Off Off -
Analog Clocks On Off Off Off -
GPIO pins On On On On -
VrefOut Pins On On Off Off -
Input Boost On On Off Off -
Analog mixer On On Off Off -
Mixer Volumes On On Off Off
Analog PC_Beep On On Off Off
Digital PC_Beep On On On On -
Lo Amp On On On Low Drive
HP Amps On On On Low Drive
VAG amp On On On Low Drive
Port Sense On On On On
Reference Bias generator On On On On Programmable
Reference Bandgap core On On On On Programmable
HD Audio-Link On On On On
D1
1
1.No DAC or ADC streams are active. Analog mixing and loop thru are supported.
D2 D3 vendor specific
2
Programmable
2
Programmable
3
Programmable
4
6
Programmable
-
5
5
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2.VAG is kept active when ports are disabled or in D2/D3. Ports may be powered down using vendor specific verbs.
3.VAG is always ramped up and down gradually, except in the case of a sudden power removal. VAG is active in D2/D3 but
in a low power state.
4. BITCLK must be active and both AVDD and DVDD must be available for Port Sense to operate.
5.Vendor specific bit for Ref Top controls VAG generator, Bandgap Reference, and Reference bias generator. Place part into
D3 and power down all ports (using vendor specific verbs) before powering down Ref Top.
6.Obviously not active if BITCLK is not running (Controller in D3).
1.4.9.1. AFG D0
The AFG D0 state is the active state for the device. All functions are active if their power state (if they
support power management at their node level) has been set to D0.
1.4.9.2. AFG D1
D1 is a lower power mode where all converter widgets are disabled. Analog mixer and port functions
are active.
1.4.9.3. AFG D2
The D2 state further reduces power by disabling the mixer and port functions. The port amplifiers
and internal references remain active to keep port coupling caps charged and the system ready for a
quick resume to either the D1 or D0 state.
1.4.9.4. AFG D3
The D3-default state is available for HD Audio compliance. All converters are shut down. Port amplifiers and references are active but in a low power state to prevent pops. Resume times may be longer than those from D2, but still very fast to meet Intel low power goals.
The traditional use for D3 was as a transitional state before power was removed (D3 cold) before the
system entered into standby, hibernate, or shut-down. To conserve power, Intel now promotes using
D3 whenever there are no active streams or other activity that requires the part to consume full
power. The system remains in S0 during this time. When a stream request or user activity requires
the CODEC to become active, the driver will immediately transition the CODEC from D3 to D0. To
enable this use model, the CODEC must resume within 10mS and not pop.
The default power state for the Audio Function Group after reset is D3-default
1.4.9.5. AFG D3 and vendor specific verbs
The programmable values, exposed via vendor-specific settings, are under the TSI Device Driver
control for further power reduction.
1.4.10. Low-voltage HDA Signaling
The 92HD73C is compatible with either 1.5V or 3.3V HDA bus signaling; the voltage selection is
done dynamically based on the input voltage of DVDD_IO.
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Str eam I D
Dat a
Length
ADC0
Left Channel
ADC0
Right Channel
ADC1
Left Channel
ADC1
Right Channel
Str eam I D
Dat a
Length
ADC1
Left Channel
ADC1
Right Channel
ADC0
Left Channel
ADC0
Right Channel
ADC0.CnvrtID.Channel = 0
ADC1.CnvrtID.Channel = 2
ADC0.CnvrtID.Channel = 2
ADC1.CnvrtID.Channel = 0
Six channel hd audio codec, Premium WLP 3/4 Compliant
When in 1.5V mode, the 92HD73C can correctly decode BITCLK, SYNC, RESET# and SDO as they
operate at 1.5V; additionally it will drive SDI and SDO at 1.5V. None of the GPIOs are affected, as
they always function at their nominal voltage (DVDD or AVDD).
1.4.11. Multi-channel capture
The capability to assign multiple ADC “Input Converters” to the same stream is supported to meet
the microphone array requirements of Vista and future operating systems. Single converter streams
are still supported and is done by assigning unique non zero Stream IDs to each converter. All capture devices (ADCs 0 and 1) may be used to create a multi-channel input stream. There are no
restrictions regarding digital microphones. However, the SPDIF input can not be used with an ADC
to create a 4-channel stream. SPDIF_In only supports stereo capture.
The ADC Converters can be associated with a single stream as long as the sample rate and the bits
per sample are the same. The assignment of converter to channel is done using the “CnvtrID” widget
and is restricted to even values. The ADC converters will always put out a stereo sample and therefore require 2 channels per converter.
The stream will not be generated unless all entries for the targeted converters are set identically, and
the total number of assigned converter channels matches the value in the NmbrChan field. These
are listed the “Multi-Converter Stream Critical Entries” table.
An example of a 4 Channel Steam with ADC0 supplying channels 0&1 and ADC1 supplying channels 2&3 is shown below. A 4 Channel stream can be created by assigning the same non-zero
stream id “Strm= N” to both ADC0 and ADC1. The sample rates must be set the same and the number of channels must be set to 4 channels “NmbrChan = 0011”.
Table 4: Example channel mapping
ADC1 CnvtrID (NID = 0x08)
[3:0] Ch = 2
ADC0 CnvtrID (NID = 0x07)
[3:0] Ch = 0
Figure 3. Multi-channel capture
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The following figure describes the bus waveform for a 24-bit, 48KHz capture stream with ID set to 1.
92HD73C
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92HD73C
0
0 0
SDI
BITCLK
1
0
0 1 1 0 0
STREAM ID DATA LENGTH
STREAM TAG
ADC0
L23
ADC0 L0ADC0
R23
ADC0 R0ADC1
L23
ADC1 L0ADC1
R23
ADC1
R0
LEFT LEFTRIGHT RIGHT
ADC0 ADC1
DATA BLOCK
Six channel hd audio codec, Premium WLP 3/4 Compliant
Figure 4. Multi-channel timing diagram
ADC[1:0] Cnvtr Bit Number Sub Field Name Description
[15] StrmType
[14] FrmtSmplRate
[13:11] SmplRateMultp
[10:8] SmplRateDiv
[6:4] BitsPerSmpl
[3:0] NmbrChan
ADC[1:0] CnvtrID Bit Number Sub Field Name Description
Stream Type (TYPE):
0: PCM
1: Non-PCM (not supported)
Sample Base Rate
0= 48kHz
1=44.1KHz
Sample Base Rate Multiple
000=48kHz/44.1kHz or less
001= x2
010= x3 (not supported)
011= x4
100-111= Reserved
Sample Base Rate Divisor
000= Divide by 1
001= Divide by 2 (not supported)
010= Divide by 3 (not supported)
011= Divide by 4 (not supported)
100= Divide by 5 (not supported)
101= Divide by 6 (not supported)
110= Divide by 7 (not supported)
111= Divide by 8 (not supported)
Bits per Sample
000= 8 bits (not supported)
001= 16 bits
010= 20 bits
011= 24 bits
100-111= Reserved
Number of Channels
Number of channels for this stream in each “sample
block” of the “packets” in each “frame” on the link.
0000=1 channel (not supported)
0001 = 2 channels
…
1111= 16 channels.
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Table 5: Multi-Converter Stream Critical Entries.
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[7:4] Strm
[3:0] Ch
Table 5: Multi-Converter Stream Critical Entries.
1.4.12. EAPD
The EAPD pin (pin 47) also supports SPDIF_In and GPIO functions. The pin defaults to EAPD after
power on reset and will remain in EAPD mode until either GPIO is enabled for pin 47 or the port I/O
is enabled to support SPDIF. Although named External Amplifier Power Down (EAPD) by the HD
Audio specification, this pin operates as an external amplifier power up signal. The EAPD value is
reflected on the EAPD pin; a 1 causes the external amplifier to power up, and a 0 causes it to power
down. When the EAPD value = 1, the EAPD pin must be placed in a state appropriate to the current
power state of the associated Pin Widget even though the EAPD value may remain 1. The default
state of this pin is 0 (driving low) and a Pull-down prevents the line from floating high when the part is
in reset.
Software-programmable integer representing link
stream ID used by the converter widget. By
convention stream 0 is reserved as unused.
Integer representing lowest channel used by
converter.
0 and 2 are valid Entries
If assigned to the same stream, one ADC must be
assigned a value of 0 and the other ADC assigned a
value of 2.
AFG Power
State
D0-D3 Asserted (Low) - - -
D0
D1
D2 De-Asserted (High) Disabled - D0-D3 Hi-Z (internal pull-down enabled)
D3 De-Asserted (High) Disabled - D0-D3 Hi-Z (internal pull-down enabled)
RESET# GPIO Enable Input Enable
De-Asserted (High) Enabled - -
De-Asserted (High) Disabled Enabled - Active - Pin is SPDIF_In
De-Asserted (High) Disabled Disabled D0-D1
De-Asserted (High) Disabled Disabled D2-D3 Hi-Z (internal pull-down enabled)
De-Asserted (High) Disabled Enabled -
De-Asserted (High) Disabled Disabled D0-D1
De-Asserted (High) Disabled Disabled D2-D3 Hi-Z (internal pull-down enabled)
EAPD Power
State
Pin Behavior
Hi-Z (internal pull-down enabled)
immediately after power on,
otherwise the previous state is
retained until the rising edge of
RESET#
Active - Pin reflects GPIO0
configuration (internal pull-up
enabled)
Active - Pin drives the value of the
EAPD bit (internal pull-down
enabled)
Inactive - Pin configured as input,
but SPDIF_In idle.
Active - Pin drives the value of the
EAPD bit (internal pull-down
enabled)
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CODEC
Audio L
Audio R
Input L
Input R
EAPD SHUTDOWN
SPKR R-
SPKR R+
SPKR L-
SPKR L+
CODEC
Audio L
Audio R
Input L
Input R
EAPD MUTE
SPKR R-
SPKR R+
SPKR L-
SPKR L+
OR
Six channel hd audio codec, Premium WLP 3/4 Compliant
1.4.13. Digital Microphone Support
Figure 5. EAPD
The digital microphone interface permits connection of a digital microphone(s) to the CODEC via the
DMIC0, DMIC1, and DMIC_CLK 3-pin interface. The DMIC0 and DMIC1 signals are inputs that carry
individual channels of digital Mic data to the ADC. In the event that a single microphone is used, the
data is ported to both ADC channels.
The DMIC_CLK output is controllable from 4.704Mhz, 3.528Mhz, 2.352Mhz, 1.176Mhz and is synchronous to the 24Mhz internal clock. The default frequency is 2.352Mhz.
The two DMIC data inputs are reported as two stereo input pin widgets that incorporate a boost
amplifier. The pin widgets are shown connected to the ADCs through the same multiplexors as the
analog ports. Although the internal implementation is different between the analog ports and the digital microphones, the functionality is the same. In most cases, the default values for the DMIC clock
rate and data sample phase will be appropriate and an audio driver will be able to configure and use
the digital microphones exactly like an analog microphone.
92HD73C supports the following digital microphone configurations:
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Six channel hd audio codec, Premium WLP 3/4 Compliant
Table 6. Valid Digital Mic Configurations
Digital Mics Data Sample ADC Conn. Notes
0 N/A N/A No Digital Microphones
Available on either DMIC_0 or DMIC_1
1 Single Edge 0, or 1
Double Edge on
either DMIC_0 or 1
2
OR
0, or 1
Single Edge on
DMIC_0 and 1
Double Edge on
3
one DMIC pin and
Single Edge on the
0, or 1
second DMIC pin.
4 Double Edge 0, or 1
Both ADC Channels produce data, may be in phase or out by 1/2 DMIC_CLK
period depending upon external configuration and timing
Available on either DMIC_0 or DMIC_1, External logic required to support
sampling on a single Digital Mic pin channel on rising edge and second Digital Mic
right channel on falling edge of DMIC_CLK for those digital microphones that don’t
support alternative clock edge capability. If both DMIC_0 and DMIC_1 are used to
support 2 digital microphones, 2 separate ADC units will be used, however, this
configuration is not recommended since it consumes two stereo ADC resources.
Requires both DMIC_0 or DMIC_1, External logic required to support sampling on
a single Digital Mic pin channel on rising edge and second Digital Mic right
channel on falling edge of DMIC_CLK for those digital microphones that don’t
support alternative clock edge capability. Two ADC units are required to support
this configuration
Connected to DMIC_0 and DMIC_1, External logic required to support sampling
on a single Digital Mic pin channel on rising edge and second Digital Mic right
channel on falling edge of DMIC_CLK for those digital microphones that don’t
support alternative clock edge capability. Two ADC units are required to support
this configuration
Table 7. DMIC_CLK and DMIC_0,1 Operation During Power States
Power State
DMIC Widget
Enabled
D0 Yes Clock Capable Input Capable
DMIC_CLK
Output
DMIC_0,1 Notes
DMIC_CLK Output is Enabled when either DMIC_0 or DMIC_1
Input Widget is Enabled. Otherwise, the DMIC_CLK remains Low
D1-D3 Yes Clock Disabled Input Disabled DMIC_CLK is HIGH-Z with Weak Pull-down
D0-D3 No Clock Disabled Input Disabled DMIC_CLK is HIGH-Z with Weak Pull-down
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DMIC_0
Or
DMIC_1
DMIC_CLK
Right
Channel
Left
Channel
Valid Data Valid Data Valid Data
DMIC_0
OR
DMIC_1
DMIC_CLK
Single Line In
Pin
On-Chip
Multiplexer
Pin
DQ
CK
Digital
Microphone
On-ChipOff-Chip
MUX
Stereo Channels
Output
STEREO
ADC0 or 1
PCM
Six channel hd audio codec, Premium WLP 3/4 Compliant
Figure 6. Mono Digital Microphone (data is ported to both left and right channels
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DMIC_0
Or
DMIC_1
DMIC_CLK
Right
Channel
Left
Channel
Valid
Data R
Valid
Data L
Valid
Data R
Valid
Data L
Valid
Data R
Digital
Microphones
DMIC_CLK
MUX
Stereo Channels
Output
Pin
Pin
External
Multiplexer
On-Chip
Multiplexer
On-ChipOff-Chip
STEREO
ADC0 or 1
PCM
MUX
DMIC_0
Or
DMIC_1
Six channel hd audio codec, Premium WLP 3/4 Compliant
Note: Some Digital Microphone Implementations support data on either edge, therefore, the external
mux may not be required.
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Figure 7. Stereo Digital Microphone Configuration
92HD73C
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92HD73C
DMIC_1
DMIC_CLK
DMIC_0
Right
Channel
Left
Channel
Valid
Data R1
Valid
Data L1
Valid
Data R1
Valid
Data L1
Valid
Data R1
Valid
Data R0
Valid
Data L0
Valid
Data R0
Valid
Data L0
Valid
Data R0
Right
Channel
Left
Channel
MUX
Stereo Channels
Output For
DMIC_0 L&R
On-Chip
Multiplexer
STEREO
ADC0
PCM
MUX
Stereo Channels
Output For
DMIC_1 L&R
On-Chip
Multiplexer
STEREO
ADC1
PCM
Digital
Microphones
DMIC_CLK
Pin
Pin
External
Multiplexer
MUX
DMIC_0
On-ChipOff-Chip
Digital
Microphones
Pin
External
Multiplexer
MUX
DMIC_1
Six channel hd audio codec, Premium WLP 3/4 Compliant
Figure 8. Quad Digital Microphone Configuration
Note: Some Digital Microphone Implementations support data on either edge, therefore, the external
mux may not be required.
1.4.14. PC-Beep
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92HD73C supports both analog and digital PC_Beep functions.
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1.4.14.1. Analog PC-Beep
92HD73C does not support automatic routing of the PC_Beep pin to all outputs when the link is in
reset. Analog PC-Beep may be supported during Link Reset if the mixer is manually configured for
pass-thru. Otherwise, Reset# must be high and Bit_Clk active.
The default values for the vendor specific verb (7EE/FEE in AFG) associated with Analog PC-Beep
are:
• Enable = 0h (Analog PC-Beep disabled - mute)
• volume = 3h (0dB)
Analog PC-Beep is supported in D3, but may be attenuated or distorted depending on the loadimpedance on the port. Line outputs can drive 10K ohm loads in D3 at 1Vrms, but will be current limited when driving lower impedance loads. Enabling or disabling analog PC-Beep may cause a click
or pop sound.
1.4.14.2. Digital PC-Beep
This block uses an 8-bit divider value to generate the PC beep from the 48kHz Azalia sync pulse.
The digital PC_Beep block generates the beep tone on all Pin Complexes that are currently configured as outputs. The HD Audio spec states that the beep tone frequency = (48kHz HD Audio SYNC
rate) / (4*Divider), producing tones from 47 Hz to 12 kHz (logarithmic scale). Other audio sources
are disabled when digital PC_Beep is active.
It should be noted that digital PC Beep is disabled if the divider = 00h.
1.4.15. Headphone Drivers
This product implements a +3dBV output option on headphone capable ports. (HP output and line
output levels are defined as 1Vrms at this time with an option to enable +3dBV FSOV using a vendor
specific verb.) The Microsoft Windows Logo Program allows up to the equivalent of 100ohms in
series. However, an output level of +3dBV at the pin is required to support 300mV at the jack with a
32ohm load and 1V with a 320 ohm load. Microsoft allows device and system manufactures to limit
output voltages to address EU safety requirements. (WLP 3.09 - please refer to the latest Windows
Logo Program requirements from Microsoft.) 92HD73C, however, requires external components
(series resistors) to limit the output voltage to 150mV with a 32 ohm load or secure software limiting
by restricting DAC and mixer gain ranges.
Although 3 Headphone amplifiers are present, only two may be used simultaneously.
Performance will degrade when driving more than one set of headphones. Only one set of headphones (32 ohm nominal) may be connected to a headphone capable port.
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1.4.16. GPIO
1.4.16.1. GPIO Pin mapping and shared functions.
Table 8. GPIO Pin mapping
GPIO
Pin Supply
#
0 47 DVDD YES YES
1 2 DVDD YES CLK YES
2 4 DVDD YES IN YES
3 40 AVDD YES YES
4 29 AVDD YES YES
5 30 AVDD YES IN 50K
6 31 AVDD YES YES
7 37 AVDD YES YES
SPDIFInSPDIF
Out
GPI/O GPI GPO VrefOut DMIC VOL
(GPIO/VOL)
(GPIO/VOL)
1.Default condition.
1.4.16.2. Volume/Digital Microphone/GPIO Selection
There are 3 functions available on pins 2 and 4. To determine which function is actually enabled on
the 2 pins, the order of precedence is followed:
1. If the GPIOs are enabled, they override both Volume Control and Digital Mics
2. If the GPIOs are not enabled through the AFG, then at reset, the Volume control is enabled with
the weak pull-up.
3. If BIOS or other software application enables either Digital Microphones inputs through the Configuration Default Register, the Volume is disconnected and the pull-ups are disconnected with
the weak pull-downs enabled.
Pull
Up
50K
(GPIO)
50K
50K
50K
(GPIO)
1
Pull
Down
1
50K
(SPDIF/EA
PD)
50K
(DMIC)
50K
(DMIC)
1
50K
(SPDIF)
50K
(DMIC)
1.4.16.3. VRefOut/GPIO Selection
Two functions are available on pins 29, 31, and 37. To determine which function is actually enabled,
the order of precedence is followed:
1. If the GPIOx function is enabled, it overrides VRefOut-X
2. If the GPIO function is not enabled through the AFG, then the VrefOut function is enabled and in
its default state.
3. If using a VrefOut pin as GPIO, make sure to incorporate a 10K ohm external pull-up to AVDD to
prevent the pin from floating in GPI mode and to allow proper operation in open-drain GPO
mode.
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1.4.17. External Volume Control
92HD73C incorporates a 2-pin volume control interface. Volume up, down, and mute functions are
easily implemented using 2 push-button switches. The CODEC provides internal pull-up resistors
simplifying external CODEC circuitry. Also, repeat and direct modes of operation add flexibility to the
interface. The typical usage model is for front panel master volume buttons on an entertainment PC,
or case mounted hardware volume control for mobile platforms.
1.4.17.1. Theory of Operation
The codec monitors the volume up/down inputs for a change of state from high to low, and waits for
the inputs to settle. If the inputs have not settled by the end of the de-bounce period, then the value
at the end of the period is used. A 0 (low voltage) on the Down pin will decrement the volume register, while a 0 on the Up pin will increment the volume register. If both inputs are 0 at the same time,
then the volume register will be set to its lowest value (mute). Pressing Up, Down, or both buttons at
the same time when the volume control interface is in mute mode, will cause the part to un-mute.
The de-bounce / repeat rate is selectable from 2.5Hz to 20Hz in 2.5Hz increments using the Volume
Knob VCSR0 verb (FE0) Rate bits (bits 2:0). This value is used for both de-bounce and repeat rates.
The de-bounce period is the time that the CODEC waits for the inputs to settle, and the repeat rate is
the rate at which the CODEC will increment/decrement the volume if a volume button is pushed and
held. When a falling edge is detected on either one of the volume control pins, the codec will wait for
(1/Rate) seconds for the input to settle. If the Continuous bit is set in the Volume Knob VCSR0 verb
(bit 3), then the codec will wait for the de-bounce period to expire then repeatedly increment or decrement the volume register at the rate specified in the Rate bits until the button is released.
1.4.17.2. Modes of Operation
•DIRECT MODE
In Direct mode, the Volume Knob widget directly controls the volume of all of the DACs in the part.
The volume in the Volume Knob widget acts as the master volume and limits the maximum volume
for each of the DAC amplifiers. The amp gain for each of the DACs can also be adjusted using the
DAC amplifiers. However, the actual gain for an individual DAC will be the sum of the Volume Knob
volume and the DAC amplifier volume. For example, if the DAC amplifier gain is set to 0x7F (0dB)
and the Volume Knob volume is set to 0x3F (-48dB) the resulting gain would be -48dB. If the combination of gains is less than -95.25dB (the equivalent to a value of 0x0 for the DAC or Volume Knob
volume settings) then the actual gain will be -95.25dB. For example, if the Volume Knob is set to
0x3F (-48dB) and the DAC amplifier volume is set to 0x1F (-72dB) then the DAC volume will be set
to -95.25dB.
Direct mode is enabled by setting bit 7 in the Volume Knob Cntrl verb (F0F). The volume is reflected
in the Volume Knob Cntrl bits 6:0 and the step size is 0.75dB. In direct mode, software can read or
write the volume in the Volume Knob widget.
• INDIRECT MODE
In indirect mode, the Volume Knob widget does not directly control the DAC amplifier gains. An
event on the volume Up/Down pins will increment/decrement the value in the Volume Knob Cntrl
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verb (F0F) volume bits (bits 6:0) just as in Direct mode. However, instead of adjusting the DAC
amplifier gain, an unsolicited response is generated (if enabled) and the control software must read
the volume in the Volume Knob widget and take appropriate action. Indirect mode is particularly useful when it is undesirable to control all of the DAC amplifier volumes at the same time, or when implementing ADC volume control.
In indirect mode, there are only 128 volume levels in the Volume Knob Cntrl volume bits, the value
will not go beyond the lower and upper limits (0x0 or 0x7F), and an unsolicited response will be
erated if an input event tries to go beyond these limits. Therefore, it is the responsibility of the controlling software to monitor the volume in the Volume Knob Widget and take appropriate action.
Indirect mode is enabled by clearing bit 7 in the Volume Knob Cntrl verb (F0F). The volume is
reflected in the Volume Knob Cntrl bits 6:0 and the step size is 0.75dB. In direct mode, software can
read or write the volume in the Volume Knob widget.
1.4.17.3. Hardware Implementation
gen-
The Volume Knob interface is comprised of two input pins, CODEC pins 2 and 4. Both pins have
internal pull-up resistors, so only two push button switches are required for most implementations.
Typically, a series resistor and shunt capacitor are used to help reduce noise and prevent damage
from ESD and other potential faults. An example circuit is shown below in below.
Figure 9. External Volume Control Circuit
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2. CHARACTERISTICS
2.1. Electrical Specifications
2.1.1. Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 92HD73C. These ratings, which are standard values for TSI commercially rated parts, are stress ratings only. Functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
Item Pin Maximum Rating
Analog maximum supply voltage AVdd 6 Volts
Digital maximum supply voltage DVdd 5.5 Volts
VREFOUT output current 5 mA
Voltage on any pin relative to ground Vss - 0.3 V to Vdd + 0.3 V
Operating temperature
0
-40oC to +85 oC (INDUSTRIAL TEMP)
oC
to +70 oC
Storage temperature -55 oC to +125 oC
Soldering temperature
Soldering temperature information for all available in the package
section of this datasheet.
2.1.2. Recommended Operating Conditions
Table 9. Recommended Operating Conditions
Parameter Min. Typ. Max. Units
Power Supply Voltage Digital - 3.3 V 3.135 3.3 3.465 V
Analog - 3.3 V 3.135 3.3 3.465 V
(Note: With Supply Override Enable
Bit set to force 5 V operation.)
Ambient Operating Temperature 0 +70 C
Case Temperature
Analog - 4 V 3.8 4 4.2 V
Analog - 4.5 V 4.51 4.75 4.99 V
Analog - 5 V 4.75 5 5.25 V
T
Commercial +90 C
case
T
Industrial +110 C
case
ESD: The 92HD73C is an ESD (electrostatic discharge) sensitive device. The human body and test equipment can
accumulate and discharge electrostatic charges up to 4000 Volts without detection. Even though the 92HD73C implements
internal ESD protection circuitry, proper ESD precautions should be followed to avoid damaging the functionality or
performance.
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2.2. 92HD73C 5V, 4.75V, and 3.3V Analog Performance Characteristics
(Tambient = 25 ºC, AVdd = Supply ± 5%, DVdd = 3.3V ± 5%, AVss=DVss=0V; 20Hz to 20KHz swept
sinusoidal input; Sample Frequency = 48 kHz; 0 dB = 1 VRMS, 10K
acterization BW: 20 Hz – 20 kHz, 0 dB settings on all gain stages)
//50pF load, Testbench Char-
Parameter
Digital to Analog Converters
Resolution All 24 Bits
Dynamic Range1: PCM to All Analog
Outputs
SNR2 - DAC to All Line-Out Ports
THD+N3 - DAC to All Line-Out Ports
3
THD+N
SNR
THD+N
THD+N
SNR
THD+N
THD+N
- DAC to All Line-Out Ports
2
- DAC to All Headphone Ports
3
- DAC to All Headphone Ports
3
- DAC to All Headphone Ports
2
- DAC to All Headphone Ports
3
- DAC to All Headphone Ports
3
- DAC to All Headphone Ports
Any Analog Input (ADC) to DAC
Crosstalk
Analog Mixer Disabled, PCM data5V4.75V
Analog Mixer Disabled, 0dB FS
Analog Mixer Disabled,-1dB FS
Analog Mixer Disabled, 10K load,
Analog Mixer Disabled, 0dB FS
Signal, 10K load, PCM data
Analog Mixer Disabled, -1dB FS
Signal, 10K load, PCM data
Analog Mixer Disabled, 32 load,
Analog Mixer Disabled, 0dB FS
Signal, 32 load, PCM data
Analog Mixer Disabled, -1dB FS
Signal, 32 load, PCM data
10KHz Signal Frequency. 0dBV
signal applied to ADC, DACs idle,
Conditions AVdd
-60dB FS signal level
Signal, PCM data
Signal, PCM data
PCM data
PCM data
5V
4.75V
3.3V
3.3V
5V
4.75V
3.3V
5V
4.75V
3.3V
5V
4.75V
3.3V
5V
4.75V
3.3V
5V
4.75V
3.3V
5V
4.75V
3.3V
5V
4.75V
3.3V
5V
4.75V
3.3V
All
Min Typ Max Unit
90
90
85
90
90
85
80
80
80
80
80
80
90
90
85
80
80
80
80
80
80
90
90
85
65
65
65
65
65
65
94
94
88
97
97
88
83
83
83
83
83
83
97
97
88
83
83
83
83
83
83
97
97
88
70
70
70
70
70
70
--80 - dB
ports enabled as output.
Any Analog Input (ADC) to DAC
Crosstalk
DAC L/R crosstalk DAC to LO or HP 20-15KHz into
DAC L/R crosstalk DAC to HP 20-15KHz into 32 load All 65 70 dB
Gain Error
1KHz Signal Frequency
see above
10K load
Analog Mixer Disabled All 0.5 dB
All
All 65 70 dB
--85 - dB
dB
dB
dBr
dBr
dB
dBr
dBr
dB
dBr
dBr
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Parameter
Interchannel Gain Mismatch
D/A Digital Filter Pass Band
4
D/A Digital Filter Transition Band
D/A Digital Filter Stop Band
D/A Digital Filter Stop Band Rejection
D/A Out-of-Band Rejection
6
Group Delay (48KHz sample rate)
Attenuation, Gain Step Size DIGITAL
DAC Offset Voltage
Deviation from Linear Phase
Analog Outputs
Full Scale All Line-Outs
Full Scale All Line-Outs
Conditions AVdd
Analog Mixer Disabled All 0.5 dB
All
All
All
5
DAC PCM Data
DAC PCM Data
All
All
All
All
All
All
5V
4.75V
3.3V
5V
4.75V
3.3V
Min Typ Max Unit
20 - 21,000 Hz
21,00
0
31,00
0
- 31,000 Hz
--Hz
-100 - - dB
-55 - - dB
-- 1ms
-0.75 - dB
-1020mV
- 1 10 deg.
1.00
1.00
0.707
2.83
2.83
2.00
1.07
1.07
0.758
3.03
3.03
2.14
-Vrms
-Vp-p
All Headphone Capable Outputs
32load
Amplifier output impedance Line Outputs
Headphone Outputs
Analog inputs
Full Scale Input Voltage
0dB Boost @4.75V
(input voltage required for 0dB FS
output)
All Analog Inputs with boost
10dB Boost
All Analog Inputs with boost
20dB Boost
All Analog Inputs with boost
30dB Boost
Input Impedance
Input Capacitance
Analog Mixer
2
SNR
- All Line-Inputs or DACs to A, B,
and D headphone capable outputs
Analog Mixer Enabled, 10K load.
DAC playing silence, line inputs
driven by ATE. Gain set to 0dB
5V
4.75V
3.3V
All
5V
4.75V
3.3V
5V
4.75V
3.3V
5V
4.75V
3.3V
5V
4.75V
3.3V
All
All
5V
4.75V
3.3V
40
40
31
60
60
42
150
0.1
-
mW
(peak)
Ohms
1.05 1.10 - Vrms
0.31 - - Vrms
0.10 - - Vrms
0.03 - - Vrms
-50 -
K
-15 - pF
85
85
85
90
90
90
dB
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Parameter
THD+N3 - All Line-Inputs or DACs to A, B,
and D headphone capable outputs
2
- All Line-Inputs or DACs to A, B,
SNR
and D headphone capable outputs
THD+N3 - All Line-Inputs or DACs to A, B,
and D headphone capable outputs
2
- DAC to All Line-Out Ports (C, E, F,
SNR
G, and H)
THD+N3 - DAC to All Line-Out Ports (C, E,
F, G, and H)
Analog Mixer Enabled, 0dB FS
Analog Mixer Enabled, 32 load.
DAC playing silence, Line inputs
Analog Mixer Enabled, 0dB FS
Analog Mixer Enabled, DACs playing
silence, line inputs driven by ATE.
Analog Mixer Enabled, 0dB FS
Attenuation, Gain Step Size ANALOG
Gain Drift
Analog to Digital Converter
Resolution All 24 Bits
Dynamic Range1, All Analog Inputs to
7
High Pass Filer Enabled, -60dB FS,
A/D
SNR2- All Analog Inputs to A/D
High Pass Filter enabled
Conditions AVdd
Signal, 10K load
driven by ATE.
Signal, 32 load
Gain set to 0dB
Signal, , 10K load
No boost
5V
4.75V
3.3V
5V
4.75V
3.3V
5V
4.75V
3.3V
5V
4.75V
3.3V
5V
4.75V
3.3V
All
All
5V
4.75V
3.3V
5V
4.75V
3.3V
Min Typ Max Unit
70
70
70
85
85
85
60
60
60
85
85
85
70
70
70
75
75
75
90
90
90
70
70
70
90
90
90
75
75
75
-1.5 - dB
- 100 - ppm/ºC
86
86
83
86
86
83
90
90
85
90
90
85
dBr
dB
dBr
dB
dBr
dB
dB
THD+N3 All Analog Inputs to A/D
High Pass Filter enabled, -1dB
FS signal level
THD+N3 All Analog Inputs to A/D
High Pass Filter enabled, -3dB
FS signal level
Analog Frequency Response
A/D Digital Filter Pass Band
8
4
A/D Digital Filter Transition Band
A/D Digital Filter Stop Band
A/D Digital Filter Stop Band Rejection
Group Delay
Any unselected analog Input to ADC
Crosstalk
Any unselected analog Input to ADC
Crosstalk
ADC L/R crosstalk Any selected input to ADC 20-15Khz All -65 dB
5
48 KHz sample rate All
10KHz Signal Frequency
1KHz Signal Frequency
5V
4.75V
3.3V
5V
4.75V
3.3V
All
All
All
All
All
All
All
75
75
65
75
75
65
10 - 30,000 Hz
20 - 21,000 Hz
21,00
0
31,00
0
-100 -90 - dB
-- 1ms
-65 -80 - dB
-65 -85 - dB
85
85
dBr
75
85
85
dBr
75
- 31,000 Hz
--Hz
TSI™ CONFIDENTIAL
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Six channel hd audio codec, Premium WLP 3/4 Compliant
Parameter
DAC to ADC crosstalk DAC output 0dBFS. All outputs
loaded. Input to ADC open. 20-15Khz
Spurious Tone Rejection
9
Conditions AVdd
Attenuation, Gain Step Size
(analog)
Gain Drift
Interchannel Gain Mismatch ADC
Power Supply
Power Supply Rejection Ratio 10kHz
Power Supply Rejection Ratio 1kHz
D0 (7.1 Playback)
10
Didd
Aidd
D0 (Stereo Playback)
Didd
Aidd
D0 (idle)
D1
D2
D3
Differential Power
Voltage Reference Outputs
10
Didd
Aidd
10
D1 Didd
D1 Aidd
10
D2 Didd
D2 Aidd
10
D3 Didd
D3 Aidd
10
One Stereo ADC Didd
One Stereo ADC Aidd
One Stereo DAC Didd
One Stereo DAC Aidd
VREFOut
10
10
Single 7.1 stream. No ADC or SPDIF
3.3V 68
5.0V, 4.75V, & 3.3V 50
Single 2 channel stream. No ADC or
SPDIF
3.3V 38
5.0V, 4.75V, & 3.3V 37
All converters enabled but no streams
playing
3.3V 55
5.0V, 4.75V, & 3.3V 72
Analog mixer active, all converters
and ports off
3.3V 14
5.0V, 4.75V, & 3.3V 35
All converters, ports and mixer off
3.3V 14
5.0V, 4.75V, & 3.3V
Anti-pop enabled
3.3V 3
5.0V, 4.75V, & 3.3V
Per converter power consumption
3.3V 11
5.0V, 4.75V, & 3.3V
3.3V 10
5.0V, 4.75V, & 3.3V
Min Typ Max Unit
All -55 dB
All
All
All
All
All
All
- -100 - dB
-1.5 - dB
- 100 - ppm/ºC
--0.5dB
--60 - dB
--70 - dB
mA
mA
mA
mA
mA
mA
mA
mA
mA
28 mA
mA
14 mA
mA
3mA
mA
4mA
All
0.5 X
AVdd
-V
TSI™ CONFIDENTIAL
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Six channel hd audio codec, Premium WLP 3/4 Compliant
Parameter
VREFILT (VAG)
Phased Locked Loop
PLL lock time
PLL (or HD Audio Bit CLK) 24MHz
clock jitter
ESD / Latchup
Latch-up
ESD - Human Body Model
Charged Device Model As described in JESD22-C101 All 500 1K V
As described in JESD78A Class II All
As described in JESD22-A114-B All
Conditions AVdd
All
All
All
Min Typ Max Unit
0.45 X
AVdd
96 200 usec
150 500 psec
70 degC
2K 3K V
1.Dynamic Range is the ratio of the full scale signal to the noise output with a -60dBFS signal as defined in AES17
as SNR in the presence of signal and outlined in AES6id, measured “A weighted” over 20 Hz to 20 kHz bandwidth
2.Ratio of Full Scale signal to idle channel noise output is measured “A weighted” over a 20 Hz to a 20 kHz bandwidth. (AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio).
3.THD+N ratio as defined in AES17 and outlined in AES6id,non-weighted, over 20 Hz to 20 kHz bandwidth.Results at the jack
are dependent on external components and will likely be 1 - 2dB worse.
4.Peak-to-Peak Ripple over Passband meets ± 0.125dB limits, 48 kHz or 44.1 kHz Sample Frequency. 1dB limit.
5.Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise.
6.The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a
bandwidth 28.8 to 100 kHz, with respect to a 1 Vrms DAC output.
oC
7.Gain drift is the change in analog volume control gain for each step across the supported 0
o
referenced to the 25
C gain value and specified in ppm per oC
TO 70 oC temperature range
8.± 1dB limits for Line Output & 0 dB gain, at -20dBV
9.Spurious tone rejection is tested with ADC dither enabled and compared to ADC performance without dither.
10.Can be set to 0.5 or 0.8 AVdd.
V
TSI™ CONFIDENTIAL
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92HD73C
Page 37
92HD73C
3 stereo DACs / 2 stereo ADCs, 8 ports UJ. 9 stereo ports total. Two SPDIF outputs. 3 HEADPHONE PORTS
DAC output can be mixed with inputs for record or playback.
HDMI
C
D
DAC 1
FRONT
LI,MIC
Rear
B
MIC,LI
DAC 0
HP
A
SPDIF_OUT
Front
E
MIC,LI
Entertainment PC
G
F
DAC 2
REAR SURR
CTR/LFE
DAC 0
SPDIF_IN
HDMI/Display Port
C
D
DAC 1
FRONT
LI,MIC / CTR-LFE
Rear
B
MIC,LI / HP
DAC0 / ADC0
HP / MIC,LI
A
SPDIF_OUT
Front
E
MIC,LI / REAR SURR
Consumer Desktop
SPDIF_IN
VOLUME
0
1
2
3
4
6
8
9
10
11
7
5
A
M
P
Mic Array
H I
Internal
C
LI,MIC
B
MIC,LI
DAC 0
HP
A
SPDIF_OUT
Side
Mobile
G
F
DAC 1
REAR SURR
CTR/LFE
DAC 2
DAC 0
EAPD
Digital Mic
Array
E
MIC,LI
DAC 0
HP
D
Dock
ADC0 / DAC0
G
F
DAC 2
REAR SURR
CTR/LFE
DAC 0
5-Stack Option
ADC1/DAC0
ADC1/DAC2
I
Video IN
ADC1
HDMI/Display Port
OR
ADC 0
ADC 0
ADC 1
ADC1
ADC1
ADC0
Six channel hd audio codec, Premium WLP 3/4 Compliant
3. PORT CONFIGURATIONS
Figure 10. Port Configuration
TSI™ CONFIDENTIAL
65 V 1.4 09/14
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92HD73C
Stream &
Channel
Select
DAC 0
Stream &
Channel
Select
Stream &
Channel
Select
HD Audio LINK LOGIC
PCM to
SPDIF OUT
SPDIF OUT0
vol
Pin Complex
Pins 35 /36
DAC 1
vol
PORT D
Digital
Mute
Digital
Mute
Vendor
Specific
MUX
ADC0
Pin 48
Pin 2
DMIC_0
DMIC_0
No Bias
MUX
ADC1
MUX
DMIC_1
DMIC_1
Pin 3
Stream &
Channel
Select
Pin Complex
Pins 39 /41
PORT A
Mic Bias
volmute
vol
vol
mute
mute
volmute
CD
volmute
Analog PC_BEEP
Digital Microphone volume and mute is
done after the ADC but shown here and in
widget list as same as analog path.
Stream &
Channel
Select
PCM to
SPDIF OUT
ADC0
MUX
ADC1
DAC0
DAC1
Boost
+0/+10/+20/+30 dB
Boost
+0/+10/+20/+30 dB
DMIC
DMIC
EAPD/SPDIF_IN
Pin 40
Stream &
Channel
Select
DAC 2
vol
Digital
Mute
MUX
DAC2
Pin Complex
Pins 16 /17
PORT F
No Bias
Pin Complex
Pins 43 /44
PORT G
No Bias
Pin Complex
Pins 45 /46
PORT H
No Bias
Stream &
Channel
Select
SPDIF IN
to PCM
Pin Complex
Pins 21 /22
PORT B
Mic Bias
InMUX1
InMUX2
Pin Complex
Pins 23 /24
PORT C
Mic Bias
Pin Complex
Pins 14 /15
PORT E
Mic Bias
Pin Complex
Pins 18/19/20
CD (Port I)
volmute InMUX 0
ADC0
Stream &
Channel
Select
vol
Gain
mute
+0 to +22.5 dB
In 1.5 dB steps
Port B
InMUX0
Port D
Port F
Port A
MUX
Pin 47
SPDIF OUT1
1 bit
ADC1
1 bit
Port B
Port C
Port D
Port A
Port E
MUX
Port G
Port H
Mixer
Port F
CD
DMIC0
DMIC1
vol
Gain
mute
+0 to +22.5 dB
In 1.5 dB steps
Port B
Port C
Port D
Port A
Port E
MUX
Port G
Port H
Mixer
Port F
CD
DMIC0
DMIC1
InMUX3
Port E
InMUX1
Port G
Port H
Port A
MUX
Port C
InMUX2
Port G
Port H
Port B
MUX
DAC1
InMUX3
DAC2
DAC0
MUX
-34.5 to +12 dB
In 1.5 dB steps
Boost
+0/+10/+20/+30 dB
Port D
HP
Boost
+0/+10/+20/+30 dB
Port A
HP
Boost
+0/+10/+20/+30 dB
Port B
HP
Boost
+0/+10/+20/+30 dB
Port C
LO
Boost
+0/+10/+20/+30 dB
Port E
LO
Boost
+0/+10/+20/+30 dB
Port F
LO
Boost
+0/+10/+20/+30 dB
Port G
LO
Boost
+0/+10/+20/+30 dB
Port H
LO
CD
-6,-12,-18, -24 dB
MixerOutVol
Vol
-46.5 to 0 dB
In 1.5 dB steps
Mixer
mute
Digital
Mute
Digital
Mute
Digital
Mute
(Vendor Specific)
To all ports
enabled as
output
MUX
Analog BeepDigital PC Beep
DAC1
MixerOutVol
DAC0
DAC2
MUX
MUX
Analog BeepDigital PC Beep
DAC1
MixerOutVol
DAC0
DAC2
MUX
MUX
Analog BeepDigital PC Beep
DAC1
MixerOutVol
DAC0
DAC2
MUX
MUX
Analog BeepDigital PC Beep
DAC1
MixerOutVol
DAC0
DAC2
MUX
MUX
Analog BeepDigital PC Beep
DAC1
MixerOutVol
DAC0
DAC2
MUX
MUX
Analog BeepDigital PC Beep
DAC1
MixerOutVol
DAC0
DAC2
MUX
MUX
Analog BeepDigital PC Beep
DAC1
MixerOutVol
DAC0
DAC2
MUX
MUX
Analog BeepDigital PC Beep
DAC1
MixerOutVol
DAC0
DAC2
MUX
Six channel hd audio codec, Premium WLP 3/4 Compliant
4. FUNCTIONAL BLOCK DIAGRAMS
TSI™ CONFIDENTIAL
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Figure 11. Functional Block Diagram
92HD73C
Page 39
92HD73C
HDA
Link
SPDIF
OUT1
NID = 26h
NID = 23h
CD
NID = 12h
VOLUME KNOB
NID = 1Fh
Dig1Pin
ADC0 MUX
ADC1 MUX
DAC0
ADC0
NID = 1Ah
NID = 28h
DMIC0
NID = 13h
Port B
Port A
NID = 0Ah
DAC0
NID = 15h
VOLUME
MUTE
NID = 24h
HP
BIAS
Mixer
NID = 29h
NID = 20h
ADC0
MUX
VOLUME
Mute
Port A
DMIC0
Mixer
DMIC1
NID = 21h
VOL
DMIC1
NID = 14h
VOL
ADC1
NID = 1Bh
DAC1
MIXER
NID = 0Bh
Port C
BIAS
NID = 0Ch
Port D
NID = 0Dh
Port E
BIAS
NID = 0Eh
Port F
NID = 0Fh
DAC1
NID = 16h
VOLUME
MUTE
10/20/30
10/20/30
0 to 22.5dB
1.5dB step
-95.25 to 0dB
0.75dB step
-95.25 to 0dB
0.75dB step
SPDIF
OUT0
NID = 25h
NID = 22h
Dig0Pin
ADC1 MUX
ADC0 MUX
PC_BEEP
NID = 1Ch
Digital
Dig2Pin
ADC1 MUX
ADC0 MUX
DAC2
NID = 17h
VOLUME
MUTE
VSW0
NID = 18h
-95.25 to 0dB
0.75dB step
VSW1
NID = 19h
BIAS
HP
HP
Port G
NID = 10h
Port H
NID = 11h
SPDIF
IN
NID = 27h
NID = 1Eh
MixerOutVol
NID = 2Ah
INPORT2
MUX
Port C
Port G
Port H
Port B
CD
Mute Volume
Mute Volume
Mute Volume
Mute Volume
NID = 1Dh
-34.5 to +12dB
in 1.5dB steps
Mute Volume
DAC0
DAC1
DAC2
(Port I)
DAC2
DAC0
DAC1
MIXER
DAC2
DAC0
DAC1
DAC2
DAC0
DAC1
DAC2
DAC0
DAC1
DAC2
DAC0
DAC1
DAC2
DAC0
DAC1
DAC2
DAC0
DAC1
MixerOutVol
DAC2
IN VOL
10/20/30
IN VOL
10/20/30
IN VOL
10/20/30
IN VOL
10/20/30
IN VOL
10/20/30
IN VOL
10/20/30
IN VOL
10/20/30
IN VOL
10/20/30
LO
LO
LO
LO
LO
Port B
Port C
Port D
Port E
Port F
Port G
Port H
CD
Volume
-46.5 to 0dB
in 1.5dB steps
ADC1
MUX
VOLUME
Mute
Port A
DMIC0
Mixer
DMIC1
0 to 22.5dB
1.5dB step
Port B
Port C
Port D
Port E
Port F
Port G
Port H
CD
INPORT1
MUX
Port E
Port G
Port H
Port A
INPORT0
MUX
Port B
Port D
Port F
Port A
INPORT3
MUX
DAC 1
DAC 2
DAC 0
NID = 2Bh
Mixer
Port H
Port G
Port F
Port E
Port D
Port C
Port B
Port A
MUTEMUTEMU TE
MixerOutVol
Mute
MixerOutVol
MixerOutVol
MixerOutVol
MixerOutVol
MixerOutVol
PC_BEEP (Pin 12)Mute Volume
-6,-12,- 18, -24 dB
VSV
To all output enabled ports
Six channel hd audio codec, Premium WLP 3/4 Compliant
5. WIDGET INFORMATION AND SUPPORTED COMMAND VERBS
TSI™ CONFIDENTIAL
©2014 TEMPO SEMICONDCUTOR, INC.
Figure 12. Widget Diagram
67 V 1.4 09/14
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Six channel hd audio codec, Premium WLP 3/4 Compliant
5.1. Widget List
ID Widget Name Description
00h Root Root Node
01h AFG Audio Function Group
0Ah Port A Port A Pin Widget (Configurable as HP, Line Out, Line In, Mic)
0Bh Port B Port B Pin Widget (Configurable as HP, Line Out, Line In, Mic)
0Ch Port C Port C Pin Widget (Configurable as Line In, Mic, Line Out)
0Dh Port D Port D Pin Widget (Configurable as HP, Line Out, Line In, Mic)
0Eh Port E Port E Pin Widget (Configurable as Line In, Mic, Line Out)
0Fh Port F Port F Pin Widget (Configurable as Line In, Mic, Line Out)
10h Port G Port G Pin Widget (Configurable as Line In, Mic, Line Out)
11h Port H Port H Pin Widget (Configurable as Line In, Mic, Line Out)
12h CD (Port I) CD Pin Widget (Configurable as Line In)
13h DigMic0 Digital Microphone 0 Pin Widget
14h DigMic1 Digital Microphone 1 Pin Widget
15h DAC0 Stereo Output Converter to DAC
16h DAC1 Stereo Output Converter to DAC
17h DAC2 Stereo Output Converter to DAC
18h Rsvd Reserved
19h rsvd Reserved
1Ah ADC0 Stereo Input Converter to ADC
1Bh
ADC1 Stereo Input Converter to ADC
1Ch PCBeep Digital PC Beep
1Dh Mixer Mixer (Input Ports, DACs, Analog PC_Beep)
1Eh MixerOutVol Mixer Out Volume
1Fh VolumeKnob External Volume Control
20h ADC0Mux ADC0 Mux with volume and mute
21h ADC1Mux ADC1 Mux with volume and mute
22h Dig0Pin Digital Output Pin (pin48)
23h Dig1Pin Secondary Digital Output Pin (pin 40)
24h Dig2Pin EAPD and Digital Input Pin (Pin 47)
25h SPDIFOut0 Stereo Output for SPDIF_Out
26h SPDIFOut1 Second Stereo Output for SPDIF_Out
27h
28h
29h
2Ah
SPDIFIn Stereo converter widget for SPDIF_In
InPort0Mux Input port pre-select for mixer
InPort1Mux input port pre-select for mixer
InPort2Mux input port pre-select for mixer
TSI™ CONFIDENTIAL
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Table 10. High Definition Audio Widget
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Six channel hd audio codec, Premium WLP 3/4 Compliant
ID Widget Name Description
2Bh
InPort3Mux input port pre-select for mixer
Table 10. High Definition Audio Widget
5.2. Pin Configuration Default Register Settings
The configuration default registers are 32-bit registers required for each pin widget. These registers are normally used
by the CODEC driver to determine the configuration of jacks and devices attached to the CODEC. When the CODEC is
powered on, these registers are loaded with the default values provided by TSI for typical system usage, and are
loaded in a way that is compatible with the Microsoft Universal Audio Architecture (UAA) driver. The values can be
overridden by TSI customers according to their system configuration. Table 18 shows the Pin Widget Configuration
Default settings.
Will be provided in the next datasheet release.
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Six channel hd audio codec, Premium WLP 3/4 Compliant
6. WIDGET INFORMATION
Bits [39:32] Bits [31:28] BITS [27:20] BITS[19:16] BITS [15:0]
Reserved CODEC Address NID Verb ID (4-bit) Payload Data (16-bit)
Table 11. Command Format for Verb with 4-bit Identifier
Bits [39:32] Bits [31:28] BITS [27:20] BITS[19:8] BITS [7:0]
Reserved CODEC Address NID Verb ID (12-bit) Payload Data (8-bit)
Table 12. Command Format for Verb with 12-bit Identifier
There are two types of responses: Solicited and Unsolicited. Solicited responses are provided as a
direct response to an issued command and will be provided in the frame immediately following the
command. Unsolicited responses are provided by the CODEC independent of any command. Unsolicited responses are the result of CODEC events such as a jack insertion detection. The formats for
Solicited Responses and Unsolicited Responses are shown in the tables below. The “Tag” field in
bits [31:28] of the Unsolicited Response identify the event.
Bit [35] Bit [34] BITS [33:32] BITS[31:0]
Valid (Valid = 1) UnSol = 0 Reserved Response
Bit [35] Bit [34] BITS [33:32] BITS[31:28] BITS [27:0]
Valid (Valid = 1) UnSol = 1 Reserved Tag Response
6.1. Root Node (NID = 00)
)
6.1.1. Root VendorID
Get
6.1.1.1. Root VendorID
Table 13. Solicited Response Format
Table 14. Unsolicited Response Format
Verb ID Payload Response
F00 00 See bitfield table.
Bit Bitfield Name RW Reset Description
[31.:16] Vendor R 111D Vendor ID.
[15.:8] DeviceFix R 76 Device ID 7675h
[7.:0] DeviceProg R 75 Device ID 7675h
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Six channel hd audio codec, Premium WLP 3/4 Compliant
6.1.2. Root RevID
Verb ID Payload Response
Get
F00 02 See bitfield table.
6.1.2.1. Root RevID
Bit Bitfield Name RW Reset Description
[31.:24] Rsvd R 00 Reserved.
[23.:20] Major R 1 Compliant HDAudio spec major revi-
sion.
[19.:16] Minor R 0 Compliant HDAudio spec minor revision
[15.:12] RevisionFix R 0 Vendors rev number for this device.
[11.:8] RevisionProg R 1 Vendors rev number for this device.
[7.:4] SteppingFix R 0 Vendor RevID.
[3.:0] SteppingProg R 1 Vendor RevID.
6.1.2.2. Root NodeInfo
Bit Bitfield Name RW Reset Description
[31.:24] Rsvd2 R 00 Reserved.
[23.:16] StartNID R 01 Starting node number (NID) of first func-
[15.:8] Rsvd1 R 00 Reserved.
[7.:0] TotalNodes R 01 Total number of nodes
6.2. AFG Node (NID = 01
)
6.2.1. AFG Reset
Get
tion group
Verb ID Payload Response
See bitfield table.
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Six channel hd audio codec, Premium WLP 3/4 Compliant
6.2.1.1. AFG Reset
Bit Bitfield Name RW Reset Description
[31.:8] Rsvd1 R 000000 Reserved.
[7.:0] Execute W 00 Function Reset.
6.2.2. AFG NodeInfo
Verb ID Payload Response
Get
6.2.2.1. AFG NodeInfo
Bit Bitfield Name RW Reset Description
[31.:24] Rsvd2 R 00 Reserved.
[23.:16] StartNID R 0A Starting node number for function group
[15.:8] Rsvd1 R 00 Reserved.
[7.:0] TotalNodes R 22 Total number of nodes.
6.2.3. AFG FGType
Get
F00 04 See bitfield table.
subordinate nodes.
Verb ID Payload Response
F00 05 See bitfield table.
6.2.3.1. AFG FGType
Bit Bitfield Name RW Reset Description
[31.:9] Rsvd R 000000 Reserved.
[8] UnSol R 1 Unsolicited response supported:
[7.:0] NodeType R 1 Function group type: 00h = Reserved;
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©2014 TEMPO SEMICONDCUTOR, INC.
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1 = yes 0 = no.
01h = Audio Function Group; 02h = Vendor Defined Modem Function Group;
03h-7Fh = Reserved; 80h-FFh = Vendor
Defined Function Group
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Six channel hd audio codec, Premium WLP 3/4 Compliant
6.2.4. AFG AFGCap
Verb ID Payload Response
Get
F00 08 See bitfield table.
6.2.4.1. AFG AFGCap
Bit Bitfield Name RW Reset Description
[31.:17] Rsvd3 R 00 Reserved.
[16] BeepGen R 1 Beep generator present: 1 = yes 0 = no.
[15.:12] Rsvd2 R 0 Reserved.
[11.:8] InputDelay R D Typical latency in frames. Number of
samples between when the sample is
received as an analog signal at the pin
and when the digital representation is
transmitted on the HD Audio link.
[7.:4] Rsvd1 R 0 Reserved.
[3.:0] OutputDelay R D Typical latency in frames. Number of
samples between when the signal is received from the HD Audio link and when
it appears as an analog signal at the pin.
6.2.5. AFG PCMCap
Get
6.2.5.1. AFG PCMCap
Bit Bitfield Name RW Reset Description
[31.:21] Rsvd2 R 000 Reserved.
[20] B32 R 0 32 bit audio format support:
[19] B24 R 1 24 bit audio format support:
[18] B20 R 1 20 bit audio format support:
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Verb ID Payload Response
F00 0A See bitfield table.
1 = yes 0 = no.
1 = yes 0 = no.
1 = yes 0 = no.
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6.2.5.1. AFG PCMCap
Bit Bitfield Name RW Reset Description
[17] B16 R 1 16 bit audio format support:
[16] B8 R 0 8 bit audio format support:
[15.:12] Rsvd1 R 0 Reserved.
[11] R12 R 0 384kHz rate support: 1 = yes 0 = no.
[10] R11 R 1 192kHz rate support: 1 = yes 0 = no.
[9] R10 R 1 176.4kHz rate support: 1 = yes 0 = no.
[8] R9 R 1 96kHz rate support: 1 = yes 0 = no.
[7] R8 R 1 88.2kHz rate support: 1 = yes 0 = no.
[6] R7 R 1 48kHz rate support: 1 = yes 0 = no.
1 = yes 0 = no.
1 = yes 0 = no.
[5] R6 R 1 44.1kHz rate support: 1 = yes 0 = no.
[4] R5 R 0 32kHz rate support: 1 = yes 0 = no.
[3] R4 R 0 22.05kHz rate support: 1 = yes 0 = no.
[2] R3 R 0 16kHz rate support: 1 = yes 0 = no.
[1] R2 R 0 11.025kHz rate support: 1 = yes 0 = no.
[0] R1 R 0 8kHz rate support: 1 = yes 0 = no.
6.2.6. AFG StreamCap
Get
6.2.6.1. AFG StreamCap
Bit Bitfield Name RW Reset Description
[31.:3] Rsvd R 00000000 Reserved.
Verb ID Payload Response
F00 0B See bitfield table.
[2] AC3 R 0 AC-3 formatted data support:
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1 = yes 0 = no.
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6.2.6.1. AFG StreamCap
Bit Bitfield Name RW Reset Description
[1] Float32 R 0 Float32 formatted data support:
[0] PCM R 1 PCM-formatted data support:
6.2.7. AFG InAmpCap
Verb ID Payload Response
1 = yes 0 = no.
1 = yes 0 = no.
Get
6.2.7.1. AFG InAmpCap
Bit Bitfield Name RW Reset Description
[31] Mute R 0 Mute support: 1 = yes 0 = no.
[30.:23] Rsvd3 R 00 Reserved.
[22.:16] StepSize R 27 Size of each step in the gain range: 0 to
[15] Rsvd2 R 0 Reserved.
[14.:8] NumSteps R 03 Number of gains steps (number of pos-
[7] Rsvd1 R 0 Reserved.
[6.:0] Offset R 00 Indicates which step is 0dB
6.2.8. AFG PwrStateCap
F00 0D See bitfield table.
127 = .25dB to 32dB in .25dB steps.
sible settings - 1).
Get
6.2.8.1. AFG PwrStateCap
Bit Bitfield Name RW Reset Description
[31.:4] Rsvd R 0000000 Reserved.
[3] D3Sup R 1 D3 power state support: 1 = yes 0 = no.
[2] D2Sup R 1 D2 power state support: 1 = yes 0 = no.
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Verb ID Payload Response
F00 0F See bitfield table.
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6.2.8.1. AFG PwrStateCap
Bit Bitfield Name RW Reset Description
[1] D1Sup R 1 D1 power state support: 1 = yes 0 = no.
[0] D0Sup R 1 D0 power state support: 1 = yes 0 = no.
6.2.9. AFG GPIOCnt
Verb ID Payload Response
Get
F00 11 See bitfield table.
6.2.9.1. AFG GPIOCnt
Bit Bitfield Name RW Reset Description
[31] GPIWake R 1 Wake capability. Assuming the Wake
Enable Mask controls are enabled
GPIOs configured as inputs can cause a
wake (generate a Status Change event
on the link) when there is a change in
level on the pin.
[30] GPIUnsol R 1 GPIO unsolicited response support: 1 =
yes 0 = no.
[29.:24] Rsvd R 00 Reserved.
[23.:16] NumGPIs R 00 Number of GPI pins supported by func-
tion group.
[15.:8] NumGPOs R 00 Number of GPO pins supported by func-
tion group.
[7.:0] NumGPIOs R 08 Number of GPIO pins supported by
6.2.10. AFG OutAmpCap
Get
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function group.
Verb ID Payload Response
F00 12 See bitfield table.
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6.2.10.1. AFG OutAmpCap
Bit Bitfield Name RW Reset Description
[31] Mute R 1 Mute support: 1 = yes 0 = no.
[30.:23] Rsvd3 R 00 Reserved.
[22.:16] StepSize R 02 Size of each step in the gain range: 0 to
[15] Rsvd2 R 0 Reserved.
[14.:8] NumSteps R 7F Number of gains steps (number of pos-
[7] Rsvd1 R 0 Reserved.
[6.:0] Offset R 7F Indicates which step is 0dB
127 = .25dB to 32dB in .25dB steps.
sible settings - 1).
6.2.11. AFG PwrState
Get
6.2.11.1. AFG PwrState
Bit Bitfield Name RW Reset Description
[31.:6] Rsvd2 R 0000000 Reserved.
[5.:4] Act R 3 Actual power state of this widget.
[3.:2] Rsvd1 R 0 Reserved.
[1.:0] Set RW 3 Current power state setting for this wid-
6.2.12. AFG UnsolResp
Verb ID Payload Response
F05 00 See bitfield table.
get.
Get
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Verb ID Payload Response
F08 00 See bitfield table.
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6.2.12.1. AFG UnsolResp
Bit Bitfield Name RW Reset Description
[31.:8] Rsvd2 R 000000 Reserved.
[7] En RW 0 Unsolicited response enable:
[6] Rsvd1 R 0 Reserved.
[5.:0] Tag RW 00 Software programmable field returned
6.2.13. AFG GPIO
Verb ID Payload Response
1 = enabled 0 = disabled.
in top six bits (31:26) of every Unsolicited Response generated by this node.
Get
F15 00 See bitfield table.
6.2.13.1. AFG GPIO
Bit Bitfield Name RW Reset Description
[31.:8] Rsvd R 000000 Reserved.
[7] Data7 RW 0 Data for GPIO7. If this GPIO bit is con-
figured as Sticky (edge-sensitive) input
it can be cleared by writing "0". For details of read back value refer to HD Audio spec. section 7.3.3.22
[6] Data6 RW 0 Data for GPIO6. If this GPIO bit is con-
figured as Sticky (edge-sensitive) input
it can be cleared by writing "0". For details of read back value refer to HD Audio spec. section 7.3.3.22
[5] Data5 RW 0 Data for GPIO5. If this GPIO bit is con-
figured as Sticky (edge-sensitive) input
it can be cleared by writing "0". For details of read back value refer to HD Audio spec. section 7.3.3.22
[4] Data4 RW 0 Data for GPIO4. If this GPIO bit is con-
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figured as Sticky (edge-sensitive) input
it can be cleared by writing "0". For details of read back value refer to HD Audio spec. section 7.3.3.22
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6.2.13.1. AFG GPIO
Bit Bitfield Name RW Reset Description
[3] Data3 RW 0 Data for GPIO3. If this GPIO bit is con-
[2] Data2 RW 0 Data for GPIO2. If this GPIO bit is con-
[1] Data1 RW 0 Data for GPIO1. If this GPIO bit is con-
figured as Sticky (edge-sensitive) input
it can be cleared by writing "0". For details of read back value refer to HD Audio spec. section 7.3.3.22
figured as Sticky (edge-sensitive) input
it can be cleared by writing "0". For details of read back value refer to HD Audio spec. section 7.3.3.22
figured as Sticky (edge-sensitive) input
it can be cleared by writing "0". For details of read back value refer to HD Audio spec. section 7.3.3.22
[0] Data0 RW 0 Data for GPIO0. If this GPIO bit is con-
6.2.14. AFG GPIOEn
Get
6.2.14.1. AFG GPIOEn
Bit Bitfield Name RW Reset Description
[31.:8] Rsvd R 000000 Reserved.
[7] Mask7 RW 0 Enable for GPIO7: 0 = pin is disabled
figured as Sticky (edge-sensitive) input
it can be cleared by writing "0". For details of read back value refer to HD Audio spec. section 7.3.3.22
Verb ID Payload Response
F16 00 See bitfield table.
(Hi-Z state); 1 = pin is enabled; behavior
determined by GPIO Direction control
[6] Mask6 RW 0 Enable for GPIO6: 0 = pin is disabled
[5] Mask5 RW 0 Enable for GPIO5: 0 = pin is disabled
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(Hi-Z state); 1 = pin is enabled; behavior
determined by GPIO Direction control
(Hi-Z state); 1 = pin is enabled; behavior
determined by GPIO Direction control
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6.2.14.1. AFG GPIOEn
Bit Bitfield Name RW Reset Description
[4] Mask4 RW 0 Enable for GPIO4: 0 = pin is disabled
[3] Mask3 RW 0 Enable for GPIO3: 0 = pin is disabled
[2] Mask2 RW 0 Enable for GPIO2: 0 = pin is disabled
[1] Mask1 RW 0 Enable for GPIO1: 0 = pin is disabled
[0] Mask0 RW 0 Enable for GPIO0: 0 = pin is disabled
(Hi-Z state); 1 = pin is enabled; behavior
determined by GPIO Direction control
(Hi-Z state); 1 = pin is enabled; behavior
determined by GPIO Direction control
(Hi-Z state); 1 = pin is enabled; behavior
determined by GPIO Direction control
(Hi-Z state); 1 = pin is enabled; behavior
determined by GPIO Direction control
(Hi-Z state); 1 = pin is enabled; behavior
determined by GPIO Direction control
6.2.15. AFG GPIODir
Get
6.2.15.1. AFG GPIODir
Bit Bitfield Name RW Reset Description
[31.:8] Rsvd R 000000 Reserved.
[7] Control7 RW 0 Direction control for GPIO7: 0 = GPIO is
[6] Control6 RW 0 Direction control for GPIO6: 0 = GPIO is
[5] Control5 RW 0 Direction control for GPIO5: 0 = GPIO is
[4] Control4 RW 0 Direction control for GPIO4: 0 = GPIO is
Verb ID Payload Response
F17 00 See bitfield table.
configured as input; 1 = GPIO is configured as output
configured as input; 1 = GPIO is configured as output
configured as input; 1 = GPIO is configured as output
configured as input; 1 = GPIO is configured as output
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6.2.15.1. AFG GPIODir
Bit Bitfield Name RW Reset Description
[3] Control3 RW 0 Direction control for GPIO3: 0 = GPIO is
[2] Control2 RW 0 Direction control for GPIO2: 0 = GPIO is
[1] Control1 RW 0 Direction control for GPIO1: 0 = GPIO is
[0] Control0 RW 0 Direction control for GPIO0: 0 = GPIO is
configured as input; 1 = GPIO is configured as output
configured as input; 1 = GPIO is configured as output
configured as input; 1 = GPIO is configured as output
configured as input; 1 = GPIO is configured as output
6.2.16. AFG GPIOWakeEn
Get
6.2.16.1. AFG GPIOWakeEn
Bit Bitfield Name RW Reset Description
[31.:8] Rsvd R 000000 Reserved.
[7] W7 RW 0 Wake enable for GPIO7: 0 = wake-up
[6] W6 RW 0 Wake enable for GPIO6: 0 = wake-up
[5] W5 RW 0 Wake enable for GPIO5: 0 = wake-up
Verb ID Payload Response
F18 00 See bitfield table.
event is disabled; 1 = When HD Audio
link is powered down (RST# is asserted)
a wake-up event will trigger a Status
Change Request event on the link.
event is disabled; 1 = When HD Audio
link is powered down (RST# is asserted)
a wake-up event will trigger a Status
Change Request event on the link.
event is disabled; 1 = When HD Audio
link is powered down (RST# is asserted)
a wake-up event will trigger a Status
Change Request event on the link.
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6.2.16.1. AFG GPIOWakeEn
Bit Bitfield Name RW Reset Description
[4] W4 RW 0 Wake enable for GPIO4: 0 = wake-up
[3] W3 RW 0 Wake enable for GPIO3: 0 = wake-up
[2] W2 RW 0 Wake enable for GPIO2: 0 = wake-up
event is disabled; 1 = When HD Audio
link is powered down (RST# is asserted)
a wake-up event will trigger a Status
Change Request event on the link.
event is disabled; 1 = When HD Audio
link is powered down (RST# is asserted)
a wake-up event will trigger a Status
Change Request event on the link.
event is disabled; 1 = When HD Audio
link is powered down (RST# is asserted)
a wake-up event will trigger a Status
Change Request event on the link.
[1] W1 RW 0 Wake enable for GPIO1: 0 = wake-up
[0] W0 RW 0 Wake enable for GPIO0: 0 = wake-up
6.2.17. AFG GPIOUnsol
Get
event is disabled; 1 = When HD Audio
link is powered down (RST# is asserted)
a wake-up event will trigger a Status
Change Request event on the link.
event is disabled; 1 = When HD Audio
link is powered down (RST# is asserted)
a wake-up event will trigger a Status
Change Request event on the link.
Verb ID Payload Response
F19 00 See bitfield table.
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6.2.17.1. AFG GPIOUnsol
Bit Bitfield Name RW Reset Description
[31.:8] Rsvd R 000000 Reserved.
[7] EnMask7 RW 0 Unsolicited enable mask for GPIO7. If
[6] EnMask6 RW 0 Unsolicited enable mask for GPIO6. If
set and the Unsolicited Response control for this widget has been enabled an
unsolicited response will be sent when
GPIO2 is configured as input and
changes state.
set and the Unsolicited Response control for this widget has been enabled an
unsolicited response will be sent when
GPIO2 is configured as input and
changes state.
[5] EnMask5 RW 0 Unsolicited enable mask for GPIO5. If
set and the Unsolicited Response control for this widget has been enabled an
unsolicited response will be sent when
GPIO2 is configured as input and
changes state.
[4] EnMask4 RW 0 Unsolicited enable mask for GPIO4. If
set and the Unsolicited Response control for this widget has been enabled an
unsolicited response will be sent when
GPIO2 is configured as input and
changes state.
[3] EnMask3 RW 0 Unsolicited enable mask for GPIO3. If
set and the Unsolicited Response control for this widget has been enabled an
unsolicited response will be sent when
GPIO2 is configured as input and
changes state.
[2] EnMask2 RW 0 Unsolicited enable mask for GPIO2. If
set and the Unsolicited Response control for this widget has been enabled an
unsolicited response will be sent when
GPIO2 is configured as input and
changes state.
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6.2.17.1. AFG GPIOUnsol
Bit Bitfield Name RW Reset Description
[1] EnMask1 RW 0 Unsolicited enable mask for GPIO1. If
[0] EnMask0 RW 0 Unsolicited enable mask for GPIO0. If
6.2.18. AFG GPIOSticky
set and the Unsolicited Response control for this widget has been enabled an
unsolicited response will be sent when
GPIO1 is configured as input and
changes state.
set and the Unsolicited Response control for this widget has been enabled an
unsolicited response will be sent when
GPIO0 is configured as input and
changes state.
Verb ID Payload Response
Get
F1A 00 See bitfield table.
6.2.18.1. AFG GPIOSticky
Bit Bitfield Name RW Reset Description
[31.:8] Rsvd R 000000 Reserved.
[7] Mask7 RW 0 GPIO7 input type (when configured as
input): 0 = Non-Sticky (level-sensitive);
1 = Sticky (edge-sensitive).
[6] Mask6 RW 0 GPIO6 input type (when configured as
input): 0 = Non-Sticky (level-sensitive);
1 = Sticky (edge-sensitive).
[5] Mask5 RW 0 GPIO5 input type (when configured as
input): 0 = Non-Sticky (level-sensitive);
1 = Sticky (edge-sensitive).
[4] Mask4 RW 0 GPIO4 input type (when configured as
input): 0 = Non-Sticky (level-sensitive);
1 = Sticky (edge-sensitive).
[3] Mask3 RW 0 GPIO3 input type (when configured as
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input): 0 = Non-Sticky (level-sensitive);
1 = Sticky (edge-sensitive).
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6.2.18.1. AFG GPIOSticky
Bit Bitfield Name RW Reset Description
[2] Mask2 RW 0 GPIO2 input type (when configured as
[1] Mask1 RW 0 GPIO1 input type (when configured as
[0] Mask0 RW 0 GPIO0 input type (when configured as
6.2.19. AFG SubID
Verb ID Payload Response
input): 0 = Non-Sticky (level-sensitive);
1 = Sticky (edge-sensitive).
input): 0 = Non-Sticky (level-sensitive);
1 = Sticky (edge-sensitive).
input): 0 = Non-Sticky (level-sensitive);
1 = Sticky (edge-sensitive).
Get
6.2.19.1. AFG SubID
Bit Bitfield Name RW Reset Description
[31.:24] Subsys3 RW 00 Subsystem ID (byte 3)
[23.:16] Subsys2 RW 00 Subsystem ID (byte 2)
[15.:8] Subsys1 RW 01 Subsystem ID (byte 1)
[7.:0] Assembly RW 00 Assembly ID
6.2.20. AFG GPIOPlrty
Get
F20 00 See bitfield table.
(Not applicable to codec vendors).
Verb ID Payload Response
F70 00 See bitfield table.
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6.2.20.1. AFG GPIOPlrty
Bit Bitfield Name RW Reset Description
[31.:8] Rsvd R 000000 Reserved.
[7] GP7 RW 1 GPIO7 Polarity: If configured as output
[6] GP6 RW 1 GPIO6 Polarity: If configured as output
[5] GP5 RW 1 GPIO5 Polarity: If configured as output
or non-sticky input: 0 = inverting; 1 =
non-inverting. If configured as sticky input: 0 = falling edges will be detected; 1
= rising edges will be detected
or non-sticky input: 0 = inverting; 1 =
non-inverting. If configured as sticky input: 0 = falling edges will be detected; 1
= rising edges will be detected
or non-sticky input: 0 = inverting; 1 =
non-inverting. If configured as sticky input: 0 = falling edges will be detected; 1
= rising edges will be detected
[4] GP4 RW 1 GPIO4 Polarity: If configured as output
or non-sticky input: 0 = inverting; 1 =
non-inverting. If configured as sticky input: 0 = falling edges will be detected; 1
= rising edges will be detected
[3] GP3 RW 1 GPIO3 Polarity: If configured as output
or non-sticky input: 0 = inverting; 1 =
non-inverting. If configured as sticky input: 0 = falling edges will be detected; 1
= rising edges will be detected
[2] GP2 RW 1 GPIO2 Polarity: If configured as output
or non-sticky input: 0 = inverting; 1 =
non-inverting. If configured as sticky input: 0 = falling edges will be detected; 1
= rising edges will be detected
[1] GP1 RW 1 GPIO1 Polarity: If configured as output
or non-sticky input: 0 = inverting; 1 =
non-inverting. If configured as sticky input: 0 = falling edges will be detected; 1
= rising edges will be detected
[0] GP0 RW 1 GPIO0 Polarity: If configured as output
or non-sticky input: 0 = inverting; 1 =
non-inverting. If configured as sticky input: 0 = falling edges will be detected; 1
= rising edges will be detected
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6.2.21. AFG GPIODrive
Verb ID Payload Response
Get
F71 00 See bitfield table.
6.2.21.1. AFG GPIODrive
Bit Bitfield Name RW Reset Description
[31.:8] Rsvd R 000000 Reserved.
[7] OD7 RW 0 GPIO7 Drive Mode: 0 = push-pull (drive
0 and 1); 1 = open drain (drive 0 float for
1).
[6] OD6 RW 0 GPIO6 Drive Mode: 0 = push-pull (drive
0 and 1); 1 = open drain (drive 0 float for
1).
[5] OD5 RW 0 GPIO5 Drive Mode: 0 = push-pull (drive
0 and 1); 1 = open drain (drive 0 float for
1).
[4] OD4 RW 0 GPIO4 Drive Mode: 0 = push-pull (drive
0 and 1); 1 = open drain (drive 0 float for
1).
[3] OD3 RW 0 GPIO3 Drive Mode: 0 = push-pull (drive
0 and 1); 1 = open drain (drive 0 float for
1).
[2] OD2 RW 0 GPIO2 Drive Mode: 0 = push-pull (drive
[1] OD1 RW 0 GPIO1 Drive Mode: 0 = push-pull (drive
[0] OD0 RW 0 GPIO0 Drive Mode: 0 = push-pull (drive
6.2.22. AFG DMic
Get
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0 and 1); 1 = open drain (drive 0 float for
1).
0 and 1); 1 = open drain (drive 0 float for
1).
0 and 1); 1 = open-drain (drive 0 float for
1).
Verb ID Payload Response
F78 00 See bitfield table.
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6.2.22.1. AFG DMic
Bit Bitfield Name RW Reset Description
[31.:6] Rsvd R 0000000 Reserved.
[5] Mono1 RW 0
[4] Mono0 RW 0
[3.:2] PhAdj RW 0 Selects what phase of the DMic clock
[1.:0] Rate RW 2 Selects the DMic clock rate:
6.2.23. AFG AnaBeep
DMic1 mono select: 0 = stereo operation,
1 = mono operation (left channel duplicated
to the right channel).
DMic0 mono select: 0 = stereo operation,
1 = mono operation (left channel duplicated
to the right channel).
the data should be latched: 0h = left
data rising edge/right data falling edge;
1h = left data center of high/right data
center of low; 2h = left data falling
edge/right data rising edge; 3h = left
data center of low/right data center of
high
0h = 4.704MHz; 1h = 3.528MHz;
2h = 2.352MHz; 3h = 1.176MHz.
Verb ID Payload Response
Get
FEE 00 See bitfield table.
6.2.23.1. AFG AnaBeep
Bit Bitfield Name RW Reset Description
[31.:3] Rsvd R 0000000 Reserved.
[2:1] Gain RW 3
[0] Enable RW 0
Analog PCBeep Gain
0h=-18dB
1h=-12dB
2h=-6dB
3h=0dB
Analog PCBeep enable
1=Analog PC Beep enabled
0=disabled
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6.3. Port A Node (NID = 0A)
6.3.1. PortA WCap
Verb ID Payload Response
Get
F00 09 See bitfield table.
6.3.1.1. PortA WCap
Bit Bitfield Name RW Reset Description
[31.:24] Rsvd2 R 00 Reserved.
[23.:20] Type R 4 Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
[19.:16] Delay R 0 Number of sample delays through wid-
get.
[15.:12] Rsvd1 R 0 Reserved.
[11] SwapCap R 0 Left/right swap support: 1 = yes 0 = no.
[10] PwrCntrl R 0 Power state support: 1 = yes 0 = no.
[9] Dig R 0 Digital stream support: 1 = yes (digital)
[8] ConnList R 1 Connection list present: 1 = yes 0 = no.
[7] UnSolCap R 1 Unsolicited response support: 1 = yes 0
[6] ProcWidget R 0 Processing state support: 1 = yes 0 =
[5] Stripe R 0 Striping support: 1 = yes 0 = no.
[4] FormatOvrd R 0 Stream format override: 1 = yes 0 = no.
[3] AmpParOvrd R 0 Amplifier capabilities override: 1 = yes
[2] OutAmpPrsnt R 0 Output amp present: 1 = yes 0 = no.
TSI™ CONFIDENTIAL
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89 V 1.4 09/14
0 = no (analog).
= no.
no.
no.
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6.3.1.1. PortA WCap
Bit Bitfield Name RW Reset Description
[1] InAmpPrsnt R 1 Input amp present: 1 = yes 0 = no.
[0] Stereo R 1 Stereo stream support: 1 = yes (stereo)
6.3.2. PortA PinCap
Verb ID Payload Response
0 = no (mono).
Get
F00 0C See bitfield table.
6.3.2.1. PortA PinCap
Bit Bitfield Name RW Reset Description
[31.:17] Rsvd2 R 0000 Reserved.
[16] EapdCap R 0 EAPD support: 1 = yes 0 = no.
[15.:8] VrefCntrl R 00 Vref support: bit 7 = Reserved; bit 6 =
Reserved; bit 5 = 100% support (1 = yes
0 = no); bit 4 = 80% support (1 = yes 0
= no); bit 3 = Reserved; bit 2 = GND support (1 = yes 0 = no); bit 1 = 50% support (1 = yes 0 = no); bit 0 = Hi-Z
support (1 = yes 0 = no)
[7] Rsvd1 R 0 Reserved.
[6] BalancedIO R 0 Balanced I/O support: 1 = yes 0 = no.
[5] InCap R 1 Input support: 1 = yes 0 = no.
[4] OutCap R 1 Output support: 1 = yes 0 = no.
[3] HdphDrvCap R 1 Headphone amp present: 1 = yes 0 =
[2] PresDtctCap R 1 Presence detection support: 1 = yes 0 =
[1] TrigRqd R 0 Trigger required for impedance sense: 1
[0] ImpSenseCap R 0 Impedance sense support: 1 = yes 0 =
TSI™ CONFIDENTIAL
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no.
no.
= yes 0 = no.
no.
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6.3.3. PortA ConLst
Verb ID Payload Response
Get
6.3.3.1. PortA ConLst
Bit Bitfield Name RW Reset Description
[31.:8] Rsvd R 000000 Reserved.
[7] LForm R 0 Connection list format: 1 = long-form
[6.:0] ConL R 03 Number of NID entries in connection list.
6.3.4. PortA ConLstEntry0
Get
F00 0E See bitfield table.
(15-bit) NID entries 0 = short-form
(7-bit) NID entries.
Verb ID Payload Response
F02 00 See bitfield table.
6.3.4.1. PortA ConLstEntry0
Bit Bitfield Name RW Reset Description
[31.:24] ConL3 R 00 Unused list entry.
[23.:16] ConL2 R 1E InputMixer Summing widget (0x1E)
[15] ConL1Range R 1
[14.:8] ConL1 R 19 DAC1 Converter widget (0x19)
[7.:0] ConL0 R 15 DAC0 Converter widget (0x15)
TSI™ CONFIDENTIAL
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1 = ConL0..ConL1 defines a range of selectable inputs.
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6.3.5. PortA ConSelectCtrl
Verb ID Payload Response
Get
6.3.5.1. PortA ConSelectCtrl
Bit Bitfield Name RW Reset Description
[31.:2] Rsvd R 00000000 Reserved.
[1.:0] Index RW 0 Connection select control index.
6.3.6. PortA PinWCntrl
Get
6.3.6.1. PortA PinWCntrl
F01 00 See bitfield table.
Verb ID Payload Response
F07 00 See bitfield table.
Bit Bitfield Name RW Reset Description
[31.:8] Rsvd2 R 000000 Reserved.
[7] HPhnEn RW 0 Headphone amp enable:
1 = enabled 0 = disabled.
[6] OutEn RW 0 Output enable:
1 = enabled 0 = disabled.
[4.:3] Rsvd1 R 0 Reserved.
[2.:0] VRefEn RW 0
Vref selection (See VrefCntrl field of PinCap
parameter for supported selections):
000b= HI-Z, 001b= 50%
010b= GND, 011b= Reserved
100b= 80%, 101b= 100%
110b= Reserved, 111b= Reserved
TSI™ CONFIDENTIAL
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6.3.7. PortA UnsolResp
Verb ID Payload Response
Get
6.3.7.1. PortA UnsolResp
Bit Bitfield Name RW Reset Description
[31.:8] Rsvd2 R 000000 Reserved.
[7] En RW 0 Unsolicited response enable: 1 = en-
[6] Rsvd1 R 0 Reserved.
[5.:0] Tag RW 00 Software programmable field returned
6.3.8. PortA ChSense
F08 00 See bitfield table.
abled 0 = disabled.
in top six bits (31:26) of every Unsolicited Response generated by this node.
Verb ID Payload Response
Get
F09 00 See bitfield table.
6.3.8.1. PortA ChSense
Bit Bitfield Name RW Reset Description
[31] PresDtct R 0 Presence detection indicator:
1 = presence detected;
0 = presence not detected.
[30.:1] Impedence R 3FFFFFFF
[0] Execute RW 1
Impedance Sense Value (Bits 30:1): Measured impedence of the widget. An all ones
value indicates an invalid sense reading
Impedance Sense Value (Bit 0)/Trigger:
Read = Impedance value bit 0
Write 0 = Impedance sense occurs using left
channel
Write 1 = Impedance sense occurs using
right channel
TSI™ CONFIDENTIAL
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6.3.9. PortA InAmpLeft
Verb ID Payload Response
Get
6.3.9.1. PortA InAmpLeft
Bit Bitfield Name RW Reset Description
[31.:2] Rsvd1 R 00000000 Reserved.
[1.:0] Gain RW 0
6.3.10. PortA InAmpRight
Get
B20 00 See bitfield table.
Amp gain step number (see InAmpCap parameter pertaining to this widget).
Verb ID Payload Response
B00 00 See bitfield table.
6.3.10.1. PortA InAmpRight
Bit Bitfield Name RW Reset Description
[31.:2] Rsvd1 R 00000000 Reserved.
[1.:0] Gain RW 0
6.3.11. PortA ConfigDefault
Get
Amp gain step number (see InAmpCap parameter pertaining to this widget).
Verb ID Payload Response
F1C 00 See bitfield table.
TSI™ CONFIDENTIAL
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6.3.11.1. PortA ConfigDefault
Bit Bitfield Name RW Reset Description
[31.:30] PortConnectivity RW 0 Port connectivity: 0h = Port complex is
[29.:24] Location RW 02 Location. Bits [5..4]: 0h = External on
[23.:20] Device RW 2 Default device: 0h = Line out; 1h =
connected to a jack; 1h = No physical
connection for port; 2h = Fixed function
device is attached; 3h = Both jack and
internal device attached (info in all other
fields refers to integrated device any
presence detection refers to jack)
primary chassis; 1h = Internal; 2h = Separate chassis; 3h = Other. Bits [3..0]: 0h
= N/A; 1h = Rear; 2h = Front; 3h = Left;
4h = Right; 5h = Top; 6h = Bottom;
7h-9h = Special; Ah-Fh = Reserved
Speaker; 2h = HP out; 3h = CD; 4h =
SPDIF Out; 5h = Digital other out; 6h =
Modem line side; 7h = Modem handset
side; 8h = Line in; 9h = Aux; Ah = Mic in;
Bh = Telephony; Ch = SPDIF In; Dh =
Digital other in; Eh = Reserved; Fh =
Other
[19.:16] Connection Type RW 1 Connection type: 0h = Unknown; 1h =
1/8" stereo/mono; 2h = 1/4" stereo/mono; 3h = ATAPI internal; 4h = RCA; 5h =
Optical; 6h = Other digital; 7h = Other
analog; 8h = Multichannel analog (DIN);
9h = XLR/Professional; Ah = RJ-11 (modem); Bh = Combination; Ch-Eh = Reserved; Fh = Other
[15.:12] Color RW 4 Color: 0h = Unknown; 1h = Black; 2h =
Grey; 3h = Blue; 4h = Green; 5h = Red;
6h = Orange; 7h = Yellow; 8h = Purple;
9h = Pink; Ah-Dh = Reserved; Eh =
White; Fh = Other
[11.:8] Misc RW 0 Miscellaneous: Bits [3..1] = Reserved;
Bit 0 = Jack detect override
[7.:4] Association RW 3 Default assocation.
[3.:0] Sequence RW 0 Sequence.
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6.4. PortB Node (NID = 0B)
6.4.1. PortB WCap
Verb ID Payload Response
Get
F00 09 See bitfield table.
6.4.1.1. PortB WCap
Bit Bitfield Name RW Reset Description
[31.:24] Rsvd2 R 00 Reserved.
[23.:20] Type R 4 Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
[19.:16] Delay R 0 Number of sample delays through wid-
get.
[15.:12] Rsvd1 R 0 Reserved.
[11] SwapCap R 0 Left/right swap support: 1 = yes 0 = no.
[10] PwrCntrl R 0 Power state support: 1 = yes 0 = no.
[9] Dig R 0 Digital stream support: 1 = yes (digital)
[8] ConnList R 1 Connection list present: 1 = yes 0 = no.
[7] UnSolCap R 1 Unsolicited response support: 1 = yes 0
[6] ProcWidget R 0 Processing state support: 1 = yes 0 =
[5] Stripe R 0 Striping support: 1 = yes 0 = no.
[4] FormatOvrd R 0 Stream format override: 1 = yes 0 = no.
[3] AmpParOvrd R 0 Amplifier capabilities override: 1 = yes
[2] OutAmpPrsnt R 0 Output amp present: 1 = yes 0 = no.
TSI™ CONFIDENTIAL
©2014 TEMPO SEMICONDCUTOR, INC.
96 V 1.4 09/14
0 = no (analog).
= no.
no.
no.
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6.4.1.1. PortB WCap
Bit Bitfield Name RW Reset Description
[1] InAmpPrsnt R 1 Input amp present: 1 = yes 0 = no.
[0] Stereo R 1 Stereo stream support: 1 = yes (stereo)
6.4.2. PortB PinCap
Verb ID Payload Response
0 = no (mono).
Get
F00 0C See bitfield table.
6.4.2.1. PortB PinCap
Bit Bitfield Name RW Reset Description
[31.:17] Rsvd2 R 0000 Reserved.
[16] EapdCap R 0 EAPD support: 1 = yes 0 = no.
[15.:8] VrefCntrl R 17 Vref support: bit 7 = Reserved; bit 6 =
Reserved; bit 5 = 100% support (1 = yes
0 = no); bit 4 = 80% support (1 = yes 0
= no); bit 3 = Reserved; bit 2 = GND support (1 = yes 0 = no); bit 1 = 50% support (1 = yes 0 = no); bit 0 = Hi-Z
support (1 = yes 0 = no)
[7] Rsvd1 R 0 Reserved.
[6] BalancedIO R 0 Balanced I/O support: 1 = yes 0 = no.
[5] InCap R 1 Input support: 1 = yes 0 = no.
[4] OutCap R 1 Output support: 1 = yes 0 = no.
[3] HdphDrvCap R 1 Headphone amp present:
[2] PresDtctCap R 1 Presence detection support:
[1] TrigRqd R 1 Trigger required for impedance sense:
[0] ImpSenseCap R 1 Impedance sense support:
TSI™ CONFIDENTIAL
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1 = yes 0 = no.
1 = yes 0 = no.
1 = yes 0 = no.
1 = yes 0 = no.
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6.4.3. PortB ConLstEntry0
Verb ID Payload Response
Get
6.4.3.1. PortB ConLst
Bit Bitfield Name RW Reset Description
[31.:8] Rsvd R 000000 Reserved.
[7] LForm R 0 Connection list format: 1 = long-form
[6.:0] ConL R 03 Number of NID entries in connection list.
6.4.4. PortB ConLstEntry0
Get
F00 0E See bitfield table.
(15-bit) NID entries 0 = short-form
(7-bit) NID entries.
Verb ID Payload Response
F02 00 See bitfield table.
6.4.4.1. PortB ConLstEntry0
Bit Bitfield Name RW Reset Description
[31.:24] ConL3 R 00 Unused list entry.
[23.:16] ConL2 R 1E MixerOutVol Selector widget (0x1E)
[15] ConL1Range R 1
[14.:8] ConL1 R 17 DAC2 Converter widget (0x17)
[7.:0] ConL0 R 15 DAC0 Converter widget (0x15)
TSI™ CONFIDENTIAL
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1 = ConL0..ConL1 defines a range of selectable inputs.
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6.4.5. PortB ConSelectCtrl
Verb ID Payload Response
Get
6.4.5.1. PortB ConSelectCtrl
Bit Bitfield Name RW Reset Description
[31.:2] Rsvd R 00000000 Reserved.
[1.:0] Index RW 0 Connection select control index.
6.4.6. PortB PinWCntrl
Get
6.4.6.1. PortB PinWCntrl
F01 00 See bitfield table.
Verb ID Payload Response
F07 00 See bitfield table.
Bit Bitfield Name RW Reset Description
[31.:8] Rsvd2 R 0000000 Reserved.
[7] HPhnEn RW 0
[6] OutEn RW 0
Headphone amp enable: 1 = enabled, 0 =
disabled.
Output enable: 1 = enabled, 0 = disabled.
[5] InEn RW 0 Input enable: 1 = enabled 0 = disabled.
[4.:3] Rsvd1 R 0 Reserved.
[2.:0] VRefEn RW 0 Vref selection (See VrefCntrl field of
PinCap parameter for supported selections): 000b= HI-Z; 001b= 50%; 010b=
GND; 011b= Reserved; 100b= 80%;
101b= 100%; 110b= Reserved; 111b=
Reserved
TSI™ CONFIDENTIAL
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6.4.7. PortB UnsolResp
Verb ID Payload Response
Get
6.4.7.1. PortB UnsolResp
Bit Bitfield Name RW Reset Description
[31.:8] Rsvd2 R 000000 Reserved.
[7] En RW 0 Unsolicited response enable:
[6] Rsvd1 R 0 Reserved.
[5.:0] Tag RW 00 Software programmable field returned
6.4.8. PortB ChSense
F08 00 See bitfield table.
1 = enabled 0 = disabled.
in top six bits (31:26) of every Unsolicited Response generated by this node.
Verb ID Payload Response
Get
F09 00 See bitfield table.
6.4.8.1. PortB ChSense
Bit Bitfield Name RW Reset Description
[31] PresDtct R 0 Presence detection indicator: 1 = pres-
ence detected; 0 = presence not detected.
[30.:1] Impedence R 3FFFFFFF
[0] Execute RW 1
Impedance Sense Value (Bits 30:1): Measured impedence of the widget. An all ones
value indicates an invalid sense reading
Impedance Sense Value (Bit 0)/Trigger:
Read = Impedance value bit 0
Write 0 = Impedance sense occurs using left
channel
Write 1 = Impedance sense occurs using
right channel
TSI™ CONFIDENTIAL
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6.4.9. PortB InAmpLeft
Verb ID Payload Response
Get
6.4.9.1. PortB InAmpLeft
Bit Bitfield Name RW Reset Description
[31.:2] Rsvd1 R 000000 Reserved.
[1.:0] Gain RW 0
6.4.10. PortD InAmpRight
Get
B20 00 See bitfield table.
Amp gain step number (see InAmpCap parameter pertaining to this widget).
Verb ID Payload Response
B00 00 See bitfield table.
6.4.10.1. PortD InAmpRight
Bit Bitfield Name RW Reset Description
[31.:2] Rsvd1 R 000000 Reserved.
[1.:0] Gain RW 0
6.4.11. PortB ConfigDefault
Get
Amp gain step number (see InAmpCap parameter pertaining to this widget).
Verb ID Payload Response
F1C 00 See bitfield table.
TSI™ CONFIDENTIAL
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6.4.11.1. PortB ConfigDefault
Bit Bitfield Name RW Reset Description
[31.:30] PortConnectivity RW 0 Port connectivity: 0h = Port complex is
[29.:24] Location RW 02 Location. Bits [5..4]: 0h = External on
[23.:20] Device RW A Default device: 0h = Line out; 1h =
connected to a jack; 1h = No physical
connection for port; 2h = Fixed function
device is attached; 3h = Both jack and
internal device attached (info in all other
fields refers to integrated device any
presence detection refers to jack)
primary chassis; 1h = Internal; 2h = Separate chassis; 3h = Other. Bits [3..0]: 0h
= N/A; 1h = Rear; 2h = Front; 3h = Left;
4h = Right; 5h = Top; 6h = Bottom;
7h-9h = Special; Ah-Fh = Reserved
Speaker; 2h = HP out; 3h = CD; 4h =
SPDIF Out; 5h = Digital other out; 6h =
Modem line side; 7h = Modem handset
side; 8h = Line in; 9h = Aux; Ah = Mic in;
Bh = Telephony; Ch = SPDIF In; Dh =
Digital other in; Eh = Reserved; Fh =
Other
[19.:16] ConnectionType RW 1 Connection type: 0h = Unknown; 1h =
1/8" stereo/mono; 2h = 1/4" stereo/mono; 3h = ATAPI internal; 4h = RCA; 5h =
Optical; 6h = Other digital; 7h = Other
analog; 8h = Multichannel analog (DIN);
9h = XLR/Professional; Ah = RJ-11 (modem); Bh = Combination; Ch-Eh = Reserved; Fh = Other
[15.:12] Color RW 9 Color: 0h = Unknown; 1h = Black; 2h =
Grey; 3h = Blue; 4h = Green; 5h = Red;
6h = Orange; 7h = Yellow; 8h = Purple;
9h = Pink; Ah-Dh = Reserved; Eh =
White; Fh = Other
[11.:8] Misc RW 0 Miscellaneous: Bits [3..1] = Reserved;
Bit 0 = Jack detect override
[7.:4] Association RW 4 Default assocation.
[3.:0] Sequence RW 0 Sequence.
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6.5. Port C Node (NID = 0C)
6.5.1. PortC WCap
Verb ID Payload Response
Get
F00 09 See bitfield table.
6.5.1.1. PortC WCap
Bit Bitfield Name RW Reset Description
[31.:24] Rsvd2 R 00 Reserved.
[23.:20] Type R 4 Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
[19.:16] Delay R 0 Number of sample delays through wid-
get.
[15.:12] Rsvd1 R 0 Reserved.
[11] SwapCap R 0 Left/right swap support: 1 = yes 0 = no.
[10] PwrCntrl R 0 Power state support: 1 = yes 0 = no.
[9] Dig R 0 Digital stream support: 1 = yes (digital)
[8] ConnList R 1 Connection list present: 1 = yes 0 = no.
[7] UnSolCap R 1 Unsolicited response support:
[6] ProcWidget R 0 Processing state support:
[5] Stripe R 0 Striping support: 1 = yes 0 = no.
[4] FormatOvrd R 0 Stream format override: 1 = yes 0 = no.
[3] AmpParOvrd R 0 Amplifier capabilities override:
[2] OutAmpPrsnt R 0 Output amp present: 1 = yes 0 = no.
TSI™ CONFIDENTIAL
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0 = no (analog).
1 = yes 0 = no.
1 = yes 0 = no.
1 = yes no.
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6.5.1.1. PortC WCap
Bit Bitfield Name RW Reset Description
[1] InAmpPrsnt R 1 Input amp present: 1 = yes 0 = no.
[0] Stereo R 1 Stereo stream support: 1 = yes (stereo)
6.5.2. PortC PinCap
Verb ID Payload Response
0 = no (mono).
Get
F00 0C See bitfield table.
6.5.2.1. PortC PinCap
Bit Bitfield Name RW Reset Description
[31.:17] Rsvd2 R 0000 Reserved.
[16] EapdCap R 0 EAPD support: 1 = yes 0 = no.
[15.:8] VrefCntrl R 17 Vref support: bit 7 = Reserved; bit 6 =
Reserved; bit 5 = 100% support (1 = yes
0 = no); bit 4 = 80% support (1 = yes 0
= no); bit 3 = Reserved; bit 2 = GND support (1 = yes 0 = no); bit 1 = 50% support (1 = yes 0 = no); bit 0 = Hi-Z
support (1 = yes 0 = no)
[7] Rsvd1 R 0 Reserved.
[6] BalancedIO R 0 Balanced I/O support: 1 = yes 0 = no.
[5] InCap R 1 Input support: 1 = yes 0 = no.
[4] OutCap R 1 Output support: 1 = yes 0 = no.
[3] HdphDrvCap R 0 Headphone amp present:
[2] PresDtctCap R 1 Presence detection support:
[1] TrigRqd R 1 Trigger required for impedance sense:
[0] ImpSenseCap R 1 Impedance sense support:
TSI™ CONFIDENTIAL
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1 = yes 0 = no.
1 = yes 0 = no.
1 = yes 0 = no.
1 = yes 0 = no.
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6.5.3. PortC ConLst
Verb ID Payload Response
Get
6.5.3.1. PortC ConLst
Bit Bitfield Name RW Reset Description
[31.:8] Rsvd R 000000 Reserved.
[7] LForm R 0 Connection list format: 1 = long-form
[6.:0] ConL R 03 Number of NID entries in connection list.
6.5.4. PortC ConLstEntry0
Get
F00 0E See bitfield table.
(15-bit) NID entries 0 = short-form
(7-bit) NID entries.
Verb ID Payload Response
F02 00 See bitfield table.
6.5.4.1. PortC ConLstEntry0
Bit Bitfield Name RW Reset Description
[31.:24] ConL3 R 00 Unused list entry.
[23.:16] ConL2 R 17 InputMixer Summing widget (0x1E)
[15] ConL1Range R 1
[14.:8] ConL1 R 17 DAC2 Converter widget (0x17)
[7.:0] ConL0 R 15 DAC0 Converter widget (0x15)
TSI™ CONFIDENTIAL
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105 V 1.4 09/14
1 = ConL0..ConL1 defines a range of selectable inputs.
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6.5.5. PortC ConSelectCtrl
Verb ID Payload Response
Get
6.5.5.1. PortC ConSelectCtrl
Bit Bitfield Name RW Reset Description
[31.:2] Rsvd R 00000000 Reserved.
[1.:0] Index RW 0 Connection select control index.
6.5.6. PortC PinWCntrl
Get
6.5.6.1. PortC PinWCntrl
F01 00 See bitfield table.
Verb ID Payload Response
F07 00 See bitfield table.
Bit Bitfield Name RW Reset Description
[31.:6] Rsvd2 R 0000000 Reserved.
[5] InEn RW 0 Input enable: 1 = enabled 0 = disabled.
[4.:3] Rsvd1 R 0 Reserved.
[2.:0] VRefEn RW 0 Vref selection (See VrefCntrl field of
6.5.7. PortC UnsolResp
Get
PinCap parameter for supported selections): 000b= HI-Z; 001b= 50%; 010b=
GND; 011b= Reserved; 100b= 80%;
101b= 100%; 110b= Reserved; 111b=
Reserved
Verb ID Payload Response
F08 00 See bitfield table.
TSI™ CONFIDENTIAL
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6.5.7.1. PortC UnsolResp
Bit Bitfield Name RW Reset Description
[31.:8] Rsvd2 R 000000 Reserved.
[7] En RW 0 Unsolicited response enable: 1 = en-
[6] Rsvd1 R 0 Reserved.
[5.:0] Tag RW 00 Software programmable field returned
6.5.8. PortC ChSense
abled 0 = disabled.
in top six bits (31:26) of every Unsolicited Response generated by this node.
Verb ID Payload Response
Get
F09 00 See bitfield table.
6.5.8.1. PortC ChSense
Bit Bitfield Name RW Reset Description
[31] PresDtct R 0 Presence detection indicator: 1 = pres-
ence detected; 0 = presence not detected.
[30.:1] Impedence R 3FFFFFFF
[0] Execute RW 1
Impedance Sense Value (Bits 30:1): Measured impedence of the widget. An all ones
value indicates an invalid sense reading
Impedance Sense Value (Bit 0)/Trigger:
Read = Impedance value bit 0
Write 0 = Impedance sense occurs using left
channel
Write 1 = Impedance sense occurs using
right channel
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6.5.9. PortC InAmpLeft
Verb ID Payload Response
Get
6.5.9.1. PortC InAmpLeft
Bit Bitfield Name RW Reset Description
[31.:2] Rsvd1 R 00000000 Reserved.
[1.:0] Gain RW 0
6.5.10. PortC InAmpRight
Get
B20 00 See bitfield table.
Amp gain step number (see InAmpCap parameter pertaining to this widget).
Verb ID Payload Response
B00 00 See bitfield table.
6.5.10.1. PortC InAmpRight
Bit Bitfield Name RW Reset Description
[31.:2] Rsvd1 R 00000000 Reserved.
[1.:0] Gain RW 0
6.5.11. PortC ConfigDefault
Get
Amp gain step number (see InAmpCap parameter pertaining to this widget).
Verb ID Payload Response
F1C 00 See bitfield table.
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6.5.11.1. PortC ConfigDefault
Bit Bitfield Name RW Reset Description
[31.:30] PortConnectivity RW 0 Port connectivity: 0h = Port complex is
[29.:24] Location RW 1 Location. Bits [5..4]: 0h = External on
[23.:20] Device RW 8 Default device: 0h = Line out; 1h =
connected to a jack; 1h = No physical
connection for port; 2h = Fixed function
device is attached; 3h = Both jack and
internal device attached (info in all other
fields refers to integrated device any
presence detection refers to jack)
primary chassis; 1h = Internal; 2h = Separate chassis; 3h = Other. Bits [3..0]: 0h
= N/A; 1h = Rear; 2h = Front; 3h = Left;
4h = Right; 5h = Top; 6h = Bottom;
7h-9h = Special; Ah-Fh = Reserved
Speaker; 2h = HP out; 3h = CD; 4h =
SPDIF Out; 5h = Digital other out; 6h =
Modem line side; 7h = Modem handset
side; 8h = Line in; 9h = Aux; Ah = Mic in;
Bh = Telephony; Ch = SPDIF In; Dh =
Digital other in; Eh = Reserved; Fh =
Other
[19.:16] ConnectionType RW 1 Connection type: 0h = Unknown; 1h =
1/8" stereo/mono; 2h = 1/4" stereo/mono; 3h = ATAPI internal; 4h = RCA; 5h =
Optical; 6h = Other digital; 7h = Other
analog; 8h = Multichannel analog (DIN);
9h = XLR/Professional; Ah = RJ-11 (modem); Bh = Combination; Ch-Eh = Reserved; Fh = Other
[15.:12] Color RW 3 Color: 0h = Unknown; 1h = Black; 2h =
Grey; 3h = Blue; 4h = Green; 5h = Red;
6h = Orange; 7h = Yellow; 8h = Purple;
9h = Pink; Ah-Dh = Reserved; Eh =
White; Fh = Other
[11.:8] Misc RW 0 Miscellaneous: Bits [3..1] = Reserved;
Bit 0 = Jack detect override
[7.:4] Association RW 2 Default assocation.
[3.:0] Sequence RW 1 Sequence.
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6.6. Port D Node (NID = 0D)
6.6.1. PortD WCap
Verb ID Payload Response
Get
F00 09 See bitfield table.
6.6.1.1. PortD WCap
Bit Bitfield Name RW Reset Description
[31.:24] Rsvd2 R 00 Reserved.
[23.:20] Type R 4 Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
[19.:16] Delay R 0 Number of sample delays through wid-
get.
[15.:12] Rsvd1 R 0 Reserved.
[11] SwapCap R 0 Left/right swap support: 1 = yes 0 = no.
[10] PwrCntrl R 0 Power state support: 1 = yes 0 = no.
[9] Dig R 0 Digital stream support: 1 = yes (digital)
[8] ConnList R 1 Connection list present: 1 = yes 0 = no.
[7] UnSolCap R 1 Unsolicited response support:
[6] ProcWidget R 0 Processing state support:
[5] Stripe R 0 Striping support: 1 = yes 0 = no.
[4] FormatOvrd R 0 Stream format override: 1 = yes 0 = no.
[3] AmpParOvrd R 1 Amplifier capabilities override:
[2] OutAmpPrsnt R 1 Output amp present: 1 = yes 0 = no.
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0 = no (analog).
1 = yes 0 = no.
1 = yes 0 = no.
1 = yes no.
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6.6.1.1. PortD WCap
Bit Bitfield Name RW Reset Description
[1] InAmpPrsnt R 1 Input amp present: 1 = yes 0 = no.
[0] Stereo R 1 Stereo stream support: 1 = yes (stereo)
6.6.2. PortD PinCap
Verb ID Payload Response
0 = no (mono).
Get
F00 0C See bitfield table.
6.6.2.1. PortD PinCap
Bit Bitfield Name RW Reset Description
[31.:17] Rsvd2 R 0000 Reserved.
[16] EapdCap R 0 EAPD support: 1 = yes 0 = no.
[15.:8] VrefCntrl R 00 Vref support: bit 7 = Reserved; bit 6 =
Reserved; bit 5 = 100% support (1 = yes
0 = no); bit 4 = 80% support (1 = yes 0
= no); bit 3 = Reserved; bit 2 = GND support (1 = yes 0 = no); bit 1 = 50% support (1 = yes 0 = no); bit 0 = Hi-Z
support (1 = yes 0 = no)
[7] Rsvd1 R 0 Reserved.
[6] BalancedIO R 0 Balanced I/O support: 1 = yes 0 = no.
[5] InCap R 1 Input support: 1 = yes 0 = no.
[4] OutCap R 1 Output support: 1 = yes 0 = no.
[3] HdphDrvCap R 1 Headphone amp present:
[2] PresDtctCap R 1 Presence detection support:
[1] TrigRqd R 0 Trigger required for impedance sense:
[0] ImpSenseCap R 0 Impedance sense support:
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1 = yes 0 = no.
1 = yes 0 = no.
1 = yes 0 = no.
1 = yes 0 = no.
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6.6.3. PortD ConLst
Verb ID Payload Response
Get
6.6.3.1. PortD ConLst
Bit Bitfield Name RW Reset Description
[31.:8] Rsvd R 000000 Reserved.
[7] LForm R 0 Connection list format: 1 = long-form
[6.:0] ConL R 03 Number of NID entries in connection list.
6.6.4. PortD ConLstEntry0
Get
F00 0E See bitfield table.
(15-bit) NID entries 0 = short-form
(7-bit) NID entries.
Verb ID Payload Response
F02 00 See bitfield table.
6.6.4.1. PortD ConLstEntry0
Bit Bitfield Name RW Reset Description
[31.:24] ConL3 R 00 Unused list entry.
[23.:16] ConL2 R 1E MixerOutVol Summing widget (0x1E)
[15] ConL1Range R 1
[15.:8] ConL1 R 17 DAC2 Converter widget (0x17)
[7.:0] ConL0 R 15 DAC0 Converter widget (0x15)
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1 = ConL0..ConL1 defines a range of selectable inputs.
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6.6.5. PortD ConSelectCtrl
Verb ID Payload Response
Get
6.6.5.1. PortD ConSelectCtrl
Bit Bitfield Name RW Reset Description
[31.:2] Rsvd R 00000000 Reserved.
[1.:0] Index RW 0 Connection select control index.
6.6.6. PortD PinWCntrl
Get
6.6.6.1. PortD PinWCntrl
F01 00 See bitfield table.
Verb ID Payload Response
F07 00 See bitfield table.
Bit Bitfield Name RW Reset Description
[31.:8] Rsvd2 R 000000 Reserved.
[7] HPhnEn RW 0
[6] OutEn RW 0 Output enable:
[5] InEn RW 0 Input enable:
[4.:0] Rsvd1 R 0 Reserved.
6.6.7. PortD UnsolResp
Get
Headphone amp enable:
1 = enabled, 0 = disabled.
1 = enabled 0 = disabled.
1 = enabled 0 = disabled.
Verb ID Payload Response
F08 00 See bitfield table.
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6.6.7.1. PortD UnsolResp
Bit Bitfield Name RW Reset Description
[31.:8] Rsvd2 R 000000 Reserved.
[7] En RW 0 Unsolicited response enable: 1 = en-
[6] Rsvd1 R 0 Reserved.
[5.:0] Tag RW 00 Software programmable field returned
6.6.8. PortD ChSense
abled 0 = disabled.
in top six bits (31:26) of every Unsolicited Response generated by this node.
Verb ID Payload Response
Get
F09 00 See bitfield table.
6.6.8.1. PortD ChSense
Bit Bitfield Name RW Reset Description
[31] PresDtct R 0 Presence detection indicator: 1 = pres-
ence detected; 0 = presence not detected.
[30.:1] Impedence R
[0] Execute RW 1
3FFFFFFFh Impedance Sense Value (Bits 30:1): Mea-
sured impedence of the widget. An all ones
value indicates an invalid sense reading
Impedance Sense Value (Bit 0)/Trigger:
Read = Impedance value bit 0
Write 0 = Impedance sense occurs using left
channel
Write 1 = Impedance sense occurs using
right channel
6.6.9. PortD InAmpLeft
Get
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Verb ID Payload Response
B20 00 See bitfield table.
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6.6.9.1. PortD InAmpLeft
Bit Bitfield Name RW Reset Description
[31.:2] Rsvd1 R 000000 Reserved.
[1.:0] Gain RW 0
6.6.10. PortD InAmpRight
Get
6.6.10.1. PortD InAmpRight
Bit Bitfield Name RW Reset Description
[31.:2] Rsvd1 R 000000 Reserved.
[1.:0] Gain RW 0
Amp gain step number (see InAmpCap parameter pertaining to this widget).
Verb ID Payload Response
B00 00 See bitfield table.
Amp gain step number (see InAmpCap parameter pertaining to this widget).
6.6.11. PortD ConfigDefault
Get
TSI™ CONFIDENTIAL
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Verb ID Payload Response
F1C 00 See bitfield table.
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6.6.11.1. PortD ConfigDefault
Bit Bitfield Name RW Reset Description
[31.:30] PortConnectivity RW 0 Port connectivity: 0h = Port complex is
[29.:24] Location RW 1 Location. Bits [5..4]: 0h = External on
[23.:20] Device RW 0 Default device: 0h = Line out; 1h =
connected to a jack; 1h = No physical
connection for port; 2h = Fixed function
device is attached; 3h = Both jack and
internal device attached (info in all other
fields refers to integrated device any
presence detection refers to jack)
primary chassis; 1h = Internal; 2h = Separate chassis; 3h = Other. Bits [3..0]: 0h
= N/A; 1h = Rear; 2h = Front; 3h = Left;
4h = Right; 5h = Top; 6h = Bottom;
7h-9h = Special; Ah-Fh = Reserved
Speaker; 2h = HP out; 3h = CD; 4h =
SPDIF Out; 5h = Digital other out; 6h =
Modem line side; 7h = Modem handset
side; 8h = Line in; 9h = Aux; Ah = Mic in;
Bh = Telephony; Ch = SPDIF In; Dh =
Digital other in; Eh = Reserved; Fh =
Other
[19.:16] ConnectionType RW 1 Connection type: 0h = Unknown; 1h =
1/8" stereo/mono; 2h = 1/4" stereo/mono; 3h = ATAPI internal; 4h = RCA; 5h =
Optical; 6h = Other digital; 7h = Other
analog; 8h = Multichannel analog (DIN);
9h = XLR/Professional; Ah = RJ-11 (modem); Bh = Combination; Ch-Eh = Reserved; Fh = Other
[15.:12] Color RW 4 Color: 0h = Unknown; 1h = Black; 2h =
Grey; 3h = Blue; 4h = Green; 5h = Red;
6h = Orange; 7h = Yellow; 8h = Purple;
9h = Pink; Ah-Dh = Reserved; Eh =
White; Fh = Other
[11.:8] Misc RW 0 Miscellaneous: Bits [3..1] = Reserved;
Bit 0 = Jack detect override
[7.:4] Association RW 1 Default assocation.
[3.:0] Sequence RW 0 Sequence.
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6.7. PortE Node (NID = 0E)
6.7.1. PortE WCap
Verb ID Payload Response
Get
F00 09 See bitfield table.
6.7.1.1. PortE WCap
Bit Bitfield Name RW Reset Description
[31.:24] Rsvd2 R 00 Reserved.
[23.:20] Type R 4 Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
[19.:16] Delay R 0 Number of sample delays through wid-
get.
[15.:12] Rsvd1 R 0 Reserved.
[11] SwapCap R 0 Left/right swap support: 1 = yes 0 = no.
[10] PwrCntrl R 0 Power state support: 1 = yes 0 = no.
[9] Dig R 0 Digital stream support: 1 = yes (digital)
[8] ConnList R 1 Connection list present: 1 = yes 0 = no.
[7] UnSolCap R 1 Unsolicited response support:
[6] ProcWidget R 0 Processing state support:
[5] Stripe R 0 Striping support: 1 = yes 0 = no.
[4] FormatOvrd R 0 Stream format override: 1 = yes 0 = no.
[3] AmpParOvrd R 0 Amplifier capabilities override:
[2] OutAmpPrsnt R 0 Output amp present: 1 = yes 0 = no.
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0 = no (analog).
1 = yes 0 = no.
1 = yes 0 = no.
1 = yes no.
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6.7.1.1. PortE WCap
Bit Bitfield Name RW Reset Description
[1] InAmpPrsnt R 1 Input amp present: 1 = yes 0 = no.
[0] Stereo R 1 Stereo stream support: 1 = yes (stereo)
6.7.2. PortE PinCap
Verb ID Payload Response
0 = no (mono).
Get
F00 0C See bitfield table.
6.7.2.1. PortE PinCap
Bit Bitfield Name RW Reset Description
[31.:17] Rsvd2 R 0000 Reserved.
[16] EapdCap R 0 EAPD support: 1 = yes 0 = no.
[15.:8] VrefCntrl R 17 Vref support: bit 7 = Reserved; bit 6 =
Reserved; bit 5 = 100% support (1 = yes
0 = no); bit 4 = 80% support (1 = yes 0
= no); bit 3 = Reserved; bit 2 = GND support (1 = yes 0 = no); bit 1 = 50% support (1 = yes 0 = no); bit 0 = Hi-Z
support (1 = yes 0 = no)
[7] Rsvd1 R 0 Reserved.
[6] BalancedIO R 0 Balanced I/O support: 1 = yes 0 = no.
[5] InCap R 1 Input support: 1 = yes 0 = no.
[4] OutCap R 1 Output support: 1 = yes 0 = no.
[3] HdphDrvCap R 0 Headphone amp present:
[2] PresDtctCap R 1 Presence detection support:
[1] TrigRqd R 1 Trigger required for impedance sense:
[0] ImpSenseCap R 0 Impedance sense support:
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1 = yes 0 = no.
1 = yes 0 = no.
1 = yes 0 = no.
1 = yes 0 = no.
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6.7.3. PortE ConLst
Verb ID Payload Response
Get
6.7.3.1. PortE ConLst
Bit Bitfield Name RW Reset Description
[31.:8] Rsvd R 000000 Reserved.
[7] LForm R 0 Connection list format: 1 = long-form
[6.:0] ConL R 03 Number of NID entries in connection list.
6.7.4. PortE ConLstEntry0
Get
F00 0E See bitfield table.
(15-bit) NID entries 0 = short-form
(7-bit) NID entries.
Verb ID Payload Response
F02 00 See bitfield table.
6.7.4.1. PortE ConLstEntry0
Bit Bitfield Name RW Reset Description
[31.:24] ConL3 R 00 Unused list entry.
[23.:16] ConL2 R 1E MixerOutVol Summing widget (0x1E)
[15] ConL1Range R 1
[15.:8] ConL1 R 17 DAC2 Converter widget (0x17)
[7.:0] ConL0 R 15 DAC0 Converter widget (0x15)
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6.7.5. PortE ConSelectCtrl
Verb ID Payload Response
Get
6.7.5.1. PortE ConSelectCtrl
Bit Bitfield Name RW Reset Description
[31.:2] Rsvd R 00000000 Reserved.
[1.:0] Index RW 0 Connection select control index.
6.7.6. PortE PinWCntrl
Get
6.7.6.1. PortE PinWCntrl
F01 00 See bitfield table.
Verb ID Payload Response
F07 00 See bitfield table.
Bit Bitfield Name RW Reset Description
[31.:6] Rsvd2 R 0000000 Reserved.
[5] InEn RW 0 Input enable: 1 = enabled 0 = disabled.
[4.:3] Rsvd1 R 0 Reserved.
[2.:0] VRefEn RW 0 Vref selection (See VrefCntrl field of
6.7.7. PortE UnsolResp
Get
PinCap parameter for supported selections): 000b= HI-Z; 001b= 50%; 010b=
GND; 011b= Reserved; 100b= 80%;
101b= 100%; 110b= Reserved; 111b=
Reserved
Verb ID Payload Response
F08 00 See bitfield table.
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6.7.7.1. PortE UnsolResp
Bit Bitfield Name RW Reset Description
[31.:8] Rsvd2 R 000000 Reserved.
[7] En RW 0 Unsolicited response enable: 1 = en-
[6] Rsvd1 R 0 Reserved.
[5.:0] Tag RW 00 Software programmable field returned
6.7.8. PortE ChSense
abled 0 = disabled.
in top six bits (31:26) of every Unsolicited Response generated by this node.
Verb ID Payload Response
Get
F09 00 See bitfield table.
6.7.8.1. PortD ChSense
Bit Bitfield Name RW Reset Description
[31] PresDtct R 0 Presence detection indicator: 1 = pres-
ence detected; 0 = presence not detected.
[30.:1] Impedence R
[0] Execute RW 1
3FFFFFFFh Impedance Sense Value (Bits 30:1): Mea-
sured impedence of the widget. An all ones
value indicates an invalid sense reading
Impedance Sense Value (Bit 0)/Trigger:
Read = Impedance value bit 0
Write 0 = Impedance sense occurs using left
channel
Write 1 = Impedance sense occurs using
right channel
6.7.9. PortE InAmpLeft
Get
TSI™ CONFIDENTIAL
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Verb ID Payload Response
B20 00 See bitfield table.
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6.7.9.1. PortE InAmpLeft
Bit Bitfield Name RW Reset Description
[31.:2] Rsvd1 R 000000 Reserved.
[1.:0] Gain RW 0
6.7.10. PortE InAmpRight
Get
6.7.10.1. PortE InAmpRight
Bit Bitfield Name RW Reset Description
[31.:2] Rsvd1 R 000000 Reserved.
[1.:0] Gain RW 0
Amp gain step number (see InAmpCap parameter pertaining to this widget).
Verb ID Payload Response
B00 00 See bitfield table.
Amp gain step number (see InAmpCap parameter pertaining to this widget).
6.7.11. PortE ConfigDefault
Get
TSI™ CONFIDENTIAL
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Verb ID Payload Response
F1C 00 See bitfield table.
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6.7.11.1. PortE ConfigDefault
Bit Bitfield Name RW Reset Description
[31.:30] PortConnectivity RW 0 Port connectivity: 0h = Port complex is
[29.:24] Location RW 1 Location. Bits [5..4]: 0h = External on
[23.:20] Device RW A Default device: 0h = Line out; 1h =
connected to a jack; 1h = No physical
connection for port; 2h = Fixed function
device is attached; 3h = Both jack and
internal device attached (info in all other
fields refers to integrated device any
presence detection refers to jack)
primary chassis; 1h = Internal; 2h = Separate chassis; 3h = Other. Bits [3..0]: 0h
= N/A; 1h = Rear; 2h = Front; 3h = Left;
4h = Right; 5h = Top; 6h = Bottom;
7h-9h = Special; Ah-Fh = Reserved
Speaker; 2h = HP out; 3h = CD; 4h =
SPDIF Out; 5h = Digital other out; 6h =
Modem line side; 7h = Modem handset
side; 8h = Line in; 9h = Aux; Ah = Mic in;
Bh = Telephony; Ch = SPDIF In; Dh =
Digital other in; Eh = Reserved; Fh =
Other
[19.:16] ConnectionType RW 1 Connection type: 0h = Unknown; 1h =
1/8" stereo/mono; 2h = 1/4" stereo/mono; 3h = ATAPI internal; 4h = RCA; 5h =
Optical; 6h = Other digital; 7h = Other
analog; 8h = Multichannel analog (DIN);
9h = XLR/Professional; Ah = RJ-11 (modem); Bh = Combination; Ch-Eh = Reserved; Fh = Other
[15.:12] Color RW 9 Color: 0h = Unknown; 1h = Black; 2h =
Grey; 3h = Blue; 4h = Green; 5h = Red;
6h = Orange; 7h = Yellow; 8h = Purple;
9h = Pink; Ah-Dh = Reserved; Eh =
White; Fh = Other
[11.:8] Misc RW 0 Miscellaneous: Bits [3..1] = Reserved;
Bit 0 = Jack detect override
[7.:4] Association RW 2 Default assocation.
[3.:0] Sequence RW 0 Sequence.
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6.8. PortF Node (NID = 0F)
6.8.1. PortF WCap
Verb ID Payload Response
Get
F00 09 See bitfield table.
6.8.1.1. PortF WCap
Bit Bitfield Name RW Reset Description
[31.:24] Rsvd2 R 00 Reserved.
[23.:20] Type R 4 Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
[19.:16] Delay R 0 Number of sample delays through wid-
get.
[15.:12] Rsvd1 R 0 Reserved.
[11] SwapCap R 0 Left/right swap support: 1 = yes 0 = no.
[10] PwrCntrl R 0 Power state support: 1 = yes 0 = no.
[9] Dig R 0 Digital stream support: 1 = yes (digital)
[8] ConnList R 1 Connection list present: 1 = yes 0 = no.
[7] UnSolCap R 1 Unsolicited response support:
[6] ProcWidget R 0 Processing state support:
[5] Stripe R 0 Striping support: 1 = yes 0 = no.
[4] FormatOvrd R 0 Stream format override: 1 = yes 0 = no.
[3] AmpParOvrd R 0 Amplifier capabilities override:
[2] OutAmpPrsnt R 0 Output amp present: 1 = yes 0 = no.
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0 = no (analog).
1 = yes 0 = no.
1 = yes 0 = no.
1 = yes no.
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6.8.1.1. PortF WCap
Bit Bitfield Name RW Reset Description
[1] InAmpPrsnt R 1 Input amp present: 1 = yes 0 = no.
[0] Stereo R 1 Stereo stream support: 1 = yes (stereo)
6.8.2. PortF PinCap
Verb ID Payload Response
0 = no (mono).
Get
F00 0C See bitfield table.
6.8.2.1. PortF PinCap
Bit Bitfield Name RW Reset Description
[31.:17] Rsvd2 R 0000 Reserved.
[16] EapdCap R 0 EAPD support: 1 = yes 0 = no.
[15.:8] VrefCntrl R 00 Vref support: bit 7 = Reserved; bit 6 =
Reserved; bit 5 = 100% support (1 = yes
0 = no); bit 4 = 80% support (1 = yes 0
= no); bit 3 = Reserved; bit 2 = GND support (1 = yes 0 = no); bit 1 = 50% support (1 = yes 0 = no); bit 0 = Hi-Z
support (1 = yes 0 = no)
[7] Rsvd1 R 0 Reserved.
[6] BalancedIO R 0 Balanced I/O support: 1 = yes 0 = no.
[5] InCap R 1 Input support: 1 = yes 0 = no.
[4] OutCap R 1 Output support: 1 = yes 0 = no.
[3] HdphDrvCap R 0 Headphone amp present:
[2] PresDtctCap R 1 Presence detection support:
[1] TrigRqd R 1 Trigger required for impedance sense:
[0] ImpSenseCap R 1 Impedance sense support:
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1 = yes 0 = no.
1 = yes 0 = no.
1 = yes 0 = no.
1 = yes 0 = no.
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6.8.3. PortF ConLst
Verb ID Payload Response
Get
6.8.3.1. PortF ConLst
Bit Bitfield Name RW Reset Description
[31.:8] Rsvd R 000000 Reserved.
[7] LForm R 0 Connection list format: 1 = long-form
[6.:0] ConL R 03 Number of NID entries in connection list.
6.8.4. PortF ConLstEntry0
Get
F00 0E See bitfield table.
(15-bit) NID entries 0 = short-form
(7-bit) NID entries.
Verb ID Payload Response
F02 00 See bitfield table.
6.8.4.1. PortF ConLstEntry0
Bit Bitfield Name RW Reset Description
[31.:24] ConL3 R 00 Unused list entry.
[23.:16] ConL2 R 17 InputMixer Summing widget (0x17)
[15] ConL1Range R 1
[14.:8] ConL1 R 11 DAC1 Converter widget (0x11)
[7.:0] ConL0 R 10 DAC0 Converter widget (0x10)
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1 = ConL0..ConL1 defines a range of selectable inputs.
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6.8.5. PortF ConSelectCtrl
Verb ID Payload Response
Get
6.8.5.1. PortF ConSelectCtrl
Bit Bitfield Name RW Reset Description
[31.:2] Rsvd R 00000000 Reserved.
[1.:0] Index RW 0 Connection select control index.
6.8.6. PortF PinWCntrl
Get
6.8.6.1. PortF PinWCntrl
F01 00 See bitfield table.
Verb ID Payload Response
F07 00 See bitfield table.
Bit Bitfield Name RW Reset Description
[31.:7] Rsvd2 R 000000 Reserved.
[6] OutEn RW 0 Output enable:
[5] InEn RW 0 input enable: 1 = enabled 0 = disabled.
[4.:0] Rsvd1 R 0 Reserved.
6.8.7. PortF UnsolResp
Get
1 = enabled 0 = disabled.
Verb ID Payload Response
F08 00 See bitfield table.
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6.8.7.1. PortF UnsolResp
Bit Bitfield Name RW Reset Description
[31.:8] Rsvd2 R 000000 Reserved.
[7] En RW 0 Unsolicited response enable: 1 = en-
[6] Rsvd1 R 0 Reserved.
[5.:0] Tag RW 00 Software programmable field returned
6.8.8. PortF ChSense
abled 0 = disabled.
in top six bits (31:26) of every Unsolicited Response generated by this node.
Verb ID Payload Response
Get
F09 00 See bitfield table.
6.8.8.1. PortF ChSense
Bit Bitfield Name RW Reset Description
[31] PresDtct R 0 Presence detection indicator: 1 = pres-
ence detected; 0 = presence not detected.
[30.:1] Impedence R
[0] Execute RW 1
3FFFFFFFhImpedance Sense Value (Bits 30:1): Mea-
sured impedence of the widget. An all ones
value indicates an invalid sense reading
Impedance Sense Value (Bit 0)/Trigger:
Read = Impedance value bit 0
Write 0 = Impedance sense occurs using left
channel
Write 1 = Impedance sense occurs using
right channel
6.8.9. PortF InAmpLeft
Get
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Verb ID Payload Response
B20 00 See bitfield table.
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