Datasheet 80C52, 87C52 Datasheet (Philips)

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Page 1

INTEGRATED CIRCUITS

80C51/87C51/80C52/87C52

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

Product specification Replaces datasheet 80C51/87C51/80C31 of 2000 Jan 20

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2000 Aug 07

Page 2

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

80C51/87C51/80C52/87C52

DESCRIPTION

The Philips 80C51/87C51/80C52/87C52 is a high-performance static 80C51 design fabricated with Philips high-density CMOS technology with operation from 2.7 V to 5.5 V .

The 8xC51 and 8xC52 contain a 128 × 8 RAM and 256 × 8 RAM respectively, 32 I/O lines, three 16-bit counter/timers, a six-source, four-priority level nested interrupt structure, a serial I/O port for either multi-processor communications, I/O expansion or full duplex UART, and on-chip oscillator and clock circuits.

In addition, the device is a low power static design which offers a wide range of operating frequencies down to zero. Two software selectable modes of power reduction—idle mode and power-down mode are available. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. Since the design is static, the clock can be stopped without loss of user data and then the execution resumed from the point the clock was stopped.

SELECTION TABLE

For applications requiring more ROM and RAM, see the 8XC54/58 and 8XC51RA+/RB+/RC+/80C51RA+ data sheet.

Note: 80C31/80C32 is specified in separate data sheet.

ROM/EPROM Memory Size

(X by 8)

80C31*/80C51/87C51

0K/4K 128 No No

80C32*/80C52/87C52

0K/8K/16K/32K 256 No No

80C51RA+/8XC51RA+/RB+/RC+

0K/8K/16K/32K 512 Yes Yes

8XC51RD+

64K 1024 Yes Yes

RAM Size

(X by 8)

Programmable

Timer Counter

(PCA)

Hardware

Watch Dog

Timer

FEA TURES

•8051 Central Processing Unit

– 4k × 8 ROM (80C51) – 8k × 8 ROM (80C52) – 128 × 8 RAM (80C51) – 256 × 8 RAM (80C52) – Three 16-bit counter/timers – Boolean processor – Full static operation – Low voltage (2.7 V to 5.5 V@ 16 MHz) operation

•Memory addressing capability

– 64k ROM and 64k RAM

•Power control modes:

– Clock can be stopped and resumed – Idle mode – Power-down mode

•CMOS and TTL compatible

•TWO speed ranges at V

– 0 to 16 MHz – 0 to 33 MHz

= 5 V

•Three package styles

•Extended temperature ranges

•Dual Data Pointers

•Security bits:

– ROM (2 bits) – OTP/EPROM (3 bits)

•Encryption array – 64 bytes

•4 level priority interrupt

•6 interrupt sources

•Four 8-bit I/O ports

•Full–duplex enhanced UART

– Framing error detection – Automatic address recognition

•Programmable clock out

•Asynchronous port reset

•Low EMI (inhibit ALE and slew rate controlled outputs)

•Wake-up from Power Down by an external interrupt

2000 Aug 07 853–0169 24291

Page 3

Philips Semiconductors Product specification

0 to +70, Plastic Dual In-line Package

2.7 V to 5.5 V

0 to 16

SOT129-1

0 to +70, Plastic Leaded Chip Carrier

2.7 V to 5.5 V

0 to 16

SOT187-2

0 to +70, Plastic Quad Flat Pack

2.7 V to 5.5 V

0 to 16

SOT307-2

Plastic Dual In-line Package

2.7 V to 5.5 V

0 to 16

SOT129-1

Plastic Leaded Chip Carrier

2.7 V to 5.5 V

0 to 16

SOT187-2

Plastic Quad Flat Pack

2.7 V to 5.5 V

0 to 16

SOT307-2

0 to +70, Plastic Leaded Chip Carrier

5 V

0 to 33

SOT187-2

0 to +70, Plastic Dual In-line Package

5 V

0 to 33

SOT129-1

Plastic Leaded Chip Carrier

5 V

0 to 33

SOT187-2

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

80C51/87C51 ORDERING INFORMATION

MEMORY SIZE

4K × 8

ROM P80C51SBPN OTP P87C51SBPN ROM P80C51SBAA OTP P87C51SBAA ROM P80C51SBBB OTP P87C51SBBB ROM P80C51SFPN OTP P87C51SFPN ROM P80C51SFAA OTP P87C51SFAA ROM P80C51SFBB OTP P87C51SFBB ROM P80C51UBAA OTP P87C51UBAA ROM P80C51UBPN OTP P87C51UBPN ROM P80C51UFAA OTP P87C51UFAA

TEMPERATURE RANGE °C

AND PACKAGE

–40 to +85,

80C51/87C51/80C52/87C52

VOLTAGE

RANGE

FREQ.

(MHz)

DWG. #

P ART NUMBER DERIVATION

DEVICE

NUMBER

ROM P80C51 S = 16 MHz ROM P80C52 S = 16 MHz

OTP P87C51 U = 33 MHz OTP P87C52 U = 33 MHz

DEVICE

NUMBER

OPERATING FREQUENCY, MAX (S) TEMPERATURE RANGE (B) PACKAGE (AA)

B = 0_ to +70_C

B = 0_ to +70_C F = –40_C to +85_C F = –40_C to +85_C

AA = PLCC AA = PLCC BB = PQFP BB = PQFP

2000 Aug 07

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Philips Semiconductors Product specification

0 to +70, Plastic Dual In-line Package

2.7 V to 5.5 V

0 to 16

SOT129-1

0 to +70, Plastic Leaded Chip Carrier

2.7 V to 5.5 V

0 to 16

SOT187-2

0 to +70, Plastic Quad Flat Pack

2.7 V to 5.5 V

0 to 16

SOT307-2

Plastic Dual In-line Package

2.7 V to 5.5 V

0 to 16

SOT129-1

Plastic Leaded Chip Carrier

2.7 V to 5.5 V

0 to 16

SOT187-2

Plastic Quad Flat Pack

2.7 V to 5.5 V

0 to 16

SOT307-2

0 to +70, Plastic Leaded Chip Carrier

5 V

0 to 33

SOT187-2

0 to +70, Plastic Dual In-line Package

5 V

0 to 33

SOT129-1

Plastic Leaded Chip Carrier

5 V

0 to 33

SOT187-2

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

80C52/87C52 ORDERING INFORMATION

MEMORY SIZE

8K × 8

ROM P80C52SBPN OTP P87C52SBPN ROM P80C52SBAA OTP P87C52SBAA ROM P80C52SBBB OTP P87C52SBBB ROM P80C52SFPN OTP P87C52SFPN ROM P80C52SFAA OTP P87C52SFAA ROM P80C52SFBB OTP P87C52SFBB ROM P80C52UBAA OTP P87C52UBAA ROM P80C52UBPN OTP P87C52UBPN ROM P80C52UFAA OTP P87C52UFAA

TEMPERATURE RANGE °C

AND PACKAGE

–40 to +85,

80C51/87C51/80C52/87C52

VOLTAGE

RANGE

FREQ.

(MHz)

DWG. #

2000 Aug 07

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Philips Semiconductors Product specification

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

BLOCK DIAGRAM

P0.0–P0.7 P2.0–P2.7

80C51/87C51/80C52/87C52

PSEN

ALE/PROG

EAV

RST

PORT 0

DRIVERS

RAM ADDR REGISTER

TIMING

AND

CONTROL

INSTRUCTION

RAM

ACC

TMP2

PSW

PORT 1

LATCH

PORT 0

LATCH

ALU

TMP1

PORT 2

DRIVERS

PORT 2

LATCH

SFRs

TIMERS

STACK

POINTER

PORT 3

LATCH

ROM/EPROM

PROGRAM

ADDRESS

BUFFER

INCRE-

MENTER

8 16

PROGRAM

COUNTER

DPTR’S

MULTIPLE

2000 Aug 07

OSCILLATOR

XTAL1 XTAL2

PORT 1

DRIVERS

P1.0–P1.7

PORT 3

DRIVERS

P3.0–P3.7

SU00845

Page 6

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

80C51/87C51/80C52/87C52

LOGIC SYMBOL

XTAL1

XTAL2

RST

EA/V

PSEN

ALE/PROG RxD TxD

INT0 INT1

T0 T1

SECONDARY FUNCTIONS

PORT 3

PIN CONFIGURA TIONS

PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS

ADDRESS AND

PORT 1PORT 2

DATA BUS

T2 T2EX

ADDRESS BUS

SU00830

Pin Function

1 NIC* 2 P1.0/T2 3 P1.1/T2EX 4 P1.2 5 P1.3 6 P1.4 7 P1.5 8 P1.6

9 P1.7 10 RST 11 P3.0/RxD 12 NIC* 13 P3.1/TxD 14 P3.2/INT0 15 P3.3/INT1

* NO INTERNAL CONNECTION

PORT 0

6140

18 28

Pin Function

16 P3.4/T0 17 P3.5/T1 18 P3.6/WR 19 P3.7/RD 20 XTAL2 21 XTAL1 22 V 23 NIC* 24 P2.0/A8 25 P2.1/A9 26 P2.2/A10 27 P2.3/A11 28 P2.4/A12 29 P2.5/A13 30 P2.6/A14

LCC

Pin Function

31 P2.7/A15 32 PSEN 33 ALE 34 NIC* 35 EA/V 36 P0.7/AD7 37 P0.6/AD6 38 P0.5/AD5 39 P0.4/AD4 40 P0.3/AD3 41 P0.2/AD2 42 P0.1/AD1 43 P0.0/AD0 44 V

SU01062

T2/P1.0

T2EX/P1.1

P1.2 P1.3 P1.4 P1.5 P1.6 P1.7

RST RxD/P3.0 TxD/P3.1

INT0

/P3.2 /P3.3

INT1

T0/P3.4 T1/P3.5

/P3.6

/P3.7

XTAL2 XTAL1

1 2 3 4 5 6 7 8 9

11 12 13 14 15 16 17 18 19 20

DUAL

IN-LINE

PACKAGE

SU01063

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA

ALE PSEN P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8

PLASTIC QUAD FLAT PACK PIN FUNCTIONS

44 34

PQFP

12 22

Pin Function

1 P1.5 2 P1.6 3 P1.7 4 RST 5 P3.0/RxD 6 NIC* 7 P3.1/TxD 8 P3.2/INT0

9 P3.3/INT1 10 P3.4/T0 11 P3.5/T1 12 P3.6/WR 13 P3.7/RD 14 XTAL2 15 XTAL1

* NO INTERNAL CONNECTION

Pin Function

16 V

17 NIC* 18 P2.0/A8 19 P2.1/A9 20 P2.2/A10 21 P2.3/A11 22 P2.4/A12 23 P2.5/A13 24 P2.6/A14 25 P2.7/A15 26 PSEN 27 ALE 28 NIC*

29 EA 30 P0.7/AD7

Pin Function

31 P0.6/AD6 32 P0.5/AD5 33 P0.4/AD4 34 P0.3/AD3 35 P0.2/AD2 36 P0.1/AD1 37 P0.0/AD0 38 V

39 NIC* 40 P1.0/T2 41 P1.1/T2EX 42 P1.2 43 P1.3 44 P1.4

SU01064

2000 Aug 07

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Philips Semiconductors Product specification

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

PIN DESCRIPTIONS

PIN NUMBER

MNEMONIC DIP LCC QFP TYPE NAME AND FUNCTION

P0.0–0.7 39–32 43–36 37–30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port with Schmitt trigger inputs. Port 0 pins

P1.0–P1.7 1–8 2–9 40–44,

P2.0–P2.7 21–28 24–31 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups and Schmitt trigger

P3.0–P3.7 10–17 11,

RST 9 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the

ALE/PROG 30 33 27 O Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the

PSEN 29 32 26 O Program Store Enable: The read strobe to external program memory. When the device is

EA/V

XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator

XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier.

NOTE:

To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than V

20 22 16 I Ground: 0 V reference. 40 44 38 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation.

that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory . In this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification and received code bytes during EPROM programming. External pull-ups are required during program verification.

1–3

1 2 40 I/O T2 (P1.0): Timer/Counter 2 external count input/clockout (see Programmable Clock-Out) 2 3 41 I T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction control

13–195,7–13

10 11 5 I RxD (P3.0): Serial input port 11 13 7 O TxD (P3.1): Serial output port 12 14 8 I INT0 (P3.2): External interrupt 13 15 9 I INT1 (P3.3): External interrupt 14 16 10 I T0 (P3.4): Timer 0 external input 15 17 11 I T1 (P3.5): Timer 1 external input 16 18 12 O WR (P3.6): External data memory write strobe 17 19 13 O RD (P3.7): External data memory read strobe

31 35 29 I External Access Enable/Programming Supply Voltage: EA must be externally held low

I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups and Schmitt trigger

inputs. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: I receives the low-order address byte during program memory verification. Alternate functions for Port 1 include:

inputs. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-u p s when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. Some Port 2 pins receive the high order address bits during EPROM programming and verification.

I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups and Schmitt trigger

inputs. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the 80C51 family, as listed below:

device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC.

address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during EPROM programming. ALE can be disabled by setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction.

executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory.

to enable the device to fetch code from external program memory locations 0000H to 0FFFH. If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than the on-chip ROM/OTP. This pin also receives the 12.75 V programming supply voltage (VPP) during EPROM programming. If security bit 1 is programmed, EA will be internally latched on Reset.

circuits.

80C51/87C51/80C52/87C52

). Port 1 also

+ 0.5 V or VSS – 0.5 V, respectively.

2000 Aug 07

Page 8

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

Table 1. 80C51/87C51/80C52/87C52 Special Function Registers

SYMBOL DESCRIPTION

ACC* Accumulator E0H E7 E6 E5 E4 E3 E2 E1 E0 00H AUXR# Auxiliary 8EH – – – – – – – AO xxxxxxx0B AUXR1# Auxiliary 1 A2H – – – LPEP2WUPD 0 – DPS xxx000x0B B* B register F0H F7 F6 F5 F4 F3 F2 F1 F0 00H DPTR: Data Pointer (2 bytes)

DPH Data Pointer High 83H 00H DPL Data Pointer Low 82H 00H

IE* Interrupt Enable A8H EA – ET2 ES ET1 EX1 ET0 EX0 0x000000B

IP* Interrupt Priority B8H – – PT2 PS PT1 PX1 PT0 PX0 xx000000B

IPH# Interrupt Priority High B7H – – PT2H PSH PT1H PX1H PT0H PX0H xx000000B

P0* Port 0 80H AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 FFH

P1* Port 1 90H – – – – – – T2EX T2 FFH

P2* Port 2 A0H AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 FFH

P3* Port 3 B0H RD WR T1 T0 INT1 INT0 TxD RxD FFH

DIRECT

ADDRESS

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB

AF AE AD AC AB AA A9 A8

BF BE BD BC BB BA B9 B8

B7 B6 B5 B4 B3 B2 B1 B0

87 86 85 84 83 82 81 80

97 96 95 94 93 92 91 90

A7 A6 A5 A4 A3 A2 A1 A0

B7 B6 B5 B4 B3 B2 B1 B0

80C51/87C51/80C52/87C52

RESET VALUE

PCON#1Power Control 87H SMOD1 SMOD0 – POF GF1 GF0 PD IDL 00xx0000B

D7 D6 D5 D4 D3 D2 D1 D0

PSW* Program Status Word D0H CY AC F0 RS1 RS0 OV – P 000000x0B

RACAP2H# Timer 2 Capture High CBH 00H RACAP2L# Timer 2 Capture Low CAH 00H

SADDR# Slave Address A9H 00H SADEN# Slave Address Mask B9H 00H

SBUF Serial Data Buffer 99H xxxxxxxxB

9F 9E 9D 9C 9B 9A 99 98 SCON* Serial Control 98H SP Stack Pointer 81H 07H

TCON* Timer Control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H

T2CON* Timer 2 Control C8H TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 00H T2MOD# Timer 2 Mode Control C9H – – – – – – T2OE DCEN xxxxxx00B

TH0 Timer High 0 8CH 00H TH1 Timer High 1 8DH 00H TH2# Timer High 2 CDH 00H TL0 Timer Low 0 8AH 00H TL1 Timer Low 1 8BH 00H TL2# Timer Low 2 CCH 00H

TMOD Timer Mode 89H GATE C/T M1 M0 GATE C/T M1 M0 00H

NOTE:

Unused register bits that are not defined should not be set by the user’s program. If violated, the device could function incorrectly. * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. – Reserved bits.

1. Reset value depends on reset source.

2. LPEP – Low Power EPROM operation (OTP/EPROM only)

SM0/FE

8F 8E 8D 8C 8B 8A 89 88

CF CE CD CC CB CA C9 C8

SM1 SM2 REN TB8 RB8 TI RI 00H

2000 Aug 07

Page 9

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

80C51/87C51/80C52/87C52

OSCILLA T OR CHARACTERISTICS

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier . The pins can be configured for use as an on-chip oscillator, as shown in the logic symbol.

To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed.

Reset

A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. To insure a good power-up reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles.

Stop Clock Mode

The static design enables the clock speed to be reduced down to 0 MHz (stopped). When the oscillator is stopped, the RAM and Special Function Registers retain their values. This mode allows step-by-step utilization and permits reduced system power consumption by lowering the clock frequency down to any value. For lowest power consumption the Power Down mode is suggested.

Idle Mode

In idle mode (see Table 2), the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset.

Power-Down Mode

To save even more power, a Power Down mode (see Table 2) can be invoked by software. In this mode, the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values down to 2.0 V and care must be taken to return VCC to the minimum specified operating voltages before the Power Down Mode is terminated.

For the 87C51 and 80C51 either a hardware reset or external interrupt can be used to exit from Power Down. Reset redefines all

the SFRs but does not change the on-chip RAM. An external interrupt allows both the SFRs and the on-chip RAM to retain their values. WUPD (AUXR1.3–Wakeup from Power Down) enables or disables the wakeup from power down with external interrupt. Where:

WUPD = 0 Disable WUPD = 1 Enable

To properly terminate Power Down the reset or external interrupt should not be executed before V operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10 ms).

With an external interrupt, INT0 or INT1 must be enabled and configured as level-sensitive. Holding the pin low restarts the oscillator but bringing the pin back high completes the exit. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down.

is restored to its normal

LPEP

The eprom array contains some analog circuits that are not required when V 4 V . The LPEP bit (AUXR.4), when set, will powerdown these analog circuits resulting in a reduced supply current. This bit should be set ONLY for applications that operate at a VCC less than 4 V.

is less than 4 V, but are required for a VCC greater than

Design Consideration

•When the idle mode is terminated by a hardware reset, the device

normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.

ONCE Mode

The ONCE (“On-Circuit Emulation”) Mode facilitates testing and debugging of systems without the device having to be removed from the circuit. The ONCE Mode is invoked by:

1. Pull ALE low while the device is in reset and PSEN

2. Hold ALE low as RST is deactivated. While the device is in ONCE Mode, the Port 0 pins go into a float

state, and the other port pins and ALE and PSEN high. The oscillator circuit remains active. While the device is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied.

is high;

are weakly pulled

Table 2. External Pin Status During Idle and Power-Down Modes

MODE PROGRAM MEMORY ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3

Idle Internal 1 1 Data Data Data Data Idle External 1 1 Float Data Address Data Power-down Internal 0 0 Data Data Data Data Power-down External 0 0 Float Data Data Data

2000 Aug 07

Page 10

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

80C51/87C51/80C52/87C52

Programmable Clock-Out

A 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed:

1. to input the external clock for Timer/Counter 2, or

2. to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz at a 16 MHz operating frequency.

To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in T2CON) must be cleared and bit T20E in T2MOD must be set. Bit TR2 (T2CON.2) also must be set to start the timer.

The Clock-Out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L) as shown in this equation:

Oscillator Frequency

4 (65536* RCAP2H, RCAP2L)

Where:

(RCAP2H,RCAP2L) = the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer.

In the Clock-Out mode Timer 2 roll-overs will not generate an interrupt. This is similar to when it is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and the Clock-Out frequency will be the same.

TIMER 2 OPERATION Timer 2

Timer 2 is a 16-bit Timer/Counter which can operate as either an event timer or an event counter, as selected by C/T function register T2CON (see Figure 1). Timer 2 has three operating modes:Capture, Auto-reload (up or down counting) ,and Baud Rate Generator, which are selected by bits in the T2CON as shown in Table 3.

2* in the special

Capture Mode

In the capture mode there are two options which are selected by bit EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or counter (as selected by C/T2* in T2CON) which, upon overflowing sets bit TF2, the timer 2 overflow bit. This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit in the IE register). If EXEN2= 1, Timer 2 operates as described above, but with the added feature that a 1- to -0 transition at external input T2EX causes the current value in the Timer 2 registers, TL2 and

TH2, to be captured into registers RCAP2L and RCAP2H, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2 like TF2 can generate an interrupt (which vectors to the same location as Timer 2 overflow interrupt. The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to determine which event caused the interrupt). The capture mode is illustrated in Figure 2 (There is no reload value for TL2 and TH2 in this mode. Even when a capture event occurs from T2EX, the counter keeps on counting T2EX pin transitions or osc/12 pulses.).

Auto-Reload Mode (Up or Down Counter)

In the 16-bit auto-reload mode, Timer 2 can be configured (as either a timer or counter (C/T2* in T2CON)) then programmed to count up or down. The counting direction is determined by bit DCEN (Down Counter Enable) which is located in the T2MOD register (see Figure 3). When reset is applied the DCEN=0 which means Timer 2 will default to counting up. If DCEN bit is set, Timer 2 can count up or down depending on the value of the T2EX pin.

Figure 4 shows Timer 2 which will count up automatically since DCEN=0. In this mode there are two options selected by bit EXEN2 in T2CON register. If EXEN2=0, then T imer 2 counts up to 0FFFFH and sets the TF2 (Overflow Flag) bit upon overflow. This causes the Timer 2 registers to be reloaded with the 16-bit value in RCAP2L and RCAP2H. The values in RCAP2L and RCAP2H are preset by software means.

If EXEN2=1, then a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at input T2EX. This transition also sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be generated when either TF2 or EXF2 are 1.

In Figure 5 DCEN=1 which enables Timer 2 to count up or down. This mode allows pin T2EX to control the direction of count. When a logic 1 is applied at pin T2EX Timer 2 will count up. Timer 2 will overflow at 0FFFFH and set the TF2 flag, which can then generate an interrupt, if the interrupt is enabled. This timer overflow also causes the 16–bit value in RCAP2L and RCAP2H to be reloaded into the timer registers TL2 and TH2.

When a logic 0 is applied at pin T2EX this causes Timer 2 to count down. The timer will underflow when TL2 and TH2 become equal to the value stored in RCAP2L and RCAP2H. Timer 2 underflow sets the TF2 flag and causes 0FFFFH to be reloaded into the timer registers TL2 and TH2.

The external flag EXF2 toggles when Timer 2 underflows or overflows. This EXF2 bit can be used as a 17th bit of resolution if needed. The EXF2 flag does not generate an interrupt in this mode of operation.

Table 3. Timer 2 Operating Modes

RCLK + TCLK CP/RL2 TR2 MODE

0 0 1 16-bit Auto-reload 0 1 1 16-bit Capture 1 X 1 Baud rate generator

X X 0 (off)

2000 Aug 07

Page 11

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

(MSB) (LSB)

80C51/87C51/80C52/87C52

TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2

CP/RL2

Symbol Position Name and Significance

TF2 T2CON.7 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set

when either RCLK or TCLK = 1.

EXF2 T2CON.6 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and

EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).

RCLK T2CON.5 Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock

in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.

TCLK T2CON.4 Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock

in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.

EXEN2 T2CON.3 Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative

transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to

ignore events at T2EX. TR2 T2CON.2 Start/stop control for Timer 2. A logic 1 starts the timer. C/T2

T2CON.1 Timer or counter select. (T imer 2)

0 = Internal timer (OSC/12) 1 = External event counter (falling edge triggered).

CP/RL2

T2CON.0 Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When

cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when

EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload

on Timer 2 overflow .

SU00728

Figure 1. Timer/Counter 2 (T2CON) Control Register

T2 Pin

T2EX Pin

OSC

÷ 12

Transition

Detector

C/T2 = 0

= 1

C/T2

EXEN2

Control

TR2

Capture

Control

Figure 2. Timer 2 in Capture Mode

TL2

(8-bits)

RCAP2L RCAP2H

TH2

(8-bits)

TF2

EXF2

Timer 2

Interrupt

SU00066

2000 Aug 07

Page 12

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

T2MOD Address = 0C9H Reset Value = XXXX XX00B

Not Bit Addressable

— — — — — — T2OE DCEN

80C51/87C51/80C52/87C52

Bit

76543210

Symbol Function

— Not implemented, reserved for future use.* T2OE Timer 2 Output Enable bit. DCEN Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter.

* User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features.

In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.

SU00729

Figure 3. Timer 2 Mode (T2MOD) Control Register

OSC

T2 PIN

÷ 12

TRANSITION

DETECTOR

C/T2 = 0

= 1

C/T2

TR2

CONTROL

RELOAD

TL2

(8-BITS)

RCAP2L RCAP2H

TH2

(8-BITS)

TF2

T2EX PIN

CONTROL

EXEN2

Figure 4. Timer 2 in Auto-Reload Mode (DCEN = 0)

EXF2

TIMER 2

INTERRUPT

SU00067

2000 Aug 07

Page 13

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

(DOWN COUNTING RELOAD VALUE)

FFH FFH

80C51/87C51/80C52/87C52

TOGGLE

EXF2

OSC

T2 Pin

T2 PIN

÷12

÷ 2

C/T2 = 0

= 1

C/T2

TR2

Figure 5. Timer 2 Auto Reload Mode (DCEN = 1)

NOTE: OSC. Freq. is divided by 2, not 12.

C/T2 = 0

C/T2

= 1

Transition

Detector

CONTROL

Control

TR2

TH2

(8-bits)

OVERFLOW

÷ 2

Reload

TL2 TH2

RCAP2L RCAP2H

(UP COUNTING RELOAD VALUE) T2EX PIN

TL2

(8-bits)

RCAP2L RCAP2H

COUNT DIRECTION 1 = UP 0 = DOWN

Timer 1

Overflow

“0” “1”

“0”“1”

TF2

÷ 16

÷ 16 TX Clock

INTERRUPT

SU00730

SMOD

RCLK

RX Clock

TCLK

T2EX Pin

2000 Aug 07

EXF2

Control

EXEN2

Note availability of additional external interrupt.

Figure 6. Timer 2 in Baud Rate Generator Mode

Timer 2 Interrupt

SU00068

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Philips Semiconductors Product specification

Baud Rate

Osc Freq

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

80C51/87C51/80C52/87C52

Baud Rate Generator Mode

Bits TCLK and/or RCLK in T2CON (Table 3) allow the serial port transmit and receive baud rates to be derived from either Timer 1 or Timer 2. When TCLK= 0, Timer 1 is used as the serial port transmit baud rate generator . When TCLK= 1, Timer 2 is used as the serial port transmit baud rate generator. RCLK has the same effect for the serial port receive baud rate. With these two bits, the serial port can have different receive and transmit baud rates – one generated by Timer 1, the other by Timer 2.

Figure 6 shows the Timer 2 in baud rate generation mode. The baud rate generation mode is like the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software.

The baud rates in modes 1 and 3 are determined by Timer 2’s overflow rate given below:

Modes 1 and 3 Baud Rates +

The timer can be configured for either “timer” or “counter” operation. In many applications, it is configured for “timer” operation (C/T Timer operation is different for Timer 2 when it is being used as a baud rate generator.

Usually, as a timer it would increment every machine cycle (i.e., 1/12 the oscillator frequency). As a baud rate generator, it increments every state time (i.e., 1/2 the oscillator frequency). Thus the baud rate formula is as follows:

Modes 1 and 3 Baud Rates =

Oscillator Frequency

[32 [65536* (RCAP2H, RCAP2L)]]

Where: (RCAP2H, RCAP2L)= The content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer.

The Timer 2 as a baud rate generator mode shown in Figure 6, is valid only if RCLK and/or TCLK = 1 in T2CON register. Note that a rollover in TH2 does not set TF2, and will not generate an interrupt. Thus, the Timer 2 interrupt does not have to be disabled when Timer 2 is in the baud rate generator mode. Also if the EXEN2 (T2 external enable flag) is set, a 1-to-0 transition in T2EX (Timer/counter 2 trigger input) will set EXF2 (T2 external flag) but will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2). Therefore when Timer 2 is in use as a baud rate generator, T2EX can be used as an additional external interrupt, if needed.

When Timer 2 is in the baud rate generator mode, one should not try to read or write TH2 and TL2. As a baud rate generator, T imer 2 is incremented every state time (osc/2) or asynchronously from pin T2;

Timer 2 Overflow Rate

2*=0).

under these conditions, a read or write of TH2 or TL2 may not be accurate. The RCAP2 registers may be read, but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers.

Table 4 shows commonly used baud rates and how they can be obtained from Timer 2.

Table 4. Timer 2 Generated Commonly Used

Baud Rates

Timer 2

RCAP2H RCAP2L

375 K 12 MHz FF FF

9.6 K 12 MHz FF D9

2.8 K 12 MHz FF B2

2.4 K 12 MHz FF 64

1.2 K 12 MHz FE C8 300 12 MHz FB 1E 110 12 MHz F2 AF 300 6 MHz FD 8F 110 6 MHz F9 57

Summary Of Baud Rate Equations

Timer 2 is in baud rate generating mode. If Timer 2 is being clocked through pin T2(P1.0) the baud rate is:

Baud Rate +

If Timer 2 is being clocked internally, the baud rate is:

Baud Rate +

Where f

OSC

To obtain the reload value for RCAP2H and RCAP2L, the above equation can be rewritten as:

RCAP2H,RCAP2L + 65536 *

Timer 2 Overflow Rate

[32 [65536* (RCAP2H, RCAP2L)]]

= Oscillator Frequency

OSC

32 Baud Rate

OSC

Timer/Counter 2 Set-up

Except for the baud rate generator mode, the values given for T2CON do not include the setting of the TR2 bit. Therefore, bit TR2 must be set, separately, to turn the timer on. See Table 5 for set-up of Timer 2 as a timer. Also see Table 6 for set-up of Timer 2 as a counter.

2000 Aug 07

Page 15

Philips Semiconductors Product specification

MODE

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

Table 5. Timer 2 as a Timer

INTERNAL CONTROL (Note 1) EXTERNAL CONTROL (Note 2)

16-bit Auto-Reload 00H 08H 16-bit Capture 01H 09H Baud rate generator receive and transmit same baud rate 34H 36H Receive only 24H 26H Transmit only 14H 16H

Table 6. Timer 2 as a Counter

INTERNAL CONTROL (Note 1) EXTERNAL CONTROL (Note 2)

16-bit 02H 0AH Auto-Reload 03H 0BH

NOTES:

1. Capture/reload occurs only on timer/counter overflow.

2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate generator mode.

80C51/87C51/80C52/87C52

T2CON

TMOD

Enhanced UART

The UART operates in all of the usual modes that are described in the first section of

Microcontrollers

detect by looking for missing stop bits, and automatic address recognition. The UART also fully supports multiprocessor communication.

When used for framing error detect the UART looks for missing stop bits in the communication. A missing bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0 and the function of SCON.7 is determined by PCON.6 (SMOD0) (see Figure 7). If SMOD0 is set then SCON.7 functions as FE. SCON.7 functions as SM0 when SMOD0 is cleared. When used as FE SCON.7 can only be cleared by software. Refer to Figure 8.

Automatic Address Recognition

Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the “Given” address or the “Broadcast” address. The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. Automatic address recognition is shown in Figure 9.

The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address.

Mode 0 is the Shift Register mode and SM2 is ignored. Using the Automatic Address Recognition feature allows a master to

selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave’s address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the

Data Handbook IC20, 80C51-Based 8-Bit

. In addition the UART can perform framing error

SADDR are to b used and which bits are “don’t care”. The SADEN mask can be logically ANDed with the SADDR to create the “Given” address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme:

Slave 0 SADDR = 1100 0000

SADEN = 1111 1101 Given = 1100 00X0

Slave 1 SADDR = 1100 0000

SADEN = 1111 1110 Given = 1100 000X

In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000.

In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0:

Slave 0 SADDR = 1100 0000

SADEN = 1111 1001 Given = 1100 0XX0

Slave 1 SADDR = 11 10 0000

SADEN = 1111 1010 Given = 1110 0X0X

Slave 2 SADDR = 11 10 0000

SADEN = 1111 1100 Given = 1110 00XX

In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0

2000 Aug 07

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Philips Semiconductors Product specification

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

80C51/87C51/80C52/87C52

and 1 and exclude Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2.

The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are trended as don’t-cares. In most cases, interpreting the don’t-cares as ones, the broadcast address will be FF hexadecimal.

SCON Address = 98H

Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are leaded with 0s. This produces a given address of all “don’t cares” as well as a Broadcast address of all “don’t cares”. This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature.

Reset Value = 0000 0000B

Bit Addressable

SM0/FE SM1 SM2 REN TB8 RB8 Tl Rl

Bit: 76543210

(SMOD0 = 0/1)*

Symbol Function FE Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid

frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit.

SM0 Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0) SM1 Serial Port Mode Bit 1

SM0 SM1 Mode Description Baud Rate**

0 0 0 shift register f

OSC

/12 0 1 1 8-bit UART variable 1 0 2 9-bit UART f

OSC

/64 or f

OSC

/32

1 1 3 9-bit UART variable

SM2 Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the

received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a Given or Broadcast Address. In Mode 0, SM2 should be 0.

REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. RB8 In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.

In Mode 0, RB8 is not used.

Tl T ransmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the

other modes, in any serial transmission. Must be cleared by software.

Rl Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in

the other modes, in any serial reception (except see SM2). Must be cleared by software.

NOTE:

*SMOD0 is located at PCON6.

= oscillator frequency

**f

OSC

Figure 7. SCON: Serial Port Control Register

SU00043

2000 Aug 07

Page 17

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

D0 D1 D2 D3 D4 D5 D6 D7 D8

80C51/87C51/80C52/87C52

START

BIT

SM0 / FE SM1 SM2 REN TB8 RB8 TI RI

SMOD1 SMOD0 – POF GF1 GF0 PD IDL

0 : SCON.7 = SM0 1 : SCON.7 = FE

DATA BYTE

SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR)

SM0 TO UART MODE CONTROL

Figure 8. UART Framing Error Detection

D0 D1 D2 D3 D4 D5 D6 D7 D8

SM0 SM1 SM2 REN TB8 RB8 TI RI

1 1

1 0

11 X

ONLY IN

MODE 2, 3

SCON

(98H)

PCON

(87H)

STOP

BIT

SU01191

SCON

(98H)

RECEIVED ADDRESS D0 TO D7

PROGRAMMED ADDRESS

IN UART MODE 2 OR MODE 3 AND SM2 = 1: INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS” – WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES – WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.

COMPARATOR

Figure 9. UART Multiprocessor Communication, Automatic Address Recognition

SU00045

2000 Aug 07

Page 18

Philips Semiconductors Product specification

INTERRUPT PRIORITY LEVEL

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

80C51/87C51/80C52/87C52

Interrupt Priority Structure

The 80C51/87C51 and 80C52/87C52 have a 6-source four-level interrupt structure. They are the IE, IP and IPH. (See Figures 10, 11, and 12.) The IPH (Interrupt Priority High) register that makes the four-level interrupt structure possible. The IPH is located at SFR address B7H. The structure of the IPH register and a description of its bits is shown in Figure 12.

The function of the IPH SFR is simple and when combined with the IP SFR determines the priority of each interrupt. The priority of each interrupt is determined as shown in the following table:

PRIORITY BITS

IPH.x IP.x

0 0 Level 0 (lowest priority) 0 1 Level 1 1 0 Level 2 1 1 Level 3 (highest priority)

Table 7. Interrupt Table

SOURCE POLLING PRIORITY REQUEST BITS HARDWARE CLEAR? VECTOR ADDRESS

X0 1 IE0 N (L)1Y (T) T0 2 TP0 Y 0BH X1 3 IE1 N (L) Y (T) 13H T1 4 TF1 Y 1BH SP 5 RI, TI N 23H T2 6 TF2, EXF2 N 2BH

NOTES:

1. L = Level activated

2. T = Transition activated

An interrupt will be serviced as long as an interrupt of equal or higher priority is not already being serviced. If an interrupt of equal or higher level priority is being serviced, the new interrupt will wait until it is finished before being serviced. If a lower priority level interrupt is being serviced, it will be stopped and the new interrupt serviced. When the new interrupt is finished, the lower priority level interrupt that was stopped will be completed.

03H

BIT SYMBOL FUNCTION

IE.7 EA Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually IE.6 — Not implemented. Reserved for future use.

IE.5 ET2 Timer 2 interrupt enable bit. IE.4 ES Serial Port interrupt enable bit. IE.3 ET1 Timer 1 interrupt enable bit. IE.2 EX1 External interrupt 1 enable bit. IE.1 ET0 Timer 0 interrupt enable bit. IE.0 EX0 External interrupt 0 enable bit.

2000 Aug 07

Enable Bit = 1 enables the interrupt. Enable Bit = 0 disables it.

enabled or disabled by setting or clearing its enable bit.

Figure 10. IE Registers

01234567

ET0EX1ET1ESET2—EA

EX0IE (0A8H)

SU00571

Page 19

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

Priority Bit = 1 assigns higher priority Priority Bit = 0 assigns lower priority

BIT SYMBOL FUNCTION

IP.7 — Not implemented, reserved for future use. IP.6 — Not implemented, reserved for future use. IP.5 PT2 Timer 2 interrupt priority bit. IP.4 PS Serial Port interrupt priority bit. IP.3 PT1 Timer 1 interrupt priority bit. IP.2 PX1 External interrupt 1 priority bit. IP.1 PT0 Timer 0 interrupt priority bit. IP.0 PX0 External interrupt 0 priority bit.

Figure 11. IP Registers

80C51/87C51/80C52/87C52

01234567

PT0PX1PT1PSPT2——

PT0HPX1HPT1HPSHPT2H——

PX0IP (0B8H)

SU00572

01234567

PX0HIPH (B7H)

Priority Bit = 1 assigns higher priority Priority Bit = 0 assigns lower priority

BIT SYMBOL FUNCTION

IPH.7 — Not implemented, reserved for future use. IPH.6 — Not implemented, reserved for future use. IPH.5 PT2H Timer 2 interrupt priority bit high. IPH.4 PSH Serial Port interrupt priority bit high. IPH.3 PT1H Timer 1 interrupt priority bit high. IPH.2 PX1H External interrupt 1 priority bit high. IPH.1 PT0H Timer 0 interrupt priority bit high. IPH.0 PX0H External interrupt 0 priority bit high.

Figure 12. IPH Registers

SU01058

2000 Aug 07

Page 20

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

80C51/87C51/80C52/87C52

Reduced EMI

All port pins of the 8xC51 and 8xC52 have slew rate controlled outputs. This is to limit noise generated by quickly switching output signals. The slew rate is factory set to approximately 10 ns rise and fall times.

Reduced EMI Mode

The AO bit (AUXR.0) in the AUXR register when set disables the ALE output.

AUXR (8EH)

765432 1 0 – – – – – – – AO

AUXR.0 AO Turns off ALE output.

Dual DPTR

The dual DPTR structure (see Figure 13) enables a way to specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1/bit0 that allows the program code to switch between them.

•New Register Name: AUXR1#

•SFR Address: A2H

•Reset Value: xxx000x0B

AUXR1 (A2H)

76543210 – – – LPEP WUPD 0 – DPS

Where:

DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1.

Select Reg DPS

DPTR0 0 DPTR1 1

Note that bit 2 is not writable and is always read as a zero. This allows the DPS bit to be quickly toggled simply by executing an INC DPTR instruction without affecting the WOPD or LPEP bits.

DPS BIT0

AUXR1

DPH

(83H)

DPL

(82H)

DPTR1 DPTR0

EXTERNAL

DATA

MEMORY

SU00745A

Figure 13.

DPTR Instructions

The instructions that refer to DPTR refer to the data pointer that is currently selected using the AUXR1/bit 0 register. The six instructions that use the DPTR are as follows:

INC DPTR Increments the data pointer by 1 MOV DPTR, #data16 Loads the DPTR with a 16-bit constant MOV A, @ A+DPTR Move code byte relative to DPTR to ACC MOVX A, @ DPTR Move external RAM (16-bit address) to

ACC

MOVX @ DPTR , A Move ACC to external RAM (16-bit

address)

JMP @ A + DPTR Jump indirect relative to DPTR

The data pointer can be accessed on a byte-by-byte basis by specifying the low or high byte in an instruction which accesses the SFRs. See application note AN458 for more details.

The DPS bit status should be saved by software when switching between DPTR0 and DPTR1.

2000 Aug 07

Page 21

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

80C51/87C51/80C52/87C52

ABSOLUTE MAXIMUM RATINGS

Operating temperature under bias 0 to +70 or –40 to +85 °C Storage temperature range –65 to +150 °C Voltage on EA/VPP pin to V Voltage on any other pin to V Maximum IOL per I/O pin 15 mA Power dissipation (based on package heat transfer limitations, not device power consumption) 1.5 W

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied.

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V noted.

1, 2, 3

PARAMETER

RATING UNIT

0 to +13.0 V

–0.5 to +6.5 V

unless otherwise

AC ELECTRICAL CHARACTERISTICS

= 0°C to +70°C or –40°C to +85°C

amb

CLOCK FREQUENCY

RANGE –f

SYMBOL FIGURE PARAMETER MIN MAX UNIT

1/t

CLCL

29 Oscillator frequency

Speed versions : S (16 MHz)

U (33 MHz)

0 0

16 33

MHz MHz

2000 Aug 07

Page 22

Philips Semiconductors Product specification

SYMBOL

PARAMETER

UNIT

VILInput lo

oltage

VOHOutput high voltage, ports 1, 2, 3

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

DC ELECTRICAL CHARACTERISTICS

= 0°C to +70°C or –40°C to +85°C, VCC = 2.7 V to 5.5 V, VSS = 0 V (16 MHz devices)

amb

TEST

CONDITIONS

w v

IH1

OL1

OH1

Input high voltage (ports 0, 1, 2, 3, EA) 0.2 VCC+0.9 VCC+0.5 V Input high voltage, XTAL1, RST

Output low voltage, ports 1, 2,

Output low voltage, port 0, ALE, PSEN

Output high voltage (port 0 in external bus mode), ALE9, PSEN

8, 7

Logical 0 input current, ports 1, 2, 3 VIN = 0.4 V –1 –50 µA Logical 1-to-0 transition current, ports 1, 2, 3 Input leakage current, port 0 0.45 < VIN < VCC – 0.3 ±10 µA

Power supply current (see Figure 21): See note 5

Active mode @ 16 MHz µA Idle mode @ 16 MHz µA Power-down mode or clock stopped (see

Figure 25 for conditions)

RST

Internal reset pull-down resistor 40 225 kΩ Pin capacitance10 (except EA) 15 pF

NOTES:

1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V.

2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I single output sinks more than 5 mA and no more than two outputs exceed the test conditions.

3. Capacitive loading on ports 0 and 2 may cause the V address bits are stabilizing.

4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when V

5. See Figures 22 through 25 for I

Active mode: I Idle mode: I

6. This value applies to T

7. Load capacitance for port 0, ALE, and PSEN

8. Under steady state (non-transient) conditions, I

Maximum I Maximum I Maximum total I

exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed

If I

test conditions.

per port pin: 15 mA (*NOTE: This is 85°C specification.)

per 8-bit port: 26 mA

9. ALE is tested to V

10.Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF (except EA

is 25 pF).

is approximately 2 V.

= 0.9 × FREQ. + 1.1 mA

= 0.18 × FREQ. +1.01 mA; See Figure 21.

amb

for all outputs: 71 mA

, except when ALE is off then VOH is the voltage specification.

OH1

test conditions.

= 0°C to +70°C. For T

= 100 pF, load capacitance for all other outputs = 80 pF.

= –40°C to +85°C, ITL = –750 µA.

amb

must be externally limited as follows:

11.To improve noise rejection a nominal 100 ns glitch rejection circuitry has been added to the RST pin, and a nominal 15 ns glitch rejection circuitry has been added to the INT0

and INT1 pins. Previous devices provided only an inherent 5 ns of glitch rejection.

4.0 V < VCC < 5.5 V –0.5 0.2 VCC–0.1 V

2.7 V<VCC< 4.0 V –0.5 0.7 V

VCC = 2.7 V

IOL = 1.6 mA

VCC = 2.7 V

IOL = 3.2 mA

VCC = 2.7 V

IOH = –20 µA

VCC = 4.5 V

IOH = –30 µA

VCC = 2.7 V

IOH = –3.2 mA

on ALE and PSEN to momentarily fall below the VCC–0.7 specification when the

VIN = 2.0 V See note 4

= 0°C to 70°C 3 50 µA

amb

= –40°C to +85°C 75 µA

amb

80C51/87C51/80C52/87C52

LIMITS

MIN TYP

0.7 V

VCC – 0.7 V

s of ALE and ports 1 and 3. The noise is due

can exceed these conditions provided that no

VCC+0.5 V

MAX

0.4 V

–650 µA

2000 Aug 07

Page 23

Philips Semiconductors Product specification

SYMBOL

PARAMETER

UNIT

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

DC ELECTRICAL CHARACTERISTICS

= 0°C to +70°C or –40°C to +85°C, 33 MHz devices; 5 V ±10%; VSS = 0 V

amb

TEST

CONDITIONS

IH1

OL1

OH1

Input low voltage Input high voltage (ports 0, 1, 2, 3, EA) 0.2 VCC+0.9 VCC+0.5 V Input high voltage, XTAL1, RST

Output low voltage, ports 1, 2, 3

Output low voltage, port 0, ALE, PSEN

Output high voltage, ports 1, 2, 3 Output high voltage (port 0 in external bus

mode), ALE9, PSEN Logical 0 input current, ports 1, 2, 3 VIN = 0.4 V –1 –50 µA

Logical 1-to-0 transition current, ports 1, 2, 3

Input leakage current, port 0 0.45 < VIN < VCC – 0.3 ±10 µA Power supply current (see Figure 21): See note 5

Active mode (see Note 5) Idle mode (see Note 5) Power-down mode or clock stopped (see Fig-

ure 25 for conditions)

RST

Internal reset pull-down resistor 40 225 kΩ Pin capacitance10 (except EA) 15 pF

NOTES:

1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V.

2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I single output sinks more than 5mA and no more than two outputs exceed the test conditions.

3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC–0.7 specification when the address bits are stabilizing.

4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when V

5. See Figures 22 through 25 for I

Active mode: I Idle mode: I

6. This value applies to T

7. Load capacitance for port 0, ALE, and PSEN

8. Under steady state (non-transient) conditions, I

Maximum I Maximum I Maximum total I

exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed

If I

test conditions.

9. ALE is tested to V

10.Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF (except EA

per port pin: 15 mA (*NOTE: This is 85°C specification.)

per 8-bit port: 26 mA

OH1

is 25 pF).

11.To improve noise rejection a nominal 100 ns glitch rejection circuitry has been added to the RST pin, and a nominal 15 ns glitch rejection circuitry has been added to the INT0

is approximately 2 V.

CC(MAX) CC(MAX)

amb

for all outputs: 71 mA

test conditions.

= 0.9 × FREQ. + 1.1 mA = 0.18 × FREQ. +1.0 mA; See Figure 21.

= 0°C to +70°C. For T

7, 8

= –40°C to +85°C, ITL = –750 µA.

amb

= 100 pF, load capacitance for all other outputs = 80 pF.

must be externally limited as follows:

4.5 V < VCC < 5.5 V –0.5 0.2 VCC–0.1 V

VCC = 4.5 V

IOL = 1.6mA

VCC = 4.5 V

IOL = 3.2mA

VCC = 4.5 V

IOH = –30µA

VCC = 4.5 V

IOH = –3.2mA

VIN = 2.0 V

See note 4

= 0°C to 70°C 3 50 µA

amb

= –40°C to +85°C 75 µA

amb

, except when ALE is off then VOH is the voltage specification.

and INT1 pins. Previous devices provided only an inherent 5 ns of glitch rejection.

80C51/87C51/80C52/87C52

LIMITS

MIN TYP

0.7 V

VCC – 0.7 V

s of ALE and ports 1 and 3. The noise is due

can exceed these conditions provided that no

VCC+0.5 V

MAX

0.4 V

–650 µA

2000 Aug 07

Page 24

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

80C51/87C51/80C52/87C52

AC ELECTRICAL CHARACTERISTICS

= 0°C to +70°C or –40°C to +85°C, VCC = +2.7 V to +5.5 V, VSS = 0 V

amb

1, 2, 3

16 MHz CLOCK VARIABLE CLOCK

SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT

1/t

LHLL

AVLL

LLAX

LLIV

LLPL

PLPH

PLIV

PXIX

PXIZ

AVIV

PLAZ

CLCL

14 Oscillator frequency

Speed versions :S 14 ALE pulse width 85 2t 14 Address valid to ALE low 22 t 14 Address hold after ALE low 32 t 14 ALE low to valid instruction in 150 4t 14 ALE low to PSEN low 32 t 14 PSEN pulse width 142 3t 14 PSEN low to valid instruction in 82 3t 14 Input instruction hold after PSEN 0 0 ns 14 Input instruction float after PSEN 37 t

14 Address to valid instruction in 207 5t 14 PSEN low to address float 10 10 ns

3.5 16 MHz –40 ns

CLCL

–40 ns

CLCL

–30 ns

CLCL

–100 ns

CLCL

–30 ns

CLCL

–45 ns

CLCL

–105 ns

CLCL

–25 ns

CLCL

–105 ns

CLCL

Data Memory

RLRH

WLWH

RLDV

RHDX

RHDZ

LLDV

AVDV

LLWL

AVWL

QVWX

WHQX

QVWH

RLAZ

WHLH

15, 16 RD pulse width 275 6t 15, 16 WR pulse width 275 6t 15, 16 RD low to valid data in 147 5t

–100 ns

CLCL

–100 ns

CLCL

–165 ns

CLCL

15, 16 Data hold after RD 0 0 ns 15, 16 Data float after RD 65 2t 15, 16 ALE low to valid data in 350 8t 15, 16 Address to valid data in 397 9t 15, 16 ALE low to RD or WR low 137 239 3t 15, 16 Address valid to WR low or RD low 122 4t 15, 16 Data valid to WR transition 13 t 15, 16 Data hold after WR 13 t

16 Data valid to WR high 287 7t

–50 3t

CLCL

–130 ns

CLCL

–50 ns

CLCL

–50 ns

CLCL

–150 ns

CLCL

–60 ns

CLCL

–150 ns

CLCL

–165 ns

CLCL

+50 ns

CLCL

15, 16 RD low to address float 0 0 ns 15, 16 RD or WR high to ALE high 23 103 t

–40 t

CLCL

+40 ns

CLCL

External Clock

CHCX

CLCX

CLCH

CHCL

18 High time 20 20 t 18 Low time 20 20 t

CLCL–tCLCX

CLCL–tCHCX

ns 18 Rise time 20 20 ns 18 Fall time 20 20 ns

Shift Register

XLXL

QVXH

XHQX

XHDX

XHDV

17 Serial port clock cycle time 750 12t 17 Output data setup to clock rising edge 492 10t 17 Output data hold after clock rising edge 8 2t

CLCL

–133 ns

–117 ns

17 Input data hold after clock rising edge 0 0 ns 17 Clock rising edge to input data valid 492 10t

–133 ns

CLCL

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN

= 100 pF, load capacitance for all other outputs = 80 pF.

3. Interfacing the 87C51, 80C51, 87C52, or 80C52 to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to Port 0 drivers.

4. See application note AN457 for external memory interface.

5. Parts are guaranteed to operate down to 0 Hz. When an external clock source is used, the RST pin should be held high for a minimum of 20 µs for power-on or wakeup from power down.

2000 Aug 07

Page 25

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

80C51/87C51/80C52/87C52

AC ELECTRICAL CHARACTERISTICS

= 0°C to +70°C or –40°C to +85°C, VCC = 5 V ±10%, VSS = 0 V

amb

1, 2, 3

VARIABLE CLOCK

16 MHz to f

max

33 MHz CLOCK

SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT

LHLL

AVLL

LLAX

LLIV

LLPL

PLPH

PLIV

PXIX

PXIZ

AVIV

PLAZ

14 ALE pulse width 2t 14 Address valid to ALE low t 14 Address hold after ALE low t 14 ALE low to valid instruction in 4t 14 ALE low to PSEN low t 14 PSEN pulse width 3t 14 PSEN low to valid instruction in 3t

–40 21 ns

CLCL

–25 5 ns

CLCL

–25 ns

CLCL

–65 55 ns

CLCL

–25 5 ns

CLCL

–45 45 ns

CLCL

–60 30 ns

CLCL

14 Input instruction hold after PSEN 0 0 ns 14 Input instruction float after PSEN t 14 Address to valid instruction in 5t

–25 5 ns

CLCL

–80 70 ns

CLCL

14 PSEN low to address float 10 10 ns

Data Memory

RLRH

WLWH

RLDV

RHDX

RHDZ

LLDV

AVDV

LLWL

AVWL

QVWX

WHQX

QVWH

RLAZ

WHLH

15, 16 RD pulse width 6t 15, 16 WR pulse width 6t 15, 16 RD low to valid data in 5t

–100 82 ns

CLCL

–100 82 ns

CLCL

–90 60 ns

CLCL

15, 16 Data hold after RD 0 0 ns 15, 16 Data float after RD 2t 15, 16 ALE low to valid data in 8t 15, 16 Address to valid data in 9t 15, 16 ALE low to RD or WR low 3t 15, 16 Address valid to WR low or RD low 4t 15, 16 Data valid to WR transition t 15, 16 Data hold after WR t

16 Data valid to WR high 7t

–50 3t

CLCL

–75 45 ns

CLCL

–30 0 ns

CLCL

–25 5 ns

CLCL

–130 80 ns

CLCL

–28 32 ns

CLCL

–150 90 ns

CLCL

–165 105 ns

CLCL

+50 40 140 ns

CLCL

15, 16 RD low to address float 0 0 ns 15, 16 RD or WR high to ALE high t

–25 t

CLCL

+25 5 55 ns

CLCL

External Clock

CHCX

CLCX

CLCH

CHCL

18 High time 0.38t 18 Low time 0.38t

CLCL CLCL

CLCL–tCLCX

CLCL–tCHCX

18 Rise time 5 ns 18 Fall time 5 ns

ns ns

Shift Register

XLXL

QVXH

XHQX

XHDX

XHDV

17 Serial port clock cycle time 12t 17 Output data setup to clock rising edge 10t 17 Output data hold after clock rising edge 2t

CLCL CLCL

CLCL

–133 167 ns –80 ns

360 ns

17 Input data hold after clock rising edge 0 0 ns 17 Clock rising edge to input data valid 10t

–133 167 ns

CLCL

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN

= 100 pF, load capacitance for all other outputs = 80 pF.

3. Interfacing the 87C51, 80C51, 87C52 or 80C52 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers.

4. Variable clock is specified for oscillator frequencies greater than 16 MHz to 33 MHz. For frequencies equal or less than 16 MHz, see 16 MHz “AC Electrical Characteristics”, page 24.

5. Parts are guaranteed to operate down to 0 Hz. When an external clock source is used, the RST pin should be held high for a minimum of 20 µs for power-on or wakeup from power down.

2000 Aug 07

Page 26

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has five characters. The first character is always ‘t’ (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A – Address C – Clock D – Input data H – Logic level high I – Instruction (program memory contents) L – Logic level low, or ALE

ALE

LHLL

P – PSEN Q – Output data R–RD

signal t – Time V – Valid W– WR

signal X – No longer a valid logic level Z – Float Examples: t

80C51/87C51/80C52/87C52

= Time for address valid to ALE low.

AVLL

=Time for ALE low to PSEN low.

LLPL

ALE

PSEN

PORT 0

PORT 2

AVLL

LLPL

LLAX

A0–A7 A0–A7

AVIV

PLPH

LLIV

PLIV

PLAZ

PXIX

INSTR IN

A0–A15 A8–A15

PXIZ

Figure 14. External Program Memory Read Cycle

WHLH

LLDV

LLWL

RLRH

SU00006

PORT 0

PORT 2

2000 Aug 07

AVLL

LLAX

A0–A7

FROM RI OR DPL

AVWL

RLAZ

AVDV

P2.0–P2.7 OR A8–A15 FROM DPF A0–A15 FROM PCH

RLDV

RHDX

DATA IN A0–A7 FROM PCL INSTR IN

RHDZ

Figure 15. External Data Memory Read Cycle

SU00025

Page 27

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

ALE

PSEN

80C51/87C51/80C52/87C52

WHLH

PORT 0

PORT 2

INSTRUCTION

ALE

CLOCK

OUTPUT DATA

WRITE TO SBUF

INPUT DATA

CLEAR RI

WLWH

WHQX

QVWH

DATA OUT A0–A7 FROM PCL INSTR IN

SU00026

AVLL

LLAX

A0–A7

FROM RI OR DPL

AVWL

LLWL

QVWX

P2.0–P2.7 OR A8–A15 FROM DPF A0–A15 FROM PCH

Figure 16. External Data Memory Write Cycle

012345678

XLXL

QVXH

XHDV

VALID VALID VALID VALID VALID VALID VALID VALID

XHQX

1230 4567

XHDX

SET TI

SET RI

SU00027

Figure 17. Shift Register Mode Timing

2000 Aug 07

VCC–0.5

0.45V

0.7V

0.2VCC–0.1

CHCL

CLCX

CLCL

CHCX

CLCH

Figure 18. External Clock Drive

SU00009

Page 28

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

80C51/87C51/80C52/87C52

VCC–0.5

0.45V

NOTE:

AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.

Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’.

0.2V

CC CC

+0.9

–0.1

SU00717

Figure 19. AC Testing Input/Output

(mA)

481216

FREQ AT XTAL1 (MHz)

Figure 21. ICC vs. FREQ

Valid only within frequency specifications of the device under test

LOAD

NOTE: For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded V

OH/VOL

ICCMAX = 0.9 X FREQ. + 1.1

TYP ACTIVE MODE

MAX IDLE MODE

TYP IDLE MODE

20 24 28 32 36

+0.1V

LOAD

–0.1V

LOAD

level occurs. IOH/IOL ≥ ±20mA.

Figure 20. Float Waveform

MAX ACTIVE MODE

SU01413

TIMING

REFERENCE

POINTS

SU00718

–0.1V

+0.1V

2000 Aug 07

Page 29

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

80C51/87C51/80C52/87C52

RST

(NC)

CLOCK SIGNAL

XTAL2

XTAL1

Figure 22. ICC Test Condition, Active Mode

All other pins are disconnected

VCC–0.5

Figure 24. Clock Signal Waveform for ICC Tests in Active and Idle Modes

0.45V

SU00719

0.7V

0.2VCC–0.1

CHCL

CLCH

= t

CLCX

CHCL

CLCL

= 5ns

RST

(NC)

CLOCK SIGNAL

XTAL2

XTAL1 V

Figure 23. ICC Test Condition, Idle Mode

All other pins are disconnected

CHCX

CLCH

SU00009

SU00720

SU00016

(NC)

RST

XTAL2

XTAL1

Figure 25. ICC Test Condition, Power Down Mode

All other pins are disconnected. V

= 2 V to 5.5 V

2000 Aug 07

Page 30

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

80C51/87C51/80C52/87C52

EPROM CHARACTERISTICS

These devices can be programmed by using a modified Improved Quick-Pulse Programming algorithm. It differs from older methods in the value used for V width and number of the ALE/PROG

The family contains two signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as being manufactured by Philips.

Table 8 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the security bits. The circuit configuration and waveforms for quick-pulse programming are shown in Figures 26 and 27. Figure 28 shows the circuit configuration for normal program memory verification.

(programming supply voltage) and in the

pulses.

Quick-Pulse Programming

The setup for microcontroller quick-pulse programming is shown in Figure 26. Note that the device is running with a 4 to 6 MHz oscillator. The reason the oscillator needs to be running is that the device is executing internal address and program data transfers.

The address of the EPROM location to be programmed is applied to ports 1 and 2, as shown in Figure 26. The code byte to be programmed into that location is applied to port 0. RST, PSEN pins of ports 2 and 3 specified in Table 8 are held at the ‘Program Code Data’ levels indicated in Table 8. The ALE/PROG low 5 times as shown in Figure 27.

To program the encryption table, repeat the 5 pulse programming sequence for addresses 0 through 1FH, using the ‘Pgm Encryption Table’ levels. Do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data.

To program the security bits, repeat the 5 pulse programming sequence using the ‘Pgm Security Bit’ levels. After one security bit is programmed, further programming of the code memory and encryption table is disabled. However , the other security bits can still be programmed.

Note that the EA maximum specified V glitch above that voltage can cause permanent damage to the

/VPP pin must not be allowed to go above the

level for any amount of time. Even a narrow

and

is pulsed

device. The VPP source should be well regulated and free of glitches and overshoot.

Program Verification

If security bits 2 and 3 have not been programmed, the on-chip program memory can be read out for program verification. The address of the program memory locations to be read is applied to ports 1 and 2 as shown in Figure 28. The other pins are held at the ‘Verify Code Data’ levels indicated in Table 8. The contents of the address location will be emitted on port 0. External pull-ups are required on port 0 for this operation.

If the 64 byte encryption table has been programmed, the data presented at port 0 will be the exclusive NOR of the program byte with one of the encryption bytes. The user will have to know the encryption table contents in order to correctly decode the verification data. The encryption table itself cannot be read out.

Reading the Signature Bytes

The signature bytes are read by the same procedure as a normal verification of locations 030H and 031H, except that P3.6 and P3.7 need to be pulled to a logic low. The values are: (030H) = 15H indicates manufactured by Philips (031H) = 92H indicates 87C51

Program/Verify Algorithms

Any algorithm in agreement with the conditions listed in Table 8, and which satisfies the timing specifications, is suitable.

Security Bits

With none of the security bits programmed the code in the program memory can be verified. If the encryption table is programmed, the code will be encrypted when verified. When only security bit 1 (see Table 9) is programmed, MOVC instructions executed from external program memory are disabled from fetching code bytes from the internal memory , EA is latched on Reset and all further programming of the EPROM is disabled. When security bits 1 and 2 are programmed, in addition to the above, verify mode is disabled. When all three security bits are programmed, all of the conditions above apply and all external program memory execution is disabled.

Encryption Array

64 bytes of encryption array are initially unprogrammed (all 1s).

Table 8. EPROM Programming Modes

MODE RST PSEN ALE/PROG EA/V

Read signature 1 0 1 1 0 0 0 0 Program code data 1 0 0* V Verify code data 1 0 1 1 0 0 1 1 Pgm encryption table 1 0 0* V Pgm security bit 1 1 0 0* V Pgm security bit 2 1 0 0* V Pgm security bit 3 1 0 0* V

NOTES:

1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin. = 12.75 V ±0.25 V .

2. V

3. V

= 5 V±10% during programming and verification.

* ALE/PROG

12.75 V. Each programming pulse is low for 100 µs (±10 µs) and high for a minimum of 10 µs.

Trademark phrase of Intel Corporation.

2000 Aug 07

receives 5 programming pulses for code data (also for user array; 5 pulses for encryption or security bits) while VPP is held at

PP PP PP PP

P2.7 P2.6 P3.7 P3.6

1 0 1 1

1 0 1 0 1 1 1 1 1 1 0 0 0 1 0 1

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Philips Semiconductors Product specification

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

Table 9. Program Security Bits for EPROM Devices

PROGRAM LOCK BITS

SB1 SB2 SB3 PROTECTION DESCRIPTION

1 U U U No Program Security features enabled. (Code verify will still be encrypted by the Encryption Array if

2 P U U MOVC instructions executed from external program memory are disabled from fetching code bytes

3 P P U Same as 2, also verify is disabled. 4 P P P Same as 3, external execution is disabled. Internal data RAM is not accessible.

NOTES:

1. P – programmed. U – unprogrammed.

2. Any other combination of the security bits is not defined.

1, 2

programmed.)

from internal memory, EA is sampled and latched on Reset, and further programming of the EPROM is disabled.

80C51/87C51/80C52/87C52

+5V

ALE/PROG:

A0–A7

4–6MHz

12345

SEE EXPLODED VIEW BELOW

1 0

1 1 1

RST P3.6 P3.7

EPROM/OTP

XTAL2

XTAL1

Figure 26. Programming Configuration

5 PULSES

= 100µs±10µs

GLGH

Figure 27. PROG Waveform

ALE/PROG

PSEN

P2.7

P2.6

P2.0–P2.5

GHGL

PGM DATA

+12.75V 5 PULSES TO GROUND 0 1

A8–A12

SU00873

= 10µs MIN

SU00875

2000 Aug 07

Page 32

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

A0–A7

80C51/87C51/80C52/87C52

+5V

PGM DATA

1 1 1

4–6MHz

RST P3.6

P3.7

XTAL2

XTAL1

EPROM/OTP

ALE/PROG

PSEN

P2.7

P2.6

P2.0–P2.5

Figure 28. Program Verification

EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS

= 21°C to +27°C, VCC = 5 V±10%, VSS = 0 V (See Figure 29)

amb

SYMBOL

1/t

CLCL

AVGL

GHAX

DVGL

GHDX

EHSH

SHGL

GHSL

GLGH

AVQV

ELQZ

EHQZ

GHGL

NOTE:

1. Not tested.

Programming supply voltage 12.5 13.0 V Programming supply current 50 Oscillator frequency 4 6 MHz Address setup to PROG low 48t Address hold after PROG 48t Data setup to PROG low 48t Data hold after PROG 48t P2.7 (ENABLE) high to V VPP setup to PROG low 10 µs VPP hold after PROG 10 µs PROG width 90 110 µs Address to data valid 48t ENABLE low to data valid 48t Data float after ENABLE 0 48t PROG high to PROG low 10 µs

PARAMETER MIN MAX UNIT

1 1 0 0 ENABLE

A8–A12

SU00839

CLCL CLCL CLCL CLCL

48t

CLCL

CLCL CLCL CLCL

2000 Aug 07

Page 33

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

PROGRAMMING* VERIFICATION*

P1.0–P1.7 P2.0–P2.5

P3.4

(A0 – A12)

ADDRESS ADDRESS

80C51/87C51/80C52/87C52

AVQV

PORT 0

P0.0 – P0.7

(D0 – D7)

DVGL

ALE/PROG

EA/V

P2.7

AVGL

EHSH

GLGH

SHGL

NOTES:

FOR PROGRAMMING CONFIGURATION SEE FIGURE 26.

FOR VERIFICATION CONDITIONS SEE FIGURE 28.

** SEE TABLE 8.

DATA IN DATA OUT

GHDX

GHAX

GHGL

LOGIC 0

GHSL

LOGIC 1 LOGIC 1

ELQV

Figure 29. EPROM Programming and Verification

EHQZ

SU01414

MASK ROM DEVICES

Security Bits

from the internal memory, EA programming of the EPROM is disabled. When security bits 1 and 2 are programmed, in addition to the above, verify mode is disabled.

Encryption Array

64 bytes of encryption array are initially unprogrammed (all 1s).

is latched on Reset and all further

Table 10. Program Security Bits

PROGRAM LOCK BITS

SB1 SB2 PROTECTION DESCRIPTION

1 U U No Program Security features enabled.

2 P U MOVC instructions executed from external program memory are disabled from fetching code bytes from

NOTES:

1. P – programmed. U – unprogrammed.

2. Any other combination of the security bits is not defined.

1, 2

(Code verify will still be encrypted by the Encryption Array if programmed.)

internal memory, EA is sampled and latched on Reset, and further programming of the EPROM is disabled.

2000 Aug 07

Page 34

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

80C51 ROM CODE SUBMISSION

When submitting ROM code for the 80C51, the following must be specified:

1. 4k byte user ROM data

2. 64 byte ROM encryption key

3. ROM security bits.

80C51/87C51/80C52/87C52

ADDRESS

0000H to 0FFFH DATA 7:0 User ROM Data 1000H to 103FH KEY 7:0 ROM Encryption Key 1040H SEC 0 ROM Security Bit 1 1040H SEC 1 ROM Security Bit 2

Security Bit 1: When programmed, this bit has two effects on masked ROM parts:

1. External MOVC is disabled, and

2. EA

is latched on Reset.

Security Bit 2: When programmed, this bit inhibits Verify User ROM. NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled.

If the ROM Code file does not include the options, the following information must be included with the ROM code. For each of the following, check the appropriate box, and send to Philips along with the code:

Security Bit #1: Security Bit #2: Encryption:

V Enabled V Disabled V Enabled V Disabled V No V Yes If Yes, must send key file.

CONTENT BIT(S) COMMENT

80C52 ROM CODE SUBMISSION

When submitting ROM code for the 80C52, the following must be specified:

1. 8k byte user ROM data

2. 64 byte ROM encryption key

3. ROM security bits.

ADDRESS

0000H to 1FFFH DATA 7:0 User ROM Data 2000H to 203FH KEY 7:0 ROM Encryption Key 2040H SEC 0 ROM Security Bit 1 2040H SEC 1 ROM Security Bit 2

Security Bit 1: When programmed, this bit has two effects on masked ROM parts:

1. External MOVC is disabled, and

2. EA

is latched on Reset.

Security Bit 2: When programmed, this bit inhibits Verify User ROM. NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled.

Security Bit #1: Security Bit #2: Encryption:

2000 Aug 07

V Enabled V Disabled V Enabled V Disabled V No V Yes If Yes, must send key file.

CONTENT BIT(S) COMMENT

Page 35

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1

80C51/87C51/80C52/87C52

2000 Aug 07

Page 36

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

PLCC44: plastic leaded chip carrier; 44 leads SOT187-2

80C51/87C51/80C52/87C52

2000 Aug 07

Page 37

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2

80C51/87C51/80C52/87C52

2000 Aug 07

Page 38

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

Data sheet status

Objective specification

Preliminary specification

Product specification

Product status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

[1]

80C51/87C51/80C52/87C52

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381

 Copyright Philips Electronics North America Corporation 2000

Date of release: 08-00

Document order number: 9397 750 07404

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2000 Aug 07