Datasheet 78Q8392L-CP, 78Q8392L-28CH Datasheet (TDK Semiconductor Corporation)

78Q8392L

Low Power Ethernet

Coaxial Transceiver

February 1998

DESCRIPTION

The 78Q8392L Ethernet Transceiver is a low power
BiCMOS coax line transmitter/receiver. The device
includes analog transmit and receive buffers, a 10
MHz on-board oscillator, timing logic for jabber and
heartbeat functions, output drivers and bandgap
reference, in addition to a current reference and
collision detector.

This transceiver provides the interface between the
single-ended coaxial cable signals and the
Manchester-encoded differential logic signals.
Primary functional blocks include the receiver,
transmitter, collision detection and jabber timer. This
IC may be used in either internal or external MAU
environments.

The 78Q8392L is available in 16-pin plastic and 28­pin PLCC packages.

CONNECT DIAGRAM

FEATURES

• Very low power consumption

• Compliant with Ethernet II, IEEE 802.3

10Base5 and 10Base2

• Integrates all transceiver functions except

signal and power isolation

• Innovative design minimizes external

components count and power consumption

• Jabber timer function integrated on chip

• Externally selectable CED heartbeat allows

operation with IEEE 802.3 compatible
repeaters

• Squelch circuitry at all inputs rejects noise

• Power-on reset and test modes

• Advanced BiCMOS process

510 ±5%

COLLISION

SIGNAL
TO DTE

DATA TO

DTE

DATA FROM

DTE

x 4

78

–9V

41

CD+

2

CD–

3

RX+

6

RX–

7

TX+

8

TX-

VEE

VEE

VEE

CDS

TXO

RXI

GND

HBE

RR-

RR+

5

13
16

15
14

10

9

12

11

COAX

78Q8392L
Low Power Ethernet
Coaxial Transceiver

FUNCTIONAL DESCRIPTION

The 78Q8392L incorporates six basic functions of
the Ethernet Transceiver, including receiving,
transmitting, collision signaling, collision detection,
jabber timing, and the heartbeat function. Refer to
Figure 1 for a general system block diagram.

RECEIVER FUNCTIONS

The receiver senses signals through the RXI input,
which minimizes reflections on the transmission
media using a low capacitance, high resistance input
buffer amplifier. The CDS ground input attaches
directly to the input buffer from the coaxial shield to
eliminate ground loop noise.

In addition to the input buffer, the receiver data path
consists of an equalizer, data slicer, receiver squelch
circuitry, and an output line driver.

The equalizer improves the cable-induced jitter; the
data slicer restores equalized received signals to fast
transition signals with binary levels to drive the
receiver line driver; and the receiver line driver dr ives
the AUI cable through an isolation transformer that
connects to the AUI interface.

Noise on the transmission media is rejected by the
receiver squelch circuitry, which determines valid
data via three criteria: Average DC level, pulse width
and transition period. The DC voltage level is
detected and compared to a set level in the receiver
comparator circuit. The pulse width must be greater
than 20 ns to pass the narrow pulse filter; the
transition timer outputs a true level on the RX Data
Valid line provided the time between transitions is
less than about 200 ns. As long as a valid RXI signal
is detected, the output line driver remains enabled.
The transition timer disables the line driver when
there are no further transitions on the data medium,
and the RX+, RX- pins go to a zero differential
voltage state (Figure 3).

TRANSMITTER FUNCTIONS

The transmitter data path consists of a transmit input
buffer, pulse-shaping filter, transmit squelch
circuitry and transmit output line driver. The
self-biasing transmit input buffer receives data
through an isolation transformer and translates the
AUI differential analog signal to square pulse suitable
for driving the pulse shaping filter.

The filter outputs a correctly shaped and bandlimited
signal to the transmit output driver, which drives the
transmission medium through a high impedance
current source. When the transmitter is off, the
capacitance of the transmit driver is isolated from the
transmission media by an external diode with a low
capacitance node. The shield of the transmission
media serves as the ground return for the transmitter
function.

A transmit squelch circuit, which consists of a pulse
threshold detector, a pulse width detector, and a
pulse duration timer, is used to suppress noise, as
well as crosstalk on the AUI cable. The squelch
circuitry disables the transmit driver if the signal at
TX+ or TX- is smaller than the pulse threshold. Pulse
noise is rejected by a pulse width detector that
passes only pulses with durations greater than 20 ns.
The pulse duration timer disables the transmit driver
if no pulses are received for two-bit periods following
valid pulses. At the end of a transmission, the pulse
duration timer disables the transmitter and triggers

the blanking timer, used to block “dribble” bits.

COLLISION DETECTION

A collision occurs when two or more transmitters
simultaneously transmit on the transmission media. A
collision is detected by comparing the average DC
level of the transmission media to a collision
threshold. The received signal at RXI is buffered and
sent through a low pass filter, then compared in the
collision threshold circuit. If the average DC level
exceeds a collision threshold, a 10 MHz signal is
output on the CD± pins.

COLLISION SIGNALING

When collision signaling is enabled, a 10 MHz signal
is sent from the CD± pins through an isolation
transformer to the DTE. When the function is
disabled, this output goes to a zero differential state.
The 10 MHz output from the CD pins indicates a
collision on the transmission media, a heartbeat
function, or that the transmitter is in jabber mode.

2

78Q8392L

Low Power Ethernet

Coaxial Transceiver

JABBER FUNCTION

When valid data on the TX± pins detected, the jabber
timer is started. If there is valid data for more than 20
ns, a latch is set which disables the transmitter
output and enables the 10 MHz output on the CD±
pins. The latch is reset within 0.5 seconds after the
valid data is removed from the transmitter input
(TX±). This action resets the jabber timer and
disables the 10 MHz CD output. The TX± inputs
must remain inactive during the 0.5 second reset
period.

DATA MEDIA

RECEIVER

INPUT

RXI

CDS

TXO

BUFFER

TRANSMIT

OUTPUT DRIVER

TX ON

EQUALIZER

LP FILTER

COLLISION

THRESHOLD

COMPARATOR

SQUELSH

THRESHOLD

CONTROL LOGIC

SLICER

SQUELCH

COLLISION

COMPARATOR

HEARTBEAT FUNCTION

The 10 MHz CD outputs are enabled for about 1 µs
at approximately 1.1 µs after the end of each
transmission. The heartbeat signal tells the DTE that
the circuit is functioning. This is implemented by
starting the heartbeat timer when the valid data
signal indicates the end of a transmission. This
function is disabled when HBE pin is tied to V

RX+
RX-

RX DATA

TRANSITION

PERIOD
TAMER

VALID

SLICER

ENABLE

BUFFERED TX

TRANSMIT INPUT

BUFFER

TX DISABLE

NARROW

PULSE
FILTER

PULSE

SHAPING

FILTER

EE.

TX+
TX-

JABBER TIMER

BLANKING TIMER

HEART BEAT TIMER

TX DATA VALID

END TRANSMIT

TX± DISABLE

CD ± ON

TRANSITION

PERIOD

TIMER

TRANSITION

END

TIMER

10 MHz

OSC

NARROW

PULSE
FILTER

TX ± > -250 mV

TX ± < -250 mV

AND CURRENT

FIGURE 1: 78Q8392L General System Block Diagram

3

BANDGAP

REFERENCE
REFERENCE

COMPARATOR

SIGNAL
PRESET
DETECT

ENABLE

CD+
CD-

RR+
RR-

78Q8392L
Low Power Ethernet
Coaxial Transceiver

PIN DESCRIPTION

NAME TYPE DESCRIPTION

CD+*/CD- O Collision Output. Balanced differential line driver outputs from the collision detect

circuitry. The 10 MHz signal from the internal oscillator is transferred to these outputs
in the event of collision, excessive transmission (jabber), or during CD Heartbeat
condition. These outputs are open emitters; pulldown resistors to VEE are required.
When operating into a 78Ω transmission line, these resistors should be 510Ω. In

Cheapernet applications, where the 78Ω drop cable is not used, higher resistor
values (up to 1.5k) may be used to save power.

RX+*/RX- O Receive Output. Balanced differential line driver outputs from the Receiver. These

outputs also require 510Ω pulldown resistors.

TX+*/TX- I Transmit Input. Balanced differential line receiver inputs to the Transmitter. The

common mode voltage for these inputs is determined internally and must not be
externally established. Signals meeting Transmitter squelch requirements are
waveshaped and output at TXO.

HBE I Heartbeat Enable. This input enables CD Heartbeat when grounded or left opened,

disables it when connected to VEE.

RR+/RR- I

RXI I Receive Input. Connects directly to the coaxial cable. Signals meeting Receiver

TXO O Transmit Output. Connects via an isolation diode to the coaxial cable.
CDS I Collision Detect Sense. Ground sense connection for the collision detect circuit. This

GND S Positive Supply Pin.
VEE S Negative Supply Pins. These pins should be connected to a large metal frame area

*IEEE names for CD± = CI±, RX± = DI±, TX± = DO±
Notes: Pin type: I-input; O-output; S-power supply

External Resistor. A fixed 1 kΩ 1% resistor connected between these pins
establishes internal operating currents.

squelch requirements are equalized for inter-symbol distortion, amplified, and output
at RX+ and RX- pin.

pin should be connected separately to the shield to avoid ground dr ops from altering
the receive mode collision threshold.

on the PC board to handle heat dissipation, and bypassed to the GND pin with a 0.1
µF capacitor as close to the package as possible.

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78Q8392L

Low Power Ethernet

Coaxial Transceiver

ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

Absolute maximum ratings indicate limits beyond which permanent damage may occur. Continuous operation at
these limits is not recommended; operations should be limited to those conditions specified under recommended
operating characteristics.

PARAMETER RATING

Supply Voltage -10V
Input Voltage 0 to VEE
Storage Temperature

-65 to 150°C
Soldering (Reflow or Dip)
Package power dissipation

DC OPERATING CHARACTERISTICS

0°C ≤ T (ambient) ≤ +70°C, VEE = -9V ± 5%

PARAMETER

I

EE1

V

EE

I

EE2

I

RXI

Supply current out of

pin - non-transmitting

Supply current out of

pin - transmitting

V

EE

Receive input bias

CONDITION MIN NOM MAX UNIT

See Note 3 -2 +25 µA

current (RXI)

I

TDC

Transmit output dc

See Note 4 374145 mA

current level (TXO)

I

TAC

Transmit output ac

See Notes 4 & 5 ±28 I

current level (TXO)

V

CD

Collision threshold

See Note 9 -1.58 -1.52 -1.404 V

(Receive mode)

V

OD

Differential output voltage

See Notes 3 & 7 ±550 ±1200 mV

(RX±, CD±)

V

OC

Common mode output

See Note 3, 6 & 7 -3.0 -2.5 -2.0 V

voltage (RX±, CD±)

V

OB

Differential output voltage

See Notes 3, 7 & 8 ±40 mV

imbalance (RX±, CD±)

V

TS

Transmitter squelch

threshold (TX±)

C

X

R

RXI

Input capacitance (RXI)

Shunt resistance –

See Note 3 100 150

non-transmitting (RXI)

R

TXO

Shunt resistance –

See Note 4 200

transmitting (TXO)

235°C for 10 sec

1.0 watts @ 25°C

-340 -260 -200 mV

68mA

50 65 mA

TDC

mA

1.2 pF
kΩ

kΩ

5

78Q8392L
Low Power Ethernet
Coaxial Transceiver

DC OPERATING CHARACTERISTICS

(continued)

NOTES

1. Currents into device pins are positive, currents
out of device pins are negative. If not
specified, voltages are referenced to ground.

2. All typicals are for VEE = -9V, Ta = 25°C.

3. -8.55V > VEE > -9.45V.

4. The voltage on TXO is -4V < V(TXO) < 0.0V.

5. The AC current measurement is referenced to
the DC current level.

GND

RX+

or

CD+

ETHERNET

XCVR

RX-

or

CD-

V

EE

510Ω ±5%

510Ω ±5%

6. Operating or idle state.

7. Test load as shown in Figure 2.

8. Device measurement taken in idle state.

9. This threshold can be determined by

monitoring the CD± output with a DC level in
RXI.

+

V

OC

-

50 µH ±1%

78 ±1%

+

V

OB

-

V

+

OD

-

= VCOM

V

EE

FIGURE 2: Test Load for CD± or RX±

6

78Q8392L

Low Power Ethernet

Coaxial Transceiver

AC OPERATING CHARACTERISTICS

0°C < T(ambient) < +70°C, VEE = 9V ± 5%

PARAMETER CONDITION MIN NOM MAX UNIT

t

RON

t

Rd

t

Rr

tRfDifferential outputs fall time

tRJReceiver & cable total jitter
t

TST

t

Td

t

Tr

t

Tf

t

TM

t

TON

t

TOFF

t

CON

t

COFF

f

CD

t

CP

t

HON

t

HW

t

JA

t

JR

t

RO

Receiver startup delay

(RXI to RX±)

Receiver propagation delay

(RXI to RX±)

Differential outputs rise time

(RX± , CD±)

(RX± , CD±)

Transmitter startup delay

(TX± to TXO)

Transmitter propagation

delay (TX± to TXO)

Transmitter rise time –

10% to 90% (TXO)

Transmitter fall time-

90% to 10% (TXO)
tTr and tTf mismatch

Transmit turn-on pulse

width at V

(TX±)

TS

Transmit turn-off pulse

width at V

(TX±)

TS

Collision turn-on delay
Collision turn-off delay

Collision frequency (CD±)

Collision pulse width (CD±)

CD Heartbeat delay

(TX± to CD±)

CD Heartbeat duration

(CD±)

Jabber activation delay

(TX± to TXO off and CD±)

Jabber reset unjab time

(TX± to TXO and CD±)

Receive Off Pulse Width

(RX+ to RX-)

400 500 ns

10 50 ns

45ns

45ns

24ns

100 200 ns

35 50 ns

20 25 30 ns

20 25 30 ns

0.5 2 ns

82030ns

140 160 180 ns

700 900 ns

2000 ns

8.5 10 11.5 MHz
40 60 ns

0.6 1.0 1.6 µs

0.6 1.0 1.5

µs

20 60 ms

250 500 650 ms

200 ns

7

78Q8392L
Low Power Ethernet
Coaxial Transceiver

ELECTRICAL SPECIFICATIONS (continued)

TRANSMIT SPECIFICATIONS

The first bit transmitted from TXO may have data and
phase violations. The second through last bit reproduce

the TX± signal with less than or equal to the specified
jitter.

There is no logical signal inversion between Tx± and TXO
output. A low level from TX+ to TX- results in more
current flowing from the coaxial cable into the TXO pin.

At the end of transmission, when the transmitter
changes from the enabled state to the idle state, no
spurious pulses are generated, i.e., the transition on
TXO proceeds monotonically to zero current.

RXI

t

RON

RECEIVE SPECIFICATIONS

The first bit sent from RX± may have data and phase
violations. The second through last bit reproduce the
received signal with less than or equal to the specified
jitter.

There is no logical signal inversion between the RXI
input and the RX± output. A high level at RXI produces
a positive differential voltage from RX+ to RX-.

50%

t

Rd

t

RO

RX±

TX±

TXO

50%

1st BIT

FIGURE 3: Receiver Timing

50%

V

TS

t

TON

t

TST

90%

10%

t

TF

50%

90%
10%

t

Rr

t

Rf

V

TS

90%

t

TOFF

10%

t

Tr

t

Td

FIGURE 4: Transmitter Timing

8

78Q8392L

Low Power Ethernet

Coaxial Transceiver

RXI

CD±

TX±

INPUT STEP

FUNCTION

V

CD

(MAX)

R = 1K

C = 150 pF

t

CON

RXI

RC NETWORK
SIMULATES WORST CASE
CABLE STEP RESPONSE

V

1

f

CD

CD

FIGURE 5: Collision Timing

78Q8392L

COLLISION

DETECTOR

(MIN)

t

t

CP

CD±

OUTPUT

COFF

CD±

TXO

CD±

TX±

t

HON

FIGURE 6: Heartbeat Timing

t

JA

FIGURE 7: Jabber Timing

t

HW

t

JR

9

78Q8392L
Low Power Ethernet
Coaxial Transceiver

INPUT SIGNAL WITH

30 NSEC RISE AND

FALL TIMES

R = 1K

RXI

C = 36 pF

RC NETWORK SIMULATES

WORST CASE CABLE JITTER

Input jitter <= ±1 nsec
RX± Output jitter <= ± 7 nsec

±t

RJ

Difference <= ± 6 nsec

FIGURE 8: Receive Jitter Timing

78Q8392L
RECEIVER

RX±

OUTPUT

TRANSMIT
OUTPUT
(TXO) 25

FIGURE 9: Test Loads TXO

10

Ω

78Q8392L

Low Power Ethernet

Coaxial Transceiver

10 MHz

1:1

39Ω ±1%

V

TS

39Ω ±1%

FIGURE 10: Test Circuit for TX± Input

TX+

78Q8392L

TX-

GND

11

78Q8392L
Low Power Ethernet
Coaxial Transceiver

PACKAGE PIN DESIGNATIONS

(Top View)

1

CD+

2

CD-

3

RX+

4

VEE

VEE

RX-

TX+

78Q8392L

5 12 RR-

6

7

89TX- HBE

16-Pin DIP 28-Pin PLCC

16

15

14

13

11

10

CDS

TXO

RXI

VEE

RR+

GND

CAUTION: Use handling procedures necessary
for a static sensitive component.

CD-

RX+

5

VEE

6

VEE

7

VEE

VEE

8

9

VEE

10

VEE

11 19

VEE

12 13 14 15 16 17 18

RX-

CD+

CDS

1234 282726

78Q8392L

TX-

TX+

HBE

TXO

GND

N/C

GND

RXI

25
24

23

22

21

20

RR+

VEE
VEE

VEE

VEE

VEE

VEE

RR-

ORDERING INFORMATION

PART DESCRIPTION ORDER NUMBER PACKAGE MARK

78Q8392L 16-Pin Plastic DIP 78Q8392L-CP 78Q8392L-CP
78Q8392L 28-Pin Plastic PLCC 78Q8392L-28CH 78Q8392L-28CH

No responsibility is assumed by TDK Semiconduct or Corporation for use of this product nor f or any infringements of pat ents and trademarks
or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of TDK
Semiconductor Corporation and the c ompany reserves the right t o make changes in specific ations at any time wi thout notice. A ccordingly,
the reader is cautioned to verif y that you are referencing the mos t current data sheet before plac ing orders. To do so, see our web site at
http://www.tsc.tdk.com or contac t your local TDK Semiconduc tor representative.

TDK Semiconductor Corp., 2642 Michelle Dr., Tustin, CA 92780, [phone], FAX [phone], http://www.tsc.tdk.com

TDK Semiconductor Corporation 02/03/98 - rev.B

12