Datasheet 7809LPRPFK, 7809LPRPFI, 7809LPRPFH, 7809LPRPFE Datasheet (MAXWELL)

16-Bit Latchup Protected

Analog to Digital Converter

R/C CS POWER DOWN

7809LP

20 k

Ω

R1

IN

10 k

Ω

R2

IN

5 k

Ω

R3

IN

CAP

REF

20 k

Ω

FEATURES:

•RAD-PAK® radiation-hardened against natural space radia-
tion

• Total dose hardness:

- > 100 krad (Si), depending upon space mission

• Latch-up Protection Technology (LPT

• SEL converted into a reset

- Rate based on cross section and mission

• Same footprint as ADS7809

• Package: 24 pin R

AD-PAK flat package

• 100 kHz min sampling rate

• ±10 V and 0 V to 5 V input range

• Advanced CMOS technology

• DNL: 15-bits “No Missing Codes”

• 83 dB min SINAD with 20 kHz input

• Single +5 V supply operation

• Utilizes internal or external reference

• Serial output

• Power dissipation: 132 mW max

TM

)

Buffer

Successive Approximation Register and Control Logic

CDAC

Comparator

Internal

4 k

Ω

+2.5V Ref.

Clock

Serial Data

Out

Logic Diagram

DESCRIPTION:

Maxwell Technologies’ 7809LP high-speed 16-bit analog to
digital converter features a greater than 100 kilorad (Si) total
dose tolerance depending upon space mission. Using Max­well’s radiation-hardened R
7809LP has the same footprint as ADS7809 and is latchup
protected by Maxwell Technologies’ Latchup Protection Tech­nology (LPT

TM

). It is a 24 pin, 16-bit sampling analog-to-digital
converter using state-of-the-art CMOS structures. The
7809LP contains a 16-bit capacitor based SAR A/D with S/H,
reference, clock, interface for microprocessor use, and serial
output drivers. The 7809LP is specified at a 100kHz sampling
rate, and guaranteed over the full temperature range. Laser­trimmed scaling resistors provide various input ranges include
±10 V and 0 to 5 V, while the innovative design allows opera­tion from a single +5 V supply, with power dissipation of under
132 mW.

Maxwell Technologies' patented R
ogy incorporates radiation shielding in the microcircuit pack­age. It eliminates the need for box shielding while providing
the required radiation shielding for a lifetime in orbit or space
mission. In a GEO orbit, R
krad (Si) radiation dose tolerance. This product is available
with screening up to Class K.

AD-PAK® packaging technology, the

AD-PAK packaging technol-

AD-PAK provides greater than 100

BUSY

Data
Clock

Serial
Data

Memory

1000585

[phone]- Fax: [phone] - www.maxwell.com

12.19.01 Rev 3

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

1

16-Bit Latchup Protected Analog to Digital Converter

TABLE 1. 7809LP PIN DESCRIPTION

PIN SYMBOL DESCRIPTION

1 R1IN Analog Input.

2 AGND1 Analog Ground. Used internally as ground reference point.

3 R2IN Analog Input.

4 R3IN Analog Input.

5 CAP Reference Buffer Capacitor. 2.2 µF tantalum to ground.

6 REF Reference Input/Output. 2.2 µF tantalum capacitor to ground.

7 AGND2 Analog Ground.

8 SB/BTC

9 EXT/INT Select External or Internal Clock for transmitting data. If HIGH, data will be output synchronized

Select Straight Binary or Binary Two’s Complement data output format. If HIGH, data will be
output in a Straight Binary format. If LOW, data will be output in a Binary Two’s Complement
format.

to the clock input on DATACLK. If LOW, a convert command will initiate the transmission of the
data from the previous conversion, along with 16 clock pulses output on DATACLK.

7809LP

Memory

10 DGND Digital Ground.

11 LPBIT Built In test function of the latchup protection. Drive LOW during normal operation.

12 LPSTATUS Latchup Protection Status Output. LPSTATUS when HIGH indicates latchup protection is

active and output data is invalid.

13 VANA Analog Supply Input. Nominally 5V.

14 VDIG Digital Supply Input. Nominally 5V.

15 SYNC Sync Output. If EXT/INT is HIGH, either a rising edge on R/C

CS

with R/C HIGH will output a pulse on SYNC synchronized to the external DATACLK.

16 DATACLK Either an input or an output depending on the EXT/INT level. Output data will be synchronized

to this clock. If EXT/INT is LOW, DATACLK will transmit 16 pulses after each conversion, and
then remain LOW between conversions.

17 DATA Serial Data Output. Data will be synchronized to DATACLK, with the format determined by the

level of SB/BTC
level input of TAG as long as CS
on both the rising and falling edges of DATACLK, and between conversions DATA will stay at
the level of the TAG input when the conversion was started.

18 TAG Tag input for use in external clock mode. If EXT/INT is HIGH, the digital data input on TAG will

be output on DATA with a delay of 16 DATACLK pulses as long as C
HIGH.

19 R/C

20 CS

Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the
hold state and starts a conversion. When EXT/INT is LOW, this also initiates the transmission
of the data results from the previous conversion. If EXT/INT is HIGH, a rising edge on R/C
C

S LOW, or a falling edge on CS with R/C HIGH, transmits a pulse on SYNC and initiates the

transmission of data from the previous conversion.

Chip Select. Internally OR’ed with R/C.

. In the external clock mode, after 16-bits of data, the 7809LOPO will output the

is LOW and R/C is HIGH. If EXT/INT is LOW, data will be valid

with CS LOW or a falling edge on

S is LOW and R/C is

with

1000585

12.19.01 Rev 3

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

2

16-Bit Latchup Protected Analog to Digital Converter

7809LP

TABLE 1. 7809LP PIN DESCRIPTION

PIN SYMBOL DESCRIPTION

21 BUSY Busy Output. Falls when a conversion is started, and remains LOW until the conversion is com-

pleted and the data is latched into the output shift register. CS
BUSY

rises, or another conversion will start without time for signal acquisition.

or R/C must be HIGH when

22 PWRD Power Down Input. If HIGH, conversions are inhibited and power consumption is significantly

reduced. Results from the previous conversions are maintained in the output shift register.

23 LPVANA Latchup Protection Analog Supply.

24 LPVDIG Latchup Protection Digital Supply.

TABLE 2. 7809LP ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL MIN MAX UNIT

Analog Inputs R1

R2
R3
CAP

REF

IN

IN

IN

1

-25

-25

-25

V

+ 0.3

ANA

25
25
25

AGND2 - 0.3

Ground Voltage Differences: DGND, AGND2 -0.3 0.3 V

V

ANA

V

DIG

V

to V

DIG

ANA

-- 7 V

7V

-- 0.3 V

Specified Performance -40 85

Digital Inputs -0.3 V

Storage Temperature T

1. Indefinite short to AGND2, momentarily short to V

ANA

.

STG

-65 150

+ 0.3 V

DIG

TABLE 3. 7809LP DC ACCURACY SPECIFICATIONS

(SPECIFIED PERFORMANCE -40 TO +85°C)

P

ARAMETER MIN TYP MAX UNIT

Integral Linearity Error

-40 to 85°C

Differential Linearity Error

-40 to 85°C

No Missing Codes

Transition Noise

Full Scale Error

Full Scale Error

2

3

4,5

4,5

(using ext. 2.5000 V

)--±0.6%

ref

Full Scale Error Drift -- ±7 -- ppm/

--

--

--

--

--

--

--

--

±3
±5

-2, 3

-1, 6

LSB

15 -- -- Bits

-- 1.3 -- LSB

-- -- ±0.6 %

V
V
V
V

°

C

°

C

LSB
LSB

Memory

1

°

C

1000585

12.19.01 Rev 3

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

3

16-Bit Latchup Protected Analog to Digital Converter

7809LP

TABLE 3. 7809LP DC ACCURACY SPECIFICATIONS

(SPECIFIED PERFORMANCE -40 TO +85°C)

P

ARAMETER MIN TYP MAX UNIT

Full Scale Error Drift (using ext. 2.5000 V

Bipolar Zero Error

4

Bipolar Zero Error Drift -- ±2 -- ppm/

Unipolar Zero Error

4

-40 to 85°C

Unipolar Zero Error Drift -- ±2 -- ppm/

Recovery to Rated Accuracy after Power Down (1 uF Capacitor to

) -- ±2 -- ppm/°C

ref

-- -- ±10 mV

--

--

--

--

±3

±16

-- 1 -- ms

mV
mV

°

C

°

C

CAP)

Power Supply Sensitivity (V

-40 to 85°C

DIG

= V

= VD) 4.75 V > VD < 5.2 V

ANA

--

--

--

--

±8

±32

LSB
LSB

1. LSB stands for Least Significant Bit. One LSB is equal to 305 µV.

2. Not tested.

3. Typical rms noise at worst case transitions and temperatures.

4. Measured with various fixed resistors.

5. For bipolar input ranges, full scale error is the worst case of -Full Scale or +Full Scale untrimmed deviation from ideal first and
last scale code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset
error. For unipolar input ranges, full scale error is the deviation of the last code transition divided by the transition voltage. It
also includes the effect of offset error.

Memory

TABLE 4. 7809LP DIGITAL INPUTS

(SPECIFIED PERFORMANCE -40 TO +85°C)

P

ARAMETER MIN TYP MAX UNIT

V

IL

V

IH

IIL, I

IH

-0.3

2.0

--

--

--

--

V

0.8
+ 0.3

D

±10

TABLE 5. 7809LP ANALOG INPUT AND THROUGHPUT SPEED

(SPECIFIED PERFORMANCE -40 TO +85°C)

P

ARAMETER MIN TYP MAX UNIT

Voltage Ranges 10 V, 0 V to 5 V

Impedance

Capacitance -- 35 -- pF

Conversion Time -- 7.6 8 µs

Complete Cycle (Acquire and Convert) -- -- 10 µs

Throughput Rate

1

100 -- -- kHz

1. Tested by application of signal.

See Table 2.

V
V

µA

1000585

12.19.01 Rev 3

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

4

16-Bit Latchup Protected Analog to Digital Converter

7809LP

TABLE 6. 7809LP AC ACCURACY SPECIFICATIONS

(SPECIFIED PERFORMANCE -40 TO +85°C)

P

ARAMETER MIN TYP MAX UNIT

Spurious-Free Dynamic Range, fIN = 20 kHz

Total Harmonic Distortion, f

= 20 kHz

IN

Signal-to-Noise (Noise + Distortion)

1

1

fIN = 20 kHz

-60 dB Input

1

Signal-to-Noise

Full-Power Bandwidth

, fIN = 20 kHz 83 88 -- dB

1,3

1

90 100 -- dB

-- -100 -90 dB

83

--

88
30

--

--

-- 250 -- kHz

2

dB

1. Guaranteed by design.

2. All specifications in dB are referred to a full-scale ±10 V input.

3. Full-Power Bandwidth defined as Full-Scale input frequency at which Signal-to-Noise (Noise + Distortion) degrades to 60 dB.

TABLE 7. 7809LP SAMPLING DYNAMICS

(SPECIFIED PERFORMANCE -40 TO +85°C)

Memory

P

ARAMETER MIN TYP MAX UNIT

Aperture Delay -- 40 -- ns

Aperture Jitter Sufficient to meet AC specification

Transient Response FS Step -- 2 -- us

Overvoltage Recovery

1

-- 150 -- ns

1. Recovers to specified performance after 2 X FS input overvoltage.

TABLE 8. 7809LP REFERENCE

(SPECIFIED PERFORMANCE -40 TO +85°C)

P

ARAMETER CONDITIONS MIN TYP MAX UNIT

Internal Reference Voltage No Load 2.48 2.5 2.52 V

Internal Reference Source Current (Must be
ext. buffer)

External Reference Voltage Range for Speci­fied Linearity

1

External Reference Current Drain Ext. 2.5000V Ref -- -- 100 µA

1. Tested by application of signal.

-- 1 -- µA

2.3 2.5 2.7 V

1000585

12.19.01 Rev 3

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

5

16-Bit Latchup Protected Analog to Digital Converter

7809LP

TABLE 9. 7809LP DIGITAL OUTPUTS

(SPECIFIED PERFORMANCE -40 TO +85°C)

P

ARAMETER CONDITIONS MIN TYP MAX UNIT

Data Format
Data Coding
Pipeline Delay

Data Clock

Internal (Output Only When Transmitting

Data)

External (Can Run Continually)

V

OL

V

OH

Leakage Current

Output Capacitance

1

1

Serial 16-bits
Binary Two’s Complement or Straight Binary
Conversion results only available after completed conversion

Selectable for internal or external data clock

EXT/INT
EXT/INT

I
I

High-Z State,
V

= 1.6 mA

SINK

SOURCE

= 0V to V

OUT

Low
High

= 500 µA

DIG

--

0.1

-­4

2.3

--

--

--

--

10

0.4

--

-- -- ±10 µA

High-Z State -- 15 -- pF

1. Not tested.

TABLE 10. 7809LP POWER SUPPLIES

(SPECIFIED PERFORMANCE -40 TO +85°C)

P

ARAMETER CONDITIONS MIN TYP MAX UNIT

V

DIG

V

ANA

I

DIG

I

ANA

Power Dissipation

PWRD LOW
PWRD HIGH

Must be < V

V

= V

ANA

= 100 kHz

s

DIG

f

ANA

= 5V

4.75 5 5.25 V

4.75 5 5.25 V

-- 0.3 -- mA

-- 16 -- mA

--

--

--

--

132
350

MHz

V

Memory

mW

1000585

12.19.01 Rev 3

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

6

16-Bit Latchup Protected Analog to Digital Converter

TABLE 11. 7809LP CONTROL LINE FUNCTIONS FOR READ AND CONVERT

7809LP

SPECIFIC FUNCTION CS R/C BUSY EXT/INT

Initiate Conver­sion and Output
Data using Inter­nal Clock

Initiate Conver­sion and Output
Data using Exter­nal Clock

Incorrect Conver­sions

Power Down x

1 > 0

1 > 0

1 > 0

1 > 0

0

0

0

000 > 1xx0xCS

x

0

1 > 0

0

1 > 0

1

1

0 > 1

x

x

1

1

1

1

1

0

0

x

x

0

0

1

1

1

1

1

x

x

DATACL

K

Output

Output

Input

Input

Input

Input

Input

x

x

PWRD SB/BTC

0

0

0

0

x

0

0

0

1

x

x

x

x

x

x

x

x

x

OPERATION

Initiates conversion “n”.
Data from conversion “n­1” clocked out on DATA
synchronized to 16 clock
pulses output on DATA­CLK

Initiates conversion “n”.
Data from conversion “n­1” clocked out on DATA
synchronized to 16 clock
pulses output on DATA­CLK

Initiates conversion “n”

Initiates conversion “n”

Outputs a pulse on SYNC
followed by data from con­version “n” clocked out
synchronized to external
DATACLK.

Outputs a pules on SYNC
followed by data from con­version “n-1” clocked out
synchronized to external
DATACLK
“n” in process.

Outputs a pulse on SYNC
followed by data from con­version “n-1” clocked out
synchronized to external
DATACLK
“n” in process.

or a new conversion will
be initiated without time
for acquisition

Analog circuitry powered.
Conversion will be initi­ated without time for
acquisition

Analog circuitry disabled.
Data from previous con­version maintained in out­put registers

1

. Conversion

1

. Conversion

or R/C must be HIGH

Memory

1000585

12.19.01 Rev 3

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

7

16-Bit Latchup Protected Analog to Digital Converter

TABLE 11. 7809LP CONTROL LINE FUNCTIONS FOR READ AND CONVERT

7809LP

SPECIFIC FUNCTION CS R/C BUSY EXT/INT

Selecting Output

x

x

x

DATACL

x

Format

x

x

x

x

1. See Figure 4 for constraints on previous data valid during conversion.

TABLE 12. 7809LP INPUT RANGE CONNECTION

ANALOG INPUT RANGE

CONNECT R1

±10V V

±5V AGND V

±3.3V V

0V to 10V AGND V

0V to 5V AGND AGND V

0V to 4V V

VIA 200Ω

IN

TO

IN

IN

IN

CONNECT R2

AGND CAP 22.9 kΩ

AGND V

VIA 100Ω

IN

TO

IN

V

IN

IN

K

x

x

PWRD SB/BTC

x

x

OPERATION

0

Serial data is output in

3

Binary Two’s Comple­ment format.

1

Serial data is output in
Straight Binary format.

CONNECT R3IN TO

CAP 13.3 kΩ

IMPEDANCE

Memory

CAP 10.7 kΩ

AGND 13.3kΩ

IN

IN

10.0 kΩ

10.7 kΩ

TABLE 13. 7809LP CONVERSION AND DATA TIMING

(TA = -40 °C TO 85 °C UNLESS OTHERWISE SPECIFIED)

S

YMBOL DESCRIPTION MIN TYP MAX UNIT

t1 Convert Pulse Width 40 -- 6000 ns

t2 BUSY

t3 BUSY

t4 BUSY

t5 Aperture Delay -- 40 -- ns

t6 Conversion Time -- 7.6 8 µs

t7 Acquisition Time -- -- 2 µs

t6 + t7 Throughput Time -- 9 10 µs

t8 R/C

t9 DATACLK Period -- 440 -- ns

t10 Data Valid to DATACLK HIGH Delay 20 75 -- ns

t11 Data Valid after DATACLK LOW Delay 100 125 -- ns

t12 External DATACLK 100 -- -- ns

t13 External DATACLK HIGH 20 -- -- ns

Delay -- -- 65 ns

LOW -- -- 8 µs

Delay after End of Conversion -- 220 -- ns

Low to DATACLK Delay -- 450 -- ns

1000585

12.19.01 Rev 3

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

8

16-Bit Latchup Protected Analog to Digital Converter

7809LP

TABLE 13. 7809LP CONVERSION AND DATA TIMING

(TA = -40 °C TO 85 °C UNLESS OTHERWISE SPECIFIED)

S

YMBOL DESCRIPTION MIN TYP MAX UNIT

t14 External DATACLK LOW 30 -- -- ns

t15 DATACLK HIGH Setup Time 20 -- t12 + 5 ns

t16 R/C

t17 SYNC Delay After DATACLK High 15 -- 35 ns

t18 Data Valid Delay 25 -- 55 ns

t19 CS

to CS Setup Time 10 -- -- ns

to Rising Edge Delay 25 -- -- ns

t20 Data Available after CS

LOW 6 -- -- µs

TABLE 14. 7809LP CONVERSION DATA TIMING

BINARY TWO’S

C

DESCRIPTION ANALOG INPUT

Full Scale
Range

Least Signifi­cant Bit (LSB)

+ Full Scale
(FS - 1 LSB)

Midscale 0V 0V 0V 5V 2.5V 2V 0000 0000

One LSB
Below Mid­scale

-Full Scale -10V -5V 3.333333V0V 0V 0V 1000 0000

±10 ±5 ±3.33V 0V to

10V

305 µV 153 µV 102 µV 153 µV 76 µV 61 µV

9.999695V4.999847V3.333231V9.999847V4.999924V3.999938V0111 1111

-305 µV -153 µV -102 µV 4.999847V2.499924V1.999939V1111 1111

0V to 5V 0V to 4V

OMPLEMENT (SB/BTC

LOW)

INARY CODE

B

1111 1111

0000 0000

1111 1111

0000 0000

DIGITAL OUTPUT

TRAIGHT BINARY

S

(SB/BTC HIGH)

HEX

ODE

BINARY CODE

1111 1111

0000 0000

1111 1111

0000 0000

C

7F FF 1111 1111

0000 1000 0000

FF FF 0111 1111

8000 0000 0000

HEX

C

ODE

FFFF

8000

7FFF

0000

Memory

1000585

12.19.01 Rev 3

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

9

16-Bit Latchup Protected Analog to Digital Converter

FIGURE 1. CONVERSION TIMING

FIGURE 2. SERIAL DATA TIMING USING INTERNAL CLOCK (CS, EXT/INT AND TAG TIED LOW)

7809LP

Memory

IGURE 3. CONVERSION AND READ TIMING WITH EXTERNAL CLOCK (EXT/INT TIED HIGH). READ AFTER

F

ONVERSION

C

1000585

12.19.01 Rev 3

All data sheets are subject to change without notice

10

©2001 Maxwell Technologies

All rights reserved.

16-Bit Latchup Protected Analog to Digital Converter

7809LP

FIGURE 4. CONVERSION AND READ TIMING WITH EXTERNAL CLOCK (EXT/INT TIED HIGH). READ DURING

ONVERSION

C

Memory

1000585

12.19.01 Rev 3

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

11

16-Bit Latchup Protected Analog to Digital Converter

FIGURE 5. OFFSET/GAIN CIRCUITS FOR UNIPOLAR INPUT RANGES

7809LP

Memory

1000585

12.19.01 Rev 3

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

12

16-Bit Latchup Protected Analog to Digital Converter

FIGURE 6. OFFSET/GAIN CIRCUITS FOR BIPOLAR INPUT RANGES

7809LP

Memory

LPTTM Operation

1000585

12.19.01 Rev 3

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

13

16-Bit Latchup Protected Analog to Digital Converter

Latchup Protection Technology (LPTTM) automatically detects an increase in the supply current of the 7809LP con­verter due to a single event effect and internally cycles the power to the converter off, then on, which restores the
steady state operation of the device. A simplified block diagram of the 7809LP circuitry is shown in Figure 7. The

TM

LPT

circuitry consists of two power switch and current sensor blocks, an LPTTM controller block, a BIT current load

block, and an active input protection block.

7809LP

Figure 7. 7809LP Simplified Block Diagram

Memory

The power switch/current sensor blocks sense the supply current drawn by the protected device on the analog and
digital supply pins. When a threshold level is exceeded on either supply line, indicating single event induced latchup of
the protected device, a signal is sent to the LPT
switches to an off state which removes the power supplies from the protected device. At the same time, a signal is
sent to open the active input protection circuits and the LPSTATUS output pin is activated. After a period of time suffi­cient to clear the latchup, the LPT
restoring the operation of the protected device. The BIT circuit is used during system test to electrically trigger the
latchup function by drawing current through the power switch/current sensor blocks sufficient to trigger the LPT
tection.

1000585

TM

controller drives the power switches and input protection back to the on state

TM

controller block. The LPTTM controller then drives the power

TM

12.19.01 Rev 3

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

pro-

14

16-Bit Latchup Protected Analog to Digital Converter

7809LP

Differences Between the 7809LP and the ADS7809

Because the 7809LP uses the ADS7809 die to perform the analog to digital conversion function, its operation and per­formance is very similar to the ADS7809 packaged part from Burr-Brown. In general the operation and application will
be the same for both parts. There are three primary differences: the operation of the supply pins, the operation of the
additional LPBIT and LPSTATUS pins, and the operation of the I/O pins when a latchup is detected.

The ADS7809 provides separate analog and digital supply pins, VANA and VDIG. These same supply pins on the
7809LPRP should be connected to the analog and digital supplies. There is no limit to the capacitance that can be
connected to these pins in the system application.

The 7809LP package also provides access to the ADS7809 die supply pins with the LPVANA and LPVDIG pins. The
signal paths between the supply input pins and the respective die supply pins are low resistance during normal device
operation. When an excessive supply current due to a single event latchup is sensed on either of the supply pins, the

TM

LPT

circuit opens both paths to the die supply pins allowing the latchup condition to clear. The LPVANA and LPV­DIG pins allow access to the current sense circuitry for electrical testing at the component level and provide optimal
locations for attaching supply decoupling capacitors. CAUTION: The LPVANA and LPVDIG pins must not be con­nected to the respective power supplies since this will defeat the LPT

TM

power switch and could result in permanent
latchup of the device during operation in a radiation environment. Electrolytic capacitors should not be connected to
these decoupling pins because the large capacitance will increase the recovery time of the 7809LP. Low ESR ceramic
capacitors should be used with a maximum of .2µF per pin.

Memory

The LPBIT input provides a means to electrically test the LPT

TM

circuit. A high level on the this pin causes a preset

current to be drawn in addition to the normal device current through the analog and digital current sensors. If the high

TM

level is maintained for a sufficient duration, it will trigger the LPT

TM

device. If the LPBIT remains high, the LPT

circuit will continuously cycle the supply voltages off then on. Driving this

input with a 10 µs high level pulse is sufficient duration to assure the LPT

circuit which will cycle the power to the protected

TM

circuit cycles the power off then on one

time only.

A high level on the LPSTATUS output indicates that the LPT

TM

circuit has removed power from the protected device.

The LPSTATUS returns low when the power is restored. LPSTATUS can be used to generate an input to the system

TM

data processor indicating that an LPT

cycle has occurred and the protected device output accuracy may not be met

until after the respective recovery time to the event.

During the time that power is removed from the protected device, it is critical that external circuitry driving the device I/
O pins does not back-drive the device supply through input protection diodes or similar integrated structures. Back­driving of the supply through the device I/O pins could contribute to an extended or even a permanent latchup condi­tion. For the ADS7809 testing has shown that for the normal signal range of operation on the analog input pins R1IN,
R2IN, and R3IN, latchup will not be sustained.

In order to prevent back-driving the supply from the digital I/O pins DATA, SYNC, TAG, R/C,

CS, and PWRD, the
7809LP incorporates active input protection circuits. These circuits act as transmission gates in series with the digital
inputs. During normal operation, these gates are on and present low resistance connections between the package
input pins and the respective die pins. When the LPT

TM

circuit detects a latchup, these gates are switched off and
present a high resistance path between the package inputs and the die inputs. The protected I/O pins are crow barred
during the latchup. The bidirectional signal, DATACLK, is also protected by a transmission gate.

Dedicated digital outputs are not similarly protected since in most applications there will be no appreciable drive signal
on these outputs to back-drive the pins. Pull up resistors on these outputs should be 10 K

1000585

12.19.01 Rev 3

All data sheets are subject to change without notice

Ω or greater to limit the

15

©2001 Maxwell Technologies

All rights reserved.

16-Bit Latchup Protected Analog to Digital Converter

7809LP

back-drive current. Low on resistance, transmission gate circuits are also connected between the package pins and
the die REF and CAP pins. These gates minimize the transient loading on the external filter capacitors required on
these pins. This greatly reduces the single event recovery time of the 7809LP to full accuracy after an LPT

TM

cycle.

During an LPT

TM

cycle, all outputs of the 7809LP are invalid and unpredictable until after the functional recovery time.
After the functional recovery time, data conversions occur with a degraded accuracy until the full accuracy recovery
time.

A summary of the pin differences between the ADS7809 and the 7809LP is provided in the table below.

TABLE 15. ADS7809 AND 7809LP PIN DIFFERENCES

PIN NUMBER ADS7809 7809LPRP PIN DIFFERENCE DESCRIPTION

1-10 Various Various Equivalent function to ADS7809 pins 1-10 respectively. Timing specifications

change slightly (0 - 10 ns) for the 7809LPRP due to the latchup protection circuitry
on ADS7809 die inputs.

15-22 Various Various Equivalent function to ADS7809 pins 11-18 respectively. Timing specifications

change slightly (0 - 10 ns) for the 7809LPRP due to the latchup protection circuitry
on ADS7809 die inputs.

11 -- LPBIT A built in test function of latchup protection. A TTL high level pulse for > 5 microsec-

onds duration on this input will trigger latchup protection of the device. This input
shall be low during normal operation.

12 -- LPSTATUS Latchup protection status output. This TTL level output is low during normal opera-

tion and goes high during a 10 µs decision time period prior to power being
removed. If the latch up current does not last at least 10 µs then LPTSTATUS will
go low (inactive) after the 10 µs decision period without power being removed.
When latchup protection is triggered, this output will go high for the duration of the
time that power is removed from the protected device (50 µs). All output except
LPSTATUS are invalid during the time that power is removed from the ADS7809
die. This output foes low within 1 us of the power being re-applied to the protected
device. Functional operation of the device is within ~25 µs after the LPSTATUS
output returns low with degraded accuracy due to the latchup filter circuitry. Full
accuracy is restored ~5 ms later. This output can be used to inform the system pro­cessor of the latchup protection trigger and the subsequent degraded accuracy in
the 7809LPRP output data. Output pull-up resistors should be 10k
outputs. I/O pins must not be driven high while this signal is active.

13 VANA VANA Equivalent function to ADS7809 pin 19. Analog Supply Input.

14 VDIG VDIG Equivalent function to ADS7809 pin 20. Digital Supply Input.

23 -- LPVANA Latchup protected analog supply pin to the ADS7809 die. Decouple to analog

ground with 0.1 µF ceramic capacitor. Do not exceed 0.2 µF. Do not connect to
VDIG and/or VANA.

24 -- LPVDIG Latchup protected digital supply pin to the ADS7809 die. Decouple to digital ground

with 0.1 µF ceramic capacitor. Do not exceed 0.2 µF. Do not connect to VDIG and/
or VANA.

Ω or larger on

Memory

1000585

12.19.01 Rev 3

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

16

16-Bit Latchup Protected Analog to Digital Converter

7809LP

Testing the 7809LPRP Latchup Protection Circuitry

The LPVANA and LPVDIG pins provide direct access to the 7809LP converter supply pins for attaching external
decoupling capacitors to ground. These pins can also be used to test the LPT

TM

operation and threshold level by sink­ing a pulsed current load to ground as shown in the test circuit in Figure 8. The most accurate threshold current mea­surements are made with the ADS7809 in its lowest power state (PWRD = 5V).

The LPT

TM

operation and device recovery times are most easily measured using the LPBIT input to trigger protection

and recovery. Applying a 10 µsec high duration TTL level to the LPBIT pin causes internal test currents sufficient to

TM

trigger the LPT

TM

LPT

operating characteristics are summarized in Table 16 according to the timing diagram shown in Figure 9. Dur-

circuit to be drawn through both the analog and digital supply sense circuits.

ing the time that the power is cycled, output signals and data from the 7809LP are invalid. The LPSTATUS signal high
indicates that power is removed from the ADS7809 die. When this signal is low, power is applied to the ADS7809 die.
The LPSTATUS signal is used to measure the supply recovery time. The supply recovery time interval starts when the
supply current rises (causing LPSTATUS to go high) and ends when the LPSTATUS signal stabilizes low again.

Within the functional recovery time interval (~25 µsec after the LPT

TM

circuit reapplies power), the normal functional
operation of the converter is restored with less than 5% full scale error. Additional settling time is then required to
return to full accuracy operation. Recovery time intervals are defined which indicate the time to recover first to within 8
bit accuracy, then to within 12 bit accuracy, and finally to full 16 bit accuracy. These recovery times are primarily due to
the single event and power cycling effects on the reference circuits and the settling times of their respective filter
capacitors.

TABLE 16. 7809LP LPTTM OPERATING CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS TYP UNIT

Supply Threshold Current ITHR PWRD = 5V 50 mA

Protection Time TPT LPBIT = 2.4V for 5 µs 1 µsec

Supply Recovery Time TSR LPBIT = 2.4V for 5 µs 50 µsec

Functional Recovery Time TFR LPBIT = 2.4V for 5 µs TSR + 25 µsec

8-bit Accuracy Recovery Time T8R LPBIT = 2.4V for 5 µs 80 µsec

Full Accuracy Recovery Time TFAR LPBIT = 2.4V for 5 µs 5 msec

Memory

1000585

12.19.01 Rev 3

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

17

16-Bit Latchup Protected Analog to Digital Converter

FIGURE 8. 7809LP LPTTM TEST CIRCUIT

C4

.1UF

GND

C4

7809LP

-7.5V

R1

200

+

C1

2.2UF

PULSE GENERATOR 1

5 USEC PULSEWIDTH
RT/FT < 10 NS

2.4V

.4V

R2 100
R3 22.9K

+

C2

2.2UF

GNDGND

GND

U?

1

R1IN

2

AGND1

3

R2IN

4

R3IN

5

CAP

6

REF

7

AGND2

8

SB/BTC

9

EXT/INT

10

DGND

11

LPBIT
LPSTATUS12VANA

7809LPRP

LPVDIG

LPVANA

PWRD

BUSY

TAG

DATA

DATACLK

SYNC

VDIG

GND

R/C

.1UF

24
23
22
21
20

CS

19
18
17
16
15
14
13

IS

+5V

S1

DIGITAL
CONTROL
AND
MONITORING

+

GND

C3
10UF

D1
1N4149

D2

1N4149

Q1
2N2369A

GND

R3

50

PULSE GENERATOR 2

20 USEC PULSEWIDTH
0V

-VP

Memory

1000585

12.19.01 Rev 3

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

18

16-Bit Latchup Protected Analog to Digital Converter

FIGURE 9. 7809LP LPTTM TIMING DIAGRAM

2.4V

PULSE GENERATOR 1

LPBIT

PULSE GENERATOR 2

SUPPLY CURRENT (IS)

.4V

0V

-VP

ITHR

IS (TYP)

5V

TPT

CHARGE CURRENT INTO
DECOUPLING CAPACITOR

IS PEAK

0

TSR

IS (TYP)

7809LP

LPSTATUS

ALL OUTPUTS

OUTPUT DATA
ERROR

0V

OUTPUTS
VALID

FULL
ACCURACY

OUTPUTS
INVALID

FULL SCALE (F.S.)

- FULL SCALE

TFR

T8R

T12R

TFAR

OUTPUTS
VALID

<1/20 F.S.

>-1/20 F.S.

<1/256 F.S.

<1/4096 F.S.

FULL
ACCURACY

Memory

1000585

12.19.01 Rev 3

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

19

16-Bit Latchup Protected Analog to Digital Converter

FIGURE 10. SEL CROSS SECTION

7809LP

Memory

FIGURE 11. SEU CROSS SECTION

1000585

12.19.01 Rev 3

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

20

16-Bit Latchup Protected Analog to Digital Converter

7809LP

Memory

24-PIN RAD-PAK® FLAT PACKAGE

SYMBOL

MIN NOM MAX

A 0.157 0.170 0.183

b 0.015 0.017 0.022

c 0.004 0.005 0.009

D -- 0.596 0.640

E 0.350 0.400 0.420

E1 -- -- 0.450

E2 0.180 0.236 --

E3 0.030 0.082 --

e 0.050 BSC

L 0.315 0.325 0.335

Q 0.026 0.053 0.056

S1 0.005 0.015 --

N24

F24-01

Note: All dimensions in inches

DIMENSION

1000585

12.19.01 Rev 3

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

21

16-Bit Latchup Protected Analog to Digital Converter

Important Notice:

These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies
functionality by testing key parameters either by 100% testing, sample testing or characterization.

The specifications presented within these data sheets represent the latest and most accurate information available to
date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no
responsibility for the use of this information.

Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems
without express written approval from Maxwell Technologies.

Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Tech­nologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts.

7809LP

Memory

1000585

12.19.01 Rev 3

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

22

16-Bit Latchup Protected Analog to Digital Converter

)

Product Ordering Options

Model Number

7809LP

7809LP

RP

F X

Feature

Screening Flow

Package

Option Details

Multi Chip Module (MCM)
K = Maxwell Class K
H = Maxwell Class H
E = Engineering (testing @ +25°C
I = Industrial (testing @ -40°C,
+25°C, +85°C)

F = Flat Pack

Memory

1000585

Radiation Feature

Base Product
Nomenclature

12.19.01 Rev 3

RP = R

AD-PAK® package

16-Bit Latchup Protected Analog
to Digital Converter

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

23