Datasheet 7545ARPFB, 7545ARPFS, 7545ARPFE Datasheet (MAXWELL)

7B991

Programmable Skew

Clock Buffer (PSCB)

FEATURES:

• All output pair skew < 100 ps typical (250 max.)

• 3.75 to 80 MHz output operation

• User-selectable output functions

• Selectable skew to 18 ns

• Inverted and non-inverted

• Operation at ½ and ¼ input frequency

• Operation at 2x and 4x input frequency (input as low as

3.75 MHz)

• Zero input to output delay

• 50% duty-cycle outputs

• Outputs drive 50

• Low operating current

• Package: 32-pin R

• Jitter < 200 ps peak-to-peak (< 25 ps RMS)

• Compatible with Pentium™-based processor

• Total dose hardness:

- >100 krads (Si), depending upon space mission

• Excellent Single Event Effects:

- SEL > 116MeV/mg/cm

- SEUTH -3 MeV/mg/cm

- SEU sat cross section: 1E-3/device

Ω terminated lines

AD-PAK® flat package

2

2

Logic Diagram

DESCRIPTION:

Maxwell Technologies’ 7B991 Programmable Skew Clock
Buffers (PSCB) offer user-selectable control over system
clock functions. These multiple-output clock drivers provide
the system integrator with functions necessary to optimize tim­ing of high-performance computer systems. Eight individual
drivers, arranged as four pairs of user-controllable outputs,
can each drive terminated transmission lines with impedances
as low as 50
skews and full-swing logic levels.

Each output can be hardwired to one of nine delay or function
configurations. Delay increments of 0.7 to 1.5 ns are deter­mined by the operating frequency with outputs able to skew up
to ± 6 time units from their nominal “zero” skew position. The
completely integrated PLL allows external load and transmis­sion line delay effects to be canceled. When this “zero delay”
capability of the PSCB is combined with the selectable output
skew functions, the user can create output-to-output delays of
up to ±12 time units.

Maxwell Technologies' patented R
ogy incorporates radiation shielding in the microcircuit pack­age. It eliminates the need for box shielding while providing
the required radiation shielding for a lifetime in orbit or space
mission. In a GEO orbit, R
krad (Si) radiation dose tolerance. This product is available
with screening up to Class S.

Ω while delivering minimal and specified output

AD-PAK® packaging technol-

AD-PAK provides greater than 100

Memory

1000604

[phone] - Fax: [phone] - www.maxwell.com

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1

Programmable Skew Clock Buffer (PSCB)

TABLE 1. 7B991 PINOUT DESCRIPTIONS

PIN SYMBOL I/O DESCRIPTION

1 REF I Reference frequency input supplies the frequency and timing

against which all functional variation is measured.

17 FB I PLL feedback (typically connected to one of the eight outputs)

3 FS I Three-level frequency range select. See Table 2.

26, 27 1F0, 1F1 I Three-level function select inputs for output pair 1 (1Q0, 1Q1). See

Table 2.

29, 30 2F0, 2F1 I Three-level function select inputs for output pair 2 (2Q0, 2Q1). See

Table 2.

4, 5 3F0, 3F1 I Three-level function select inputs for output pair 3 (3Q0, 3Q1). See

Table 2.

6, 7 4F0, 4F1 I Three-level function select inputs for output pair 4 (4Q0, 4Q1). See

Table 2.

31 TEST I Three-level select. See test mode section under the block diagram

descriptions.

23, 24 1Q1, 1Q0 O Output pair 1. See Table 2.

21, 22 2Q1, 2Q0 O Output pair 2. See Table 2.

14, 15 3Q1, 3Q0 O Output pair 3. See Table 2.

10, 11 4Q1, 4Q0 O Output pair 4. See Table 2.

9, 16, 18, 25 V

2V

12, 13, 21,

22, 28, 32

CCN

CCQ

GND PWR Ground.

PWR Power supply for output drivers

PWR Power supply for internal circuitry

7B991

Memory

TABLE 2. 7B991 ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL MIN MAX UNIT

Storage Temperature T

Operating Temperature Range T

Supply Voltage to Ground Potential V

DC Input Voltage V

Output Current into Outputs (LOW) I

Static Discharge Voltage (per MIL-STD-882, Method 3015) V

Latchup Current I

1000604

12.19.01 Rev 3

S

A

S

I

OUT

SD

LU

All data sheets are subject to change without notice

-65 150 °C

-40 85 °C

-0.5 7.0 V

-0.5 7.0 V

-- 64 mA

>2001 -- V

>200 -- mA

©2001 Maxwell Technologies.

All rights reserved.

2

Programmable Skew Clock Buffer (PSCB)

TABLE 3. DELTA LIMITS

PARAMETER VARIATION

7B991

I

CCQ

I

CCN

±10% of specified value in Table 5

±10% of specified value in Table 5

TABLE 4. 7B991 RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL MIN MAX UNIT

Supply Voltage V

Input HIGH Voltage (REF and FB

CC

V

IH

inputs only)

Input LOW Voltage (REF and FB

V

IL

inputs only)

Three-Level Input HIGH Voltage (Test,
FS, xFn)

1

Thermal Impedance

Θ

V

IHH

JC

1. These inputs are normally wired to VCC,GND, or left unconnected (actual threshold voltages vary as a percentage of VCC).
Internal termination resistors hold unconnected inputs at V
puts may glitch and the PLL may require an additional t

CC

time before all datasheet limits are achieved.

LOCK

-0.5 +7.0 V

2.0 V

CC

V

-0.5 0.8 V

VCC-0.85 V

CC

V

-- 3.43 °C/W

/2. If these inputs are switched, the function and timing of the out-

Memory

TABLE 5. 7B991 DC ELECTRICAL CHARACTERISTICS

(VCC = 5V ±10%, TA = -40 TO 85°C, UNLESS OTHERWISE SPECIFIED)

P

ARAMETER SYMBOL TEST CONDITIONS MIN MAX UNIT

Output HIGH Voltage V

Output LOW Voltage V

Input HIGH Voltage (REF and FB
inputs only)

Input LOW Voltage (REF and FB
inputs only)

Three-Level Input HIGH Voltage
(Test, FS, xFn)

Three-Level Input MID Voltage (Test,
FS, xFn)

Three-Level Input LOW Voltage (Test,
FS, xFn)

Input HIGH Leakage Current
(REF and FB inputs only)

Input LOW Leakage Current
(REF and FB inputs only)

1

1

1

VCC = Min, IOH = -16 mA 2.4 -- V

OH

VCC = Min, IOL = 46 mA -- 0.45 V

OL

V

IH

V

IL

V

V

V

I

I

Min < VCC < Max VCC-0.85 -- V

IHH

Min < VCC < Max VCC/2 -

IMM

Min < VCC < Max 0.0 0.85 V

ILL

VCC = Max, VIN = 5V -- 10 µA

IH

VCC = Max, VIN = 0.4V -500 -- µA

IL

2.0 -- V

-- 0.8 V

VCC/2 +

500 mV

500 mV

V

1000604

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3

Programmable Skew Clock Buffer (PSCB)

TABLE 5. 7B991 DC ELECTRICAL CHARACTERISTICS

(VCC = 5V ±10%, TA = -40 TO 85°C, UNLESS OTHERWISE SPECIFIED)

P

ARAMETER SYMBOL TEST CONDITIONS MIN MAX UNIT

7B991

Input HIGH Current (Test, FS, xFn) I

Input MID Current (Test, FS, xFn) I

Input LOW Current (Test, FS, xFn) I

Output Short Circuit (Test, FS, xFn)

2

IMM

I

VIN = V

IH

CC

-- 200 µA

VIN = 2.75 -200 200 µA

VIN = GND -- -200 µA

ILL

OS

VCC = Max., V

= GND (25 °C

OUT

-- -250 mA

only)

Operating Current used by Internal
Circuitry

Output Buffer Current per Output Pair

3

Power Dissipation per Output Pair

4

I

CCQ

I

CCN

CCN

= Max, all input

CCQ

selects open

V

= V

CCN

CCQ

= Max, I

= 0 mA,

OUT

Input selects open, fMAX

P

V

= V

D

CCN

CCQ

= Max, I

OUT

= 0 mA

-- 90 mA

-- 14 mA

-- 78 mW

V

= V

Input selects open, fMAX

1. These inputs are normally wired to V
Internal termination resistors hold unconnected inputs at V
puts may glitch and the PLL may require an additional t

,GND, or left unconnected (actual threshold voltages vary as a percentage of VCC).

CC

/2. If these inputs are switched, the function and timing of the out-

CC

time before all datasheet limits are achieved.

LOCK

2. This device should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room
temperature only.

3. Total output current per output pair can be approximated by the following expression that includes device current plus load cur­rent:

ICCN = [(4 + 0.11F) + [((835-3F)/Z) + (.0022FC)]N] x 1.1

Where:

f = frequency in MHz

C = capacitive load in pF

Z = line impedance in ohms

N = number of loaded outputs; 0, 1, or 2

FC = F < C

4. Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation
due to the load circuit:

PD = [(22 + 0.61F) + [((1550-2.7F)/Z) + (.0125FC)]N] x 1.1

Memory

TABLE 6. 7B991 CAPACITANCE

P

ARAMETER SYMBOL TEST CONDITIONS MAX UNIT

Input Capacitance C

1. Guaranteed by design.

1000604

1

TA = 25 °C, f = 1 MHz, VCC = 5.0V 10 pF

IN

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4

©2001 Maxwell Technologies.

All rights reserved.

Programmable Skew Clock Buffer (PSCB)

FIGURE 1. TTL AC TEST LOAD

FIGURE 2. TTL INPUT TEST WAVEFORM

7B991

Memory

TABLE 7. AC ELECTRICAL CHARACTERISTICS

(VCC = 5V ±10%, TA = -40 TO 85°C, UNLESS OTHERWISE SPECIFIED)

P

ARAMETER SYMBOL MIN TYP MAX UNIT

Operating Clock Frequency in MHz FS = LOW

REF Pulse Width HIGH t

REF Pulse Width LOW t

Programmable Skew Unit t

Zero Output Matched-Pair Skew (XQ0, XQ1)

Zero Output Skew (All Outputs)

6,8,9

Output Skew (Rise-Rise, Fall-Fall, Same Class Out-

6,10

puts)

Output Skew (Rise-Fall, Nominal-Inverted, Divided­Divided)

6,10

Output Skew (Rise-Rise, Fall-Fall, Different Class
Outputs)

6,10

Output Skew (Rise-Fall, Nominal-Divided, Divided­Inverted)

Device-to-Device Skew

6,10

1,11,12

Propagation Delay, REF Rise to FB Rise t

Output Duty Cycle Variation

13

1,4

FS = MID

FS = HIGH

1,4,5

6,7

1,4

t

SKEWPR

t

SKEW0

t

SKEW1

t

SKEW2

t

SKEW3

t

SKEW4

t

f

NOM

RPWH

RPWL

U

t

DEV

PD

ODCV

1,2,3

15 -- 30 MHz

25 -- 50

40 -- 80

5.0 -- -- ns

5.0 -- -- ns

See Table 2

-- 0.1 0.50 ns

-- 0.3 0.75 ns

-- 0.6 1.0 ns

-- 1.0 1.5 ns

-- 0.7 1.2 ns

-- 1.2 1.7 ns

-- -- 1.65 ns

-1 0.0 1 ns

-1.2 0.0 1.2 ns

1000604

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5

Programmable Skew Clock Buffer (PSCB)

7B991

TABLE 7. AC ELECTRICAL CHARACTERISTICS

1,2,3

(VCC = 5V ±10%, TA = -40 TO 85°C, UNLESS OTHERWISE SPECIFIED)

P

ARAMETER SYMBOL MIN TYP MAX UNIT

Output HIGH Time Deviation from 50%

Output LOW Time Deviation from 50%

Output Rise Time

Output Fall Time

PLL Lock Time

14,16

14,16

17

Cycle-to-Cycle Output Jitter Peak-to-

1. The level to be set of FS in determined by the “normal” operating frequency (f
Logic Block Diagram). Nominal frequency (f
undivided modes (See Table 9). The frequency appearing at the REF and FB inputs will be f
FB is undivided. The frequency of the REF and FB inputs will be f

14,15

14,15

t

PWH

t

PWL

t

ORISE

t

OFALL

t

LOCK

t

3

Peak

) always appears at 1Q0 and the other outputs when they are operated in their

NOM

JR

-- -- 3 ns

-- -- 3.5 ns

0.15 1.5 2.5 ns

0.15 1.5 2.5 ns

-- -- 0.5 ms

-- -- 200 ps

) of the VCO and Time Unit Generator (see

NOM

when the output connected to

NOM

NOM

/2 or f

/4 when the part is configured for a frequency

NOM

multiplication by using a divided output as the FB input.

2. Test measurement levels for the 7B991 are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times of 2 ns or
less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified.

3. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parame­ters.

4. For all three state inputs. HIGH indicates a connection to V
connections. Internal termination circuitry holds an unconnected input to V

5. When the FS pin is selected HIGH, the REF input must not transition upon power-up until V

6. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same t
has been selected when all are loaded with 50 pF and terminated with 50

7. t

8. t

is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0tU.

SKEWPR

is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not

SKEW0

, LOW indicates a connection to GND, and MID indicates an open

CC

CC

/2.

has reached 4.3V.

CC

U

Ω to 2.06V.

delay

shifted.

9. C

= 0 pF. For CL = 30 pF, t

L

10.There are three classes of outputs: Nominal (multiple of t

SKEW0

= 0.35 ns.

delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and

U

divided (3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode).

11. t

is the output-to-output skew between any two devices operating under the same conditions (VCC ambient temperature, air

DEV

flow, etc.)

12.Guaranteed by design.

13.t

is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in t

ODCV

SKEW2

and t

SKEW4

spec-

ifications.

14.Specified with outputs loaded 30 pF for the 7B99 devices. Devices are terminated through 50

15.t

is measured at 2.0V. t

PWH

16.t

17.t

and t

ORISE

is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within

LOCK

measured between 0.8V and 2.0V.

OFALL

is measured at 0.8V.

PWL

normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until t

Ω to 2.05V.

is

PD

within specified limits.

Memory

1000604

12.19.01 Rev 3

All data sheets are subject to change without notice

©2001 Maxwell Technologies.

All rights reserved.

6

Programmable Skew Clock Buffer (PSCB)

FIGURE 3. AC TIMING DIAGRAMS

7B991

Memory

1000604

12.19.01 Rev 3

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©2001 Maxwell Technologies.

All rights reserved.

7

Programmable Skew Clock Buffer (PSCB)

7B991

BLOCK DIAGRAM DESCRIPTION

Phase Frequency Detector and Filter

These two blocks accept inputs from the reference frequency (REF) input and the feedback (FB) input and generate
correction information to control the frequency of the Voltage-Controlled Oscillator (VCO). These blocks, along with
the VCO, form a Phase-Locked Loop (PLL) that tracks the incoming REF signal.

VCO and Time Unit Generator

The VCO accepts analog control inputs from the PLL filter block and generates a frequency that is used by the time
unit generator to create discrete time units that are selected in the skew select matrix. The operational range of the
VCO is determined by the FS control pin. The time unit (t
the level of the FS pin as shown in Table 1.

) is determined by the operating frequency of the device and

U

TABLE 8. 7B991 FREQUENCY RANGE SELECT AND tU CALCULATION

2,3

FS

LOW 15 30 44 22.7

MID 25 50 26 38.5

HIGH 40 80 16 62.5

1. For all three state inputs. HIGH indicates a connection to VCC. LOW indicates a connection to GND, and MID indicates an
open connection. Internal termination circuitry holds an unconnected input to V

2. The level to be set of FS is determined by the “normal” operating frequency (f
Logic Block Diagram). Nominal frequency (f
undivided modes (See Table 9). The frequency appearing at the REF and FB inputs will be f
FB is undivided. The frequency appearing at the REF and FB inputs will be f
frequency multiplication by using a divided output as the FB input.

3. When the FS pin is selected HIGH, the REF input must not transition upon power-up until V

fNOM (MH

M

IN MAX

Z)t

) always appears at 1Q0 and the other outputs when they are operated in their

NOM

= 1/fNOM X N

U

WHERE N =

CC

NOM

/2 or f

NOM

/2.

) of the VCO and Time Unit Generator (see

NOM

/4 when the part is configured for a

NOM

CC

1

PPROXIMATE FREQUENCY (MHZ)

A

AT WHICH t

when the output connected to

has reached 4.3V.

= 1.0 ns

U

Skew Select Matrix

The skew select matrix is comprised of four independent sections. Each section has two low-skew, high-fanout driv­ers(xQ0, xQ1), and two corresponding three-level function select (xF0, xF1) inputs. Table 9 below shows the nine pos­sible output functions for each section as determined by the function select inputs. All times are measured with respect
to the REF input assuming that the output connected to the FB input has 0t

selected.

U

Memory

1000604

12.19.01 Rev 3

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8

Programmable Skew Clock Buffer (PSCB)

7B991

TABLE 9. 7B991 PROGRAMMABLE SKEW CONFIGURATIONS

UNCTION SELECTS OUTPUT FUNCTIONS

F

1

1F1, 2F1, 3F1, 4F1 1F0, 2F0, 3F0, 4F0 1Q0, 1Q1, 2Q0, 2Q1 3Q0, 3Q1 4Q0, 4Q1

LOW LOW -4t

LOW MID -3t

LOW HIGH -2t

MID LOW -1t

MID MID 0t

MID HIGH +1t

HIGH LOW +2t

HIGH MID +3t

HIGH HIGH +4t

U

U

U

U

U

U

U

U

U

Divide by 2 Divide by 2

-6t

-4t

-2t

0t

+2t

+4t

+6t

U

U

U

U

U

U

U

-6t

-4t

-2t

0t

+2t

+4t

+6t

U

U

U

U

U

U

U

Divide by 4 Inverted

1. For all three state inputs. HIGH indicates a connection to VCC. LOW indicates a connection to GND, and MID indicates an open
connections. Internal termination circuitry holds an inconnected input to V

FIGURE 4. TYPICAL OUTPUTS WITH FB CONNECTED TO A ZERO-SKEW OUTPUT

CC

/2.

1

Memory

1. FB connected to an output selected for “zero” skew (i.e. xF1 = xF0 = MID)

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9

Programmable Skew Clock Buffer (PSCB)

7B991

Tes t M od e

The TEST input is a three-level input. In normal system operation, this pin is connected to ground, allowing the
7B991RP to operate as explained briefly above (for testing purposes, any of the three-level inputs can have a remov-

able jumper to ground, or be tied LOW through a 100Ω resistor. This will allow an external tester to change the state

of these pins.)

If the TEST input is forced to its MID or HIGH state, the device will operate with its internal phase locked loop discon­nected, and input levels supplied to REF will directly control all outputs. Relative output to output functions are the
same as in normal mode.

In contrast with normal operation (TEST tied LOW). All outputs will function based only on the connection of their own
function select inputs (xF0 and xF1) and the waveform characteristics of the REF input.

Memory

1000604

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10

Programmable Skew Clock Buffer (PSCB)

7B991

OPERATIONAL MODE DESCRIPTIONS

FIGURE 5. ZERO-SKEW AND/OR ZERO-DELAY CLOCK DRIVER

Figure 5 shows the PSCB configured as a zero-skew clock buffer. In this mode, the 7B991 can be used as the basis
for a low-skew clock distribution tree. When all of the function select inputs (xF0, xF1) are left open, the outputs are
aligned and may each drive a terminated transmission line to an independent load. The FB input can be tied to any
output in this configuration and the operating frequency range is selected with the FS pin. The low-skew specification,
coupled with the ability to drive terminated transmission lines (with impedances as low as 50
circuit board design.

Ω), allow efficient printed

Memory

FIGURE 6. PROGRAMMABLE-SKEW CLOCK DRIVE

Figure 6 shows a configuration to equalize skew between metal traces of different lengths. In addition to low skew
between outputs, the PSCB can be programmed to stagger the timing of its outputs. The four groups of output pairs
can each be programmed to different output timing. Skew timing can be adjusted over a wide range in small incre­ments with the appropriate strapping of the function select pins. In this configuration, the 4Q0 output is fed back to FB
and configured for zero skew. The other three pairs of outputs are programmed to yield different skews relative to the
feedback. By advancing the clock signal on the longer traces or retarding the clock signal on shorter traces, all loads
can receive the clock pulse at the same time.

In this illustration, the FB input is connected to an output with 0-ns skew (xF1, xF0 = MID) selected. The internal PLL
synchronizes the FB and REF inputs and aligns their rising edges to insure that all outputs have precise phase align­ment.

1000604

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©2001 Maxwell Technologies.

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11

Programmable Skew Clock Buffer (PSCB)

Clock skews can be advanced by ± 6 time units (tU) when using an output selected for zero skew as the feedback. A
wider range of delays is possible if the output connected to FB is also skewed. Since “Zero Skew”, +t
defined relative to output groups, and since the PLL aligns the rising edges of REF and FB, it is possible to create
wider output skews by proper selection of the xFn inputs. For example, a +10 t
achieved by connecting 1Q0 to FB and setting 1F0 = 1F1 = GND, 3F0 = MID, and 3F1 = HIGH (Since FB aligns at -4
t

and 3Qx skews to +6 tU, a total of +10 tU skew is realized.). Many other configurations can be realized by skewing

U

both the output used as the FB input and skewing the other outputs.

between REG and 3Qx can be

U

7B991

and -tU are

U

FIGURE 7. INVERTED OUTPUT CONNECTIONS

Memory

Figure shows an example of the invert function of the PSCB. In this example the 4Q0 output used as the FB input is
programmed for invert (4F0 = 4F1 = HIGH) while the other three pairs of outputs are programmed for zero skew.
When 4F0 and 4F1 are tied high, 4Q0 and 4Q1 become inverted zero phase outputs. The PLL aligns the rising edge
of the FB input with the rising edge of the REF. This causes the 1Q, 2Q, and 3Q outputs to become the “inverted” out­puts with respect to the REF input. By selecting which output connects to FB, it is possible to have 2 inverted and 6
non-inverted output or 6 inverted and 2 non-inverted outputs. The correct configuration would be determined by the
need for more (or fewer) inverted outputs. 1Q, 2Q, and 3Q outputs can also be skewed to compensate for varying
trace delays independent of inversion on 4Q.

FIGURE 8. FREQUENCY MULTIPLIER WITH SKEW CONNECTIONS

Figure illustrates the PSCB configured as a clock multiplier. The 3Q0 output is programmed to divide by four and is
fed back to FB. This causes the PLL to increase its frequency until the 3Q0 and 3Q1 outputs are locked at 20 MHz
while the 1Qx and 2Qx outputs run at 80 MHz. The 4Q0 and 4Q1 outputs are programmed to divide by two, which

1000604

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12

Programmable Skew Clock Buffer (PSCB)

results in a 40 MHz waveform at these outputs. Note that the 20 and 40 MHz clocks fall simultaneously and are out of
phase on their rising edge. This will allow the designer to use the rising edges of the ½ frequency and ¼ frequency
outputs without concern for rising-edge skew. The 2Q0, 2Q1, 1Q0, and 1Q1 outputs run at 80 MHz and are skewed by
programming their select inputs accordingly. Note that the FS pin is wired for 80 MHz operation because that is the fre­quency of the fastest output.

7B991

FIGURE 9. FREQUENCY DIVIDER CONNECTIONS

Memory

Figure demonstrates the PSCB in a clock divider application. 2Q0 is fed back to the FB input and programmed for
zero skew. 3Qx is programmed to divide by four. 4Qx is programmed to divide by two. Note that the falling edges of
the 4Qx and 3Qx outputs are aligned. This allows use of the rising edges of the ½ frequency and ¼ frequency without
concern for skew mismatch. The 1Qx outputs are programmed to zero skew and are aligned with the 2Qx outputs. In
this example, the FS input is grounded to configure the device in the 15 to 30 MHz range since the highest frequency
output is running at 20 MHz.

FIGURE 10. MULTI-FUNCTION CLOCK DRIVER

Figure shows some of the functions that are selectable on the 3Qx and 4Qx outputs. These include inverted outputs
and outputs that offer divide-by-2 and divide-by-4 timing. An inverted output allows the system designer to clock differ­ent sub-systems on opposite edges, without suffering from the pulse asymmetry typical of non-ideal loading. This
function allows the two subsystems to each be clocked 180 degrees out of phase, but still to be aligned within the
skew specification.

The divided outputs offer a zero-delay divider for portions of the system that need the clock to be divided by either two
or four, and still remain within a narrow skew of the “1X” clock. Without this feature, an external divider would need to
be added, and the propagation delay of the divider would add to the skew between the different clock signals.

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13

Programmable Skew Clock Buffer (PSCB)

These divided outputs, coupled with the Phase Locked Loop, allow the PSCB to multiply the clock rate at the REF
input by either two or four. This mode will enable the designer to distribute a low-frequency clock between various por­tions of the system, and then locally multiply the clock rate to a more suitable frequency, while still maintaining the low­skew characteristics described above at the same time. It can multiply by two and four or divide by two (and four) at
the same time that it is shifting its outputs over a wide range or maintaining zero skew between selected outputs.

7B991

FIGURE 11. BOARD-TO-BOARD CLOCK DISTRIBUTION

Memory

Figure shows the 7B991 connected in series to construct a zero-skew clock distribution tree between boards. Delays
of the downstream clock buffers can be programmed to compensate for the wire length (i.e. select negative skew
equal to the wire delay) necessary to connect them to the master clock source, approximating a zerp-delay clock tree.
Cascaded clock buffers will accumulate low-frequency jitter because of the non-ideal filtering characteristics of the
PLL filter. It is recommended that not more than two clock buffers be connected in series.

1000604

12.19.01 Rev 3

All data sheets are subject to change without notice

©2001 Maxwell Technologies.

All rights reserved.

14

Programmable Skew Clock Buffer (PSCB)

7B991

Memory

32 PIN RAD-PAK® FLAT PACKAGE

SYMBOL DIMENSION

MIN NOM MAX

A 0.121 0.134 0.147

b 0.015 0.017 0.022

c 0.004 0.005 0.009

D -- 0.820 0.830

E 0.472 0.480 0.488

E1 -- -- 0.498

E2 0.304 0.310 --

E3 0.030 0.085 --

e 0.050 BSC

L 0.355 0.365 0.375

Q 0.020 0.035 0.045

S1 0.005 0.027 --

N32

F32-10

Note: All dimensions in inches

1000604

12.19.01 Rev 3

All data sheets are subject to change without notice

©2001 Maxwell Technologies.

All rights reserved.

15

Programmable Skew Clock Buffer (PSCB)

Important Notice:

These data sheets are created using the chip manufacturer’s published specifications. Maxwell Technologies verifies
functionality by testing key parameters either by 100% testing, sample testing or characterization.

The specifications presented within these data sheets represent the latest and most accurate information available to
date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no
responsibility for the use of this information.

Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems
without express written approval from Maxwell Technologies.

Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Tech­nologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts.

7B991

Memory

1000604

12.19.01 Rev 3

All data sheets are subject to change without notice

©2001 Maxwell Technologies.

All rights reserved.

16

Programmable Skew Clock Buffer (PSCB)

)

Product Ordering Options

Model Number

7B991

7545A

XX

F X

Feature

Screening Flow

Package

Option Details

Monolithic
S = Maxwell Class S
B = Maxwell Class B
E = Engineering (testing @ +25°C
I = Industrial (testing @ -55°C,
+25°C, +125°C)

Memory

F = Flat Pack

1000604

Radiation Feature

Base Product
Nomenclature

12.19.01 Rev 3

RP = R

AD-PAK® package

Programmable Skew Clock Buffer
(PSCB)

All data sheets are subject to change without notice

17

©2001 Maxwell Technologies.

All rights reserved.