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74VHCT574A
Octal D-Type Flip-Flop with 3-STATE Outputs
74VHCT574A Octal D-Type Flip-Flop with 3-STATE Outputs
July 1997
Revised April 2005
General Description
The VHCT574A is an advance d high speed CMOS octal
flip-flop with 3-STATE output fabricated with silicon gate
CMOS technology. It achieves the high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type flipflop is controlled by a clock input (CP) and an Output
Enable input (OE
outputs are in a high impedance state.
Protection circuits en sure that 0V to 7V can be appli ed to
the input and output (No te 1) pins without regard to the
supply voltage. This device can be used to interface 3 V to
5V systems and two supply systems such as bat tery back
up. This circuit prevents device destruction due to mismatched supply and input voltages.
Note 1: Outputs in OFF-State.
). When the OE input is HIGH, the eight
Features
■ High speed: f
■ Power Down Protection is provided on all inputs and
outputs.
■ Low Noise: V
■ Low Power Dissipation:
I
4 PA (max) @ TA 25qC
CC
■ Pin and Function Compatible with 74HCT574
140 MHz (typ) at TA 25qC
MAX
1.6V (max)
OLP
Ordering Code:
Order Number Package Number Package Description
74VHCT574AM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74VHCT574ASJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHCT574AMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHCT574AN N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also availab le on Tape and Reel. Specify by appending the suffix let t er “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
IEEE/IEC
Connection Diagram
© 2005 Fairchild Semiconductor Corporation DS500029 www.fairchildsemi.com
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Pin Descriptions Truth Table
Pin Names Description
D
0–D7
Data Inputs
CP Clock Pulse Input 3-STATE
74VHCT574A
OE
O
0–O7
Output Enable Input 3-STATE
Outputs
Functional Description
The VHCT574A consi sts of eight edge-triggered flip-fl ops
with individual D-type inputs and 3-STATE true outputs.
The buffered clock and bu ffered Output Enable are common to all flip-flops. The eight flip-flo ps will store the state
of their individual D inputs that meet the setup and hold
time requirements on the LOW- to-HIGH Clock (C P) transi-
Logic Diagram
Inputs Outputs
D
H
L
CP OE O
n
n
L H
L L
X X H Z
H HIGH Voltage Level
L
LOW Voltage Level
Immaterial
X
Z
High Impedance
LOW-to-HIGH Transition
tion. With the Output Enable (OE
) LOW, the contents of the
eight flip-flops are available at the ou tputs. When the OE
HIGH, the outputs go to the high imp edance state. O peration of the OE
input does not affect th e state of the flip-
flops.
is
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Absolute Maximum Ratings(Note 2) Recommended Operating
Supply Voltage (VCC)
DC Input Voltage (V
DC Output Voltage (V
)
IN
)
OUT
(Note 3)
(Note 4)
Input Diode Current (I
Output Diode Current (I
DC Output Current (I
DC V
/GND Current (ICC)
CC
Storage Temperature (T
Lead Temperature (T
)
IK
) (Note 5) r20 mA
OK
)
OUT
)
STG
)
L
0.5V to 7.0V
0.5V to 7.0V
0.5V to VCC 0.5V
0.5V to 7.0V
r
r
65q
C to 150qC
(Soldering, 10 seconds) 260
Conditions
Supply Voltage (V
Input Voltage (V
Output Voltage (V
20 mA
Operating Temperature (T
25 mA
75 mA
Input Rise and Fall Time (t
Note 2: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
q
C
ables. Fairchild does not recommend operation outside databook specifications.
Note 3: HIGH or LOW state. I
observed.
Note 4: When outputs are in OFF-State or when V
Note 5: V
Note 6: Unused inputs must be held HIGH or LOW. They may not float.
(Note 3) 0V to V
(Note 4) 0V to 5.5V
V
5.0V r 0.5V 0 ns/V a 20 ns/V
CC
OUT
(Note 6)
) 4.5V to 5.5V
CC
) 0V to 5.5V
IN
)
OUT
)
OPR
, tf)
r
absolute maximum rating must be
OUT
GND, V
! VCC (Outputs Active).
OUT
CC
DC Electrical Characteristics
Symbol Parameter
V
IH
V
IL
V
OH
V
OL
I
OZ
I
IN
I
CC
I
CCT
I
OFF
HIGH Level 4.5 2.0 2.0
Input Voltage 5.5 2.0 20
LOW Level 4.5 0.8 0.8
Input Voltage 5.5 0.8 0.8
HIGH Level
Output Voltage 3.94 3.80 V or VILIOH 8 mA
LOW Level
Output Voltage 0.36 0.44 V or V
3-STATE Output
Off-State Current V
Input Leakage 0–5.5 r0.1 r1.0 PAVIN 5.5V or GND
Current
Quiescent Supply 5.5 4.0 40.0 PAVIN VCC or GND
Current
Maximum ICC/Input 5.5 1.35 1.50 mA VIN 3.4V
Output Leakage Current 0.0 0.5 5.0
(Power Down State)
V
CC
(V) Min Typ Max Min Max
4.5
4.5
5.5 r0.25 r2.5 PA
TA 25qCT
4.40 4.50 4.40 V VIN VIHIOH 50 PA
0.0 0.1 0.1 V VIN VIHIOL 50 PA
40qC to 85qC
A
Units Conditions
V
V
VIN VIH or V
OUT
Other Input VCC or GND
P
AV
OUT
40q
C to 85qC
OV.
8 mA
ILIOL
IL
VCC or GND
5.5V
74VHCT574A
CC
3 www.fairchildsemi.com
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Noise Characteristics
Symbol Parameter
74VHCT574A
V
OLP
(Note 7)
V
OLV
Quiet Output Maximum Dynamic V
Quiet Output Minimum Dynamic V
(Note 7)
V
IHD
Minimum HIGH Level Dynamic Input Voltage 5.0 2.0 V CL 50 pF
(Note 7)
V
ILD
Maximum LOW Level Dynamic Input Voltage 5.0 0.8 V CL 50 pF
(Note 7)
Note 7: Parameter guaranteed by design.
AC Electrical Characteristics
Symbol Parameter
t
PLH
t
PHL
t
PZL
t
PZH
t
PLZ
t
PHZ
t
OSLH
t
OSHL
f
MAX
Propagation Delay
Time 5.6 10.4 1.0 11.5 CL 50 pF
3-STATE Output
Enable Time 7.3 11.2 1.0 12.5 CL 50 pF
3-STATE Output
Disable Time
Output to
Output Skew
Maximum Clock
Frequency 85 130 75 CL 50 pF
C
IN
Input 4 10 10 pF VCC Open
Capacitance
C
OUT
Output 9 pF VCC 5.0V
Capacitance
C
PD
Power Dissipation 25 pF (Note 9)
Capacitance
Note 8: Parameter guaranteed by design. t
Note 9: C
operating current can be obtained by the equation: I
can be calculated by the equation: C
is defined as the value of the internal equivalent capacitanc e w hich is calculated from the operating c urrent consumption without load. Average
PD
V
5.0 r 0.5
5.0 r 0.5
5.0 r 0.5 7.0 11.2 1.0 12.0 ns
5.0 r 0.5 1.0 1.0 ns
5.0 r 0.5
|t
OSLH
(total) 20 12n.
PD
25qC
V
CC
(V)
OL
OL
CC
5.0 1.2 1.6 V CL 50 pF
5.0
TA 25qCT
(V) Min Typ Max Min Max
4.1 9.4 1.0 10.5
6.5 10.2 1.0 11.5
T
A
Typ Limits
1.2
1.6 V CL 50 pF
A
Units Conditions
40qC to 85qC
Units Conditions
ns
RL 1 k:CL 15 pF
ns
RL 1 k:CL 50 pF
(Note 8)
90 140 80
t
|; t
|t
t
PLH max
PLH min
OSHL
PHL max
(opr.) CPD * VCC * fIN ICC/8 (per F/F). The total CPD when n pcs. of the Octal D F lip-Flop operates
CC
PHL min
|
MHz
CL 15 pF
CL 15 pF
AC Operating Requirements
V
Symbol Parameter
tW(H) Minimum Pulse Width (CP)
tW(L)
t
S
t
H
Minimum Set-Up Time 5.0 r 0.5 2.5 2.5
Minimum Hold Time 5.0 r 0.5 2.5 2.5
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CC
(V)
5.0 r 0.5 6.5 8.5 ns
TA 25qC T
40qC to 85qC
A
Min Typ Max Min Max
Units
ns
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Physical Dimensions inches (millimeters) unless otherwise noted
74VHCT574A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
5 www.fairchildsemi.com
Page 6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
74VHCT574A
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
www.fairchildsemi.com 6
Package Number M20D
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
74VHCT574A
20-Lead Thin Shrin k Small Ou tlin e Pack age (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
7 www.fairchildsemi.com
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
74VHCT574A Octal D-Type Flip-Flop with 3-STATE Outputs
Fairchild does not assume any responsibility for use of an y circuitry described, no circuit patent licenses are imp lied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the
user.
2. A critical component in any componen t of a life support
device or system whose failu re to perform can be reasonably expected to cause the failure of the li fe su pp ort
device or system, or to affect its safety or effectiveness.
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