Datasheet 74VHCT16373ATTR Datasheet (SGS Thomson Microelectronics)

WITH 3-STATE OUTPUTS NON INVERTING

■ HIGH SPEED:

t

= 5.0 ns (TYP.) at VCC=5V

PD

■ LOW POWER DISSIPATION:

I

=4µA (MAX.) at TA=25°C

CC

■ COMPATIBLE WITHTTL OUTPUTS:

V

=2V (MIN.) VIL= 0.8 (MAX.)

IH

■ POWER DOWN PROTECTION ON INPUTS

■ SYMMETRICAL OUTPUT IMPEDANCE:

|I

|=IOL=8mA(MIN)

OH

■ BALANCED PROPAGATION DELAYS:

t

≅ t

PLH

PHL

■ OPERATING VOLTA GE RANGE:

V

(OPR) = 4.5V to 5.5V

CC

■ PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 16373

■ IMPROVED LATCH-UP IMMUNITY

■ LOW NOISE: V

= 0.9V (MAX.)

OLP

74VHCT16373A

16-BIT D-TYPE LATCH

TSSOP

ORDER CODES

PACKAGE TUBE T & R

TSSOP 74VHCT16373ATTR

PIN CONNECTION

DESCRIPTION

The 74VHCT16373A is an advanced high-speed
CMOS 16 BIT D-TYPE LATCH with 3 STATE
OUTPUTS NON INVERTING fabricated with
sub-micron silicon gate and double-la yer meta l
wiring C

2

MOS technology.
These 16 bit D-TYPE latches are byte controlled
by two latch enable inputs (nLE) and two output
enable inputs(nOE

).
While the nLE input is held at a high level, the nQ
outputs will follow the data (D) inputs.
When the nLE is taken LOW, the nQ outputs will
be latched at the logic level of D data inputs.
When the (nOE

) input is low, the nQ outputs will
be in a normal lo gic s tate (high or low logic level);
when nOE

is at h igh level ,the outputs will be in a
high impedance state.
Power down protection is provided on all inputs
and 0 t o 7V can be accepted on inputs with no
regard to t he supply voltage. This device can be
usedto interface 5V to 3V.
All inputs and outpu ts are equipped with protec­tion circuits against static discharge, giving them
2KV ESD immunity and transient excess vo ltage.

1/10February 2003

74VHCT16373A

INPUT EQUIVALENT CIRCUIT

PIN DESCRIPTION

PIN No SYMBOL NAME AND FUNCTION

1 1OE

2, 3, 5, 6, 8, 9,

11, 12

13,14,16,17,

19, 20, 22, 23

24 2OE

25 2LE Latch Enable Input

36,35,33,32,

30, 29, 27, 26

47,46,44,43,

41, 40, 38, 37

48 1LE Latch Enable Input

4, 10, 15, 21,
28, 34, 39, 45

7, 18, 31, 42 V

1Q0 to 1Q7 3-State Outputs

2Q0 to 2Q7 3-State Outputs

2D0 to 2D7 Data Inputs

1D0 to 1D7 Data Inputs

GND Ground (0V)

CC

3 State Output Enable
Input (Active LOW)

3 State Output Enable
Input (Active LOW)

Positive Supply Voltage

TRUTH TABLE

INPUTS OUTPUT

OE

HXX Z

L L X NO CHANGE *
LHL L
LHH H

X : Don‘tCare
Z : High Impedance
* : Qoutputs are latched at the time when the LE input is taken low
logiclevel.

LE D Q

IEC L OGIC SYMBOLS

2/10

LOGIC DIAGRAM

This logic diagram has not to be used to estimate propagation delays

ABSOLUTE MAXIMUM RATINGS

74VHCT16373A

Symbol Parameter Value Unit

V

V

V

I

I

OK

I

or I

I

CC

T

T

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied

Supply Voltage

CC

DC Input Voltage

I

DC Output Voltage -0.5 to VCC+ 0.5

O

DC Input Diode Current

IK

DC Output Diode Current
DC Output Current

O

DC VCCor Ground Current

GND

Storage Temperature

stg

Lead Temperature (10 sec)

L

-0.5 to +7.0 V

-0.5 to +7.0 V
V

-20 mA

± 20 mA
± 25 mA
± 75 mA

-65 to +150 °C

300 °C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Value Unit

V

V

V

T

dt/dv Input Rise and Fall Time (note 1) (Vcc= 5.0±0.5V)

Supply Voltage

CC

Input Voltage

I

Output Voltage 0 to V

O

Operating Temperature

op

4.5 to 5.5 V
0 to 5.5 V

CC

-55 to 125 °C
0 to 20 ns/V

V

1) VINfrom0.8V to 2.0V

3/10

74VHCT16373A

DC SPECIFICATIONS

Symbol Parameter

V

V

V

I

High Level Input

IH

Voltage

V

Low Level Input

IL

Voltage
High Level Output

OH

Voltage
Low Level Output

OL

Voltage
High Impedance

I

OZ

Output Leakage
Current

Input Leakage

I

I

Current
Quiescent Supply

CC

Current

Test Condition Value

= 25°C

T

V

CC

(V)

4.5to

5.5

A

Min. Typ. Max. Min. Max. Min. Max.

222V

4.5to

5.5

4.5

4.5

4.5

4.5

5.5

0to

5.5

5.5

IO=-50 µA

=-8 mA

I

O

IO=50 µA

=8 mA

I

O

I=VIH

or V

IL

V

VO=VCCor GND

V

= 5.5V or GND

I

V

I=VCC

or GND

4.4 4.5 4.4 4.4

3.94 3.8 3.7

0.0 0.1 0.1 0.1

-40 to 85°C -55 to 125°C

Unit

0.8 0.8 0.8 V

V

0.36 0.44 0.55

V

±0.25 ± 2.5 ± 2.5 µA

± 0.1 ± 1 ± 1 µA

44040µA

AC ELECTRICAL CHARACTERISTICS (Input t

Test Condition Value Unit

Symbol Parameter

t
t

t
t

t
t

PZH

t
t

PHZ

t

OSLH

t

OSHL

(*) Voltagerangeis5.0V ± 0.5V
(Note 1 : Parameter guaranteed by design. t

Propagation Delay

PLH

Time

PHL

LE to Qn
Propagation Delay

PLH

Time

PHL

Dn to Qn
Output Enable

PZL

Time
Output Disable

PLZ

Time

t

Pulse Width (LE)

w

HIGH
Setup Time Dn to

t

s

LE HIGH or LOW
Hold Time Dn to LE

t

h

HIGH or LOW
Output to Output

Skew time (note 1)

V

5.0

5.0

5.0

5.0

5.0

5.0

5.0

5.0

5.0

5.0

5.0

5.0

C

CC

(V)

L

(pF)

(*)

15 5.0 8.5 1 9.5 1 9.5

(*)

50 6.0 9.5 1 10.5 1 10.5

(*)

15 5.5 8.5 1 9.5 1 9.5

(*)

50 6.2 9.5 1 10.5 1 10.5

(*)

15 5.2 9.5 1 10.5 1 10.5

(*)

50 6.5 10.5 1 11.5 1 11.5

(*)

15 6 10.2 1 11.0 1 11.0 ns

(**)

50 7 11.2 1 12.0 1 12.0

(*)

(*)

(*)

(*)

50 1.. 1.5 1.5 ns

=|t

soLH

pLHm-tpLHn

=3ns)

r=tf

= 25°C

T

A

-40 to 85°C -55 to 125°C

Min. Typ. Max. Min. Max. Min. Max.

555ns

444ns

111ns

|, t

soHL

=|t

pHLm-tpHLn

|

ns

ns

ns

4/10

74VHCT16373A

CAPACITIVE CHARACTERISTICS

Test Condition Value

= 25°C

Symbol Parameter

V

CC

(V)

C

C

C

Input Capacitance

IN

Output

OUT

Capacitance
Power Dissipation

PD

Capacitance

5.0

= 10MHz

f

IN

T

A

Min. Typ. Max. Min. Max. Min. Max.

410 10 10pF
6pF

21 pF

(note 1)

1) CPDis defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I

DYNAMIC SWITCHING CHARACTERISTICS

Test Condition Value

= 25°C

Symbol Parameter

V

CC

(V)

V
V

Dynamic Low

OLP

Voltage Quiet

OLV

Output (note 1, 2)

5.0

Dynamic High

V

IHD

Voltage Input

5.0 3.5 V

C

L

=50pF

(note 1, 3)
Dynamic Low

V

ILD

Voltage Input

5.0 1.5 V

(note 1, 3)

1) Worst case package.

2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n-1) outputs switching and one output at GND.

3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (V
(V

), f=1MHz.

IHD

T

A

Min. Typ. Max. Min. Max. Min. Max.

0.6 0.9

-0.9 -0.6

-40 to 85°C -55 to 125°C

CC(opr)=CPDxVCCxfIN+ICC

-40 to 85°C -55 to 125°C

), 0V to threshold

ILD

Unit

/n (per Latch)

Unit

V

5/10

74VHCT16373A

TEST CIRCUIT

TEST SWITCH

t

PLH,tPHL

t

PZL,tPLZ

t

PZH,tPHZ

CL= 15/50 pF or equivalent (includes jig and probe capacitance)
R

=R1=1KΩ or equivalent

L

R

T=ZOUT

of pulse generator (typically 50Ω)

Open

V

CC

GND

WAVEFORM 1 : LETO Qn PROPAGATION DEL AYS, LEMINIMUMPULSE WIDTH, Dn T O LESETUP
AND HOLD TIMES (f=1MHz; 50% duty cycle)

6/10

WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)

74VHCT16373A

WAVEFORM 3 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)

7/10

74VHCT16373A

TSSOP48 MECHANICAL DATA

mm. inch

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

A 1.2 0.047

A1 0.05 0.15 0.002 0.006

A2 0.9 0.035

b 0.17 0.27 0.0067 0.011

c 0.09 0.20 0.0035 0.0079

D 12.4 12.6 0.488 0.496

E 8.1 BSC 0.318 BSC

E1 6. 0 6.2 0.236 0.244

e 0 .5 BSC 0.0197 BSC

K0˚ 8˚0˚ 8˚

L 0.50 0.75 0. 020 0.030

A2

A

A1

b

e

D

K

c

E1

L

E

PIN 1 IDENTIFICATION

8/10

1

7065588C

74VHCT16373A

Tape & Reel TSSOP48 MECHANICAL DATA

mm. inch

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

A 330 12.992
C 12.8 13.2 0.504 0.519
D 20.2 0.795
N 60 2.362

T 30.4 1.197
Ao 8.7 8.9 0.343 0.350
Bo 13.1 13.3 0.516 0.524
Ko 1.5 1.7 0.059 0.067
Po 3.9 4.1 0.153 0.161

P 11.9 12.1 0.468 0.476

9/10

74VHCT16373A

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use o f suc h inf ormat ion n or f or an y infr ingeme nt of paten ts or oth er ri gh ts of third part ies whic h may resul t f rom
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.

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