The 74VHCT16 245A is an advanc ed high-speed
CMOS 16-BIT BUS TRANSCEIVER (3-STATE)
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology.
This IC is intended for two-way asynch ronous
communicationbetweendatabusses;the
direction of data transmission is determined by
DIR input. The enable input G
canbeusedto
disable the device so that the busses are
effectively isolated.
All inputsand outputs are equipped wit h
protection circuits against static discharge, giving
them 2KV ESD immunit y and transient excess
voltage.
All floating bus terminals during High Z State must
be held HIGH or LOW.
TSSOP
ORDER CODES
PACKAGETUBET & R
TSSOP74VHCT16245ATTR
PIN CONNECTION
1/10July 2003
Page 2
74VCHT16245A
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN NoSYMBOLNAME AND FUNCTION
11DIRDirectional Control
2, 3, 5, 6, 8, 9,
11, 12
13,14,16,17,
19, 20, 22, 23
242DIRDirectional Control
252G
36,35,33,32,
30, 29, 27, 26
47,46,44,43,
41, 40, 38, 38
481G
4, 10, 15, 21,
28, 34, 39, 45
7, 18, 31, 42
1B1 to 1B8 Data Inputs/Outputs
2B1 to 2B8 Data Inputs/Outputs
Output Enable Input
2A1 to 2A8 Data Inputs/Outputs
1A1 to 1A8 Data Inputs/Outputs
Output Enable Input
GNDGround (0V)
V
CC
Positive Supply Voltage
IEC LOGIC SYMBOLS
TRUTH TABLE
INPUTSFUNCTIONOUTPUT
G
LLOUTPUTINPUTA = B
LHINPUTOUTPUTB = A
HXZZZ
X :Don‘t Care
Z : High Impedance
2/10
DIRA BUSB BUSYn
Page 3
74VCHT16245A
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
V
V
V
I
I
OK
I
or I
I
CC
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) Output in OFF State
2) Highor Low State
RECOMMENDED OPERATING CONDITIONS
SymbolParameterValueUnit
V
V
V
V
T
dt/dv
1) Output in OFF State
2) Highor Low State
3) VIN from0.8V to 2V
Supply Voltage
CC
DC Input Voltage (DIR, G)
I
DC BUS I/O Voltage (see note 1)
I/O
DC BUS I/O Voltage (see note 2)-0.5 to VCC+ 0.5
I/O
DC Input Diode Current
IK
DC Output Diode Current
DC Output Current
O
DC VCCor Ground Current
GND
Storage Temperature
stg
Lead Temperature (10 sec)
L
Supply Voltage
CC
Input Voltage
I
BUS I/O Voltage (see note 1)
I/O
BUS I/O Voltage (see note 2)0 to V
I/O
Operating Temperature
op
Input Rise and Fall Time (see note 3) (V
=5.0±0.5V)
CC
-0.5 to +7.0V
-0.5 to +7.0V
-0.5 to +7.0V
-20mA
± 20mA
± 25mA
± 75mA
-65 to +150°C
300°C
4.5 to 5.5V
0 to 5.5V
0 to 5.5V
CC
-55 to 125°C
0 to 20ns/V
V
V
3/10
Page 4
74VCHT16245A
DC SPECIFICATIONS
SymbolParameter
V
V
V
I
+
I
OPD
High Level Input
IH
Voltage
V
Low Level Input
IL
Voltage
High Level Output
OH
Voltage
Low Level Output
OL
Voltage
IozHigh Impedance
Output Leakage
Current
Input Leakage
I
I
Current
Quiescent Supply
CC
Current
I
Additional Worst
CC
Case Supply
Current
Output Leakage
Current
Test ConditionValue
= 25°C
T
V
CC
(V)
4.5to
5.5
A
Min.Typ. Max. Min. Max.Min. Max.
222V
4.5to
5.5
4.5
4.5
4.5
4.5
5.5
0to
5.5
5.5
IO=-50 µA
=-8 mA
I
O
IO=50 µA
=8 mA
I
O
I=VIH
or V
V
VO=0Vto5.5V
V
= 5.5V or GND
I
V
I=VCC
or GND
4.44.54.44.4
3.943.83.7
0.00.10.10.1
IL
±0.25± 2.5± 2.5µA
One Input at 3.4V,
other input at V
5.5
CC
or GND
=5.5V
0
V
OUT
-40 to 85°C -55 to 125°C
Unit
0.80.80.8V
V
0.360.440.55
V
± 0.1± 1.0± 1.0µA
44040µA
1.351.51.5mA
0.55.05.0µA
AC ELECTRICAL CHARACTERISTICS (Input t
Test ConditionValue
SymbolParameter
t
t
t
t
PZH
t
t
PHZ
t
OSLH
t
OSHL
(*) Voltage rangeis 5.0V ± 0.5V
Note 1: Parameter guaranteed by design. t
Propagation Delay
PLH
Time
PHL
Output Enable
PZL
Time
Output Disable
PLZ
Time
Output to Output
Skew Time (note 1)
(*)
(V)
C
(pF)
L
V
CC
5.0154.57.51.08.51.010.0
5.0505.38.71.09.51.011.0
5.015
5.0509.714.81.016.01.017.0
RL = 1KΩ
5.050RL= 1KΩ10.015.41.016.51.017.5ns
5.0501.01.01.0ns
=|t
soLH
pLHm-tpLHn
r=tf
|, t
=3ns)
= 25°C
T
A
Min.Typ. Max. Min. Max.Min. Max.
9.013.81.015.01.016.0
soHL
=|t
pHLm-tpHLn
|
-40 to 85°C -55 to 125°C
Unit
ns
ns
4/10
Page 5
74VCHT16245A
CAPACITIVE CHARACTERISTICS
Test ConditionValue
= 25°C
SymbolParameter
T
A
Min.Typ. Max. Min. Max.Min. Max.
C
C
C
Input Capacitance
IN
Bus Input
I/O
Capacitance
Power Dissipation
PD
Capacitance
6101010pF
8pF
18pF
(note 1)
1) CPDis defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (RefertoTest Circuit). Averageoperating current can beobtained by the following equation. I
DYNAMIC SWITCHING CHARACTERISTICS
Test ConditionValue
= 25°C
SymbolParameter
V
CC
(V)
V
V
Dynamic Low
OLP
Voltage Quiet
OLV
Output (note 1, 2)
5.0
Dynamic High
V
IHD
Voltage Input
5.02.0
C
L
=50pF
(note 1, 3)
Dynamic Low
V
ILD
Voltage Input
5.00.8
(note 1, 3)
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.0V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.0V. Inputs under test switching: 3.0V to threshold (V
(V
), f=1MHz.
IHD
T
A
Min.Typ. Max. Min. Max.Min. Max.
0.60.9
-0.9-0.6
-40 to 85°C -55 to 125°C
CC(opr)=CPDxVCCxfIN+ICC
-40 to 85°C -55 to 125°C
), 0V to threshold
ILD
Unit
/8(per circuit)
Unit
V
5/10
Page 6
74VCHT16245A
TEST CIRCUIT
TESTSWITCH
t
PLH,tPHL
t
PZL,tPLZ
t
PZH,tPHZ
CL=15/ 50pF or equivalent (includes jig and probe capacitance)
RL=R1=1KΩor equivalent
R
T=ZOUT
of pulse generator (typically 50Ω
Open
V
CC
GND
WAVEFORM 1: PROPAG ATION DE LAYS (f=1MHz; 50% duty cycle)
6/10
Page 7
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
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mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
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