Datasheet 74VHCT14ASJX, 74VHCT14ASJ, 74VHCT14AN, 74VHCT14AMX, 74VHCT14AMTCX Datasheet (Fairchild Semiconductor)
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December 1998
Revised March 1999
74VHCT14A Hex Schmitt Inverter
© 1999 Fairchild Semiconductor Corporation DS500147.prf www.fairchildsemi.com
74VHCT14A
Hex Schmi t t Inverter
General Description
The VHCT14A is an advanced high speed CMOS Hex
Schmitt Inverter fabricated with silicon gate CMOS technology. The VHCT14A contains six independent inverters
which are capable of transform ing slowly changing input
signals into sharply defined, jitter-free output signals.
Protection circuits en sure that 0V to 7V c an be app lied to
the input pins without reg ard to the supply voltage an d to
the output pins with V
CC
= 0V. These circuits prevent
device destruction due to m ismatched supply and input/
output voltages. This devic e can be use d to inte rfa ce 3V to
5V systems and two supply systems such as battery
backup.
Features
■ High spee d: tPD = 5.0 ns (typ) at TA = 25°C
■ High noise immunity: V
IH
= 2.0V, VIL = 0.8V
■ Power down protection is provided on all inputs and outputs
■ Low noise: V
OLP
= 1.0V (max)
■ Low power dissipation:
I
CC
= 2 µA (max) @ TA = 25°C
■ Pin and function compatible with 74HCT14
Ordering Code:
Surface mount pack ages are also available on Tape and Reel. Specif y by appending the suffix letter “X ” to th e ordering code.
Logic Symbol
Pin Descriptions
Connection Diagram
Truth Table
Order Number Package Number Package Description
74VHCT14AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
74VHCT14ASJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHCT14AMTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHCT14AN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
A
n
Inputs
O
n
Outputs
AO
LH
HL
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74VHCT14A
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
(Note 5)
Note 1: Absolute Maximum Ratings are values beyond which the device
may be damaged or ha ve its useful li fe impaire d. The datab ook specifications should be met, without exception, to ensure that the system design is
reliable over its p ower supp ly, temperature, and ou tput/input loading variables. Fairchild does not recom mend operation outside data book specifications.
Note 2: HIGH or LOW state. I
OUT
absolute maximum rating must be
observed.
Note 3: V
CC
= 0V.
Note 4: V
OUT
< GND, V
OUT
> VCC (Outputs Active)
Note 5: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Noise Characteristics
Note 6: Paramete r guaranteed by design.
Supply Voltage (VCC) −0.5V to +7.0V
DC Input Voltage (V
IN
) −0.5V to +7.0V
DC Output Voltage (V
OUT
)
(Note 2) −0.5V to V
CC
+ 0.5V
(Note 3) −0.5V to 7.0V
Input Diode Current (I
IK
) −20 mA
Output Diode Current (I
OK
)
(Note 4) ±20 mA
DC Output Current (I
OUT
) ±25 mA
DC V
CC
/GND Current (ICC) ±50 mA
Storage Temperature (T
STG
) −65°C to +150°C
Lead Temperature (T
L
)
(Soldering, 10 seconds) 260°C
Supply Voltage (V
CC
) 4.5V to +5.5V
Input Voltage (V
IN
) 0V to +5.5V
Output Voltage (V
OUT
)
(Note 2) 0V to V
CC
(Note 3) 0V to 5.5V
Operating Temperature (T
OPR
) −40°C to +85°C
Symbol Parameter
V
CC
(V)
TA = 25°CT
A
= −40°C to +85°C
Units Conditions
Min Typ Max Min Max
V
P
Positive Threshold Voltage 4.5 1.9 1.9
V
5.5 2.1 2.1
V
N
Negative Threshold Voltage 4.5 0.5 0.5
V
5.5 0.6 0.6
V
H
Hysteresis Voltage 4.5 0.4 1.4 0.4 1.4
V
5.5 0.4 1.5 0.4 1.5
V
OH
HIGH Level Output Voltage
4.5
4.40 4.50 4.40 V VIN = VIL IOH = −50 µA
3.94 3.80 V IOH = −8 mA
V
OL
LOW Level Output Voltage
4.5
0.0 0.1 0.1 V VIN = VIH IOL = 50 µA
0.36 0.44 V IOL = 8 mA
I
IN
Input Leakage Current 0 − 5.5 ±0.1 ±1.0 µAVIN = 5.5V or GND
I
CC
Quiescent Supply Current 5.5 2.0 20.0 µAVIN = VCC or GND
I
CCT
Maximum ICC/Input
5.5 1.35 1.50 mA
VIN = 3.4V
Other Inputs = VCC or GND
I
OFF
Output Leakage Current 0.0 0.5 5.0 µAV
OUT
= 5.5V
(Power Down State)
Symbol Parameter
VCC
(V)
TA = 25°C
Units Conditions
Typ Limits
V
OLP
(Note 6)
Quiet Output Maximum Dynamic V
OL
5.0 0.8 1.0 V CL = 50 pF
V
OLV
(Note 6)
Quiet Output Minimum Dynamic V
OL
5.0 −0.8 1.0 V CL = 50 pF
V
IHD
(Note 6)
Minimum HIGH Level Dynamic Input Voltage
5.0 2.0 V CL = 50 pF
V
ILD
(Note 6)
Maximum LOW Level Dynamic Input Voltage
5.0 0.8 V CL = 50 pF
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74VHCT14A
AC Electrical Characteristics
Note 7: CPD is defined as the value of the internal equivalent capacitance which is c alc ulated from the opera ti ng c urrent consumption wit hout load. Average
operating current ca n be obtained by the equation: I
CC
(opr.) = CPD * VCC * fIN + ICC/6 (per gate).
Symbol Parameter
V
CC
TA = 25°C T
A
= −40°C to +85°C
Units Conditions
(V) Min Typ Max Min Max
t
PHL
Propagation Delay
5.0 ± 0.5
5.0 7 .6 1.0 9.0 ns CL = 15 pF
t
PLH
6.5 9 .6 1.0 11.0 ns CL = 50 pF
C
IN
Input Capacitance 2 10 10 pF VCC = OPEN
C
PD
Power Dissipation Capacitance 11 pF (Note 7)
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74VHCT14A
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
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74VHCT14A
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
74VHCT14A Hex Schmitt Inverter
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life supp ort de vices o r syste ms a re device s or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the
user.
2. A cri tical compon ent in any com ponen t of a life su pport
device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the life su pp ort
device or system, or to affect its safety or effectiveness.
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N14A
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