Datasheet 74VHCT08ASJX, 74VHCT08ASJ, 74VHCT08AN, 74VHCT08AMX, 74VHCT08AMTCX Datasheet (Fairchild Semiconductor)
...Page 1
July 1997
Revised March 1999
74VHCT08A Quad 2-Input AND Gate
© 1999 Fairchild Semiconductor Corporation DS500025.prf www.fairchildsemi.com
74VHCT08A
Quad 2-Input AND Gate
General Description
The VHCT08A is an advanced high speed CMOS 2 Input
AND Gate fabricated with silicon gate CMOS technology. It
achieves the high-speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation.
The internal circuit is composed of 4 stages including buffer
output, which provi de high noise immunity and stable ou tput.
Protection circuits ensu re that 0V to 7V can be applied to
the input pins without reg ard to the supply voltage an d to
the output pins with V
CC
= 0V. These circuits prevent
device destruction due to m ismatched supply and input/
output voltages. This devic e can be use d to inte rfa ce 3V to
5V systems and two supply systems such as battery
backup.
Features
■ High spee d: tPD = 5.0 ns (typ) at TA = 25°C
■ High noise immunity: V
IH
= 2.0V, VIL = 0.8V
■ Power down protection is provided on all inputs and
outputs
■ Low noise: V
OLP
= 0.8V (max)
■ Low power dissipation:
I
CC
= 2 µA (max) @ TA = 25°C
■ Pin and function compatible with 74HCT08
Ordering Code:
Surface mount pack ages are also available on Tape and Reel. Specify by appending the s uffix let te r “X” to the ordering code
Logic Symbol
IEEE/IEC
Pin Descriptions
Connection Diagram
Truth T able
Order Number Package Number Package Description
74VHCT08AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74VHCT08ASJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHCT08AMTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHCT08AN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
A
n
, B
n
Inputs
O
n
Outputs
A B O
L L L
L H L
H L L
H H H
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74VHCT08A
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
(Note 5)
Note 1: Absolute Maximum Ratings are values beyond which the device
may be damaged or ha ve its useful li fe impaire d. The datab ook specifications should be met, without exception, to ensure that the system design is
reliable over its p ower supp ly, temperature, and ou tput/input loading variables. Fairchild does not recom mend operation outside data book specifications.
Note 2: HIGH or LOW state. I
OUT
absolute maximum rating must be
observed.
Note 3: V
CC
= 0V.
Note 4: V
OUT
< GND, V
OUT
> VCC (Outputs Active).
Note 5: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Noise Characteristics
Note 6: Paramete r guaranteed by design.
Supply Voltage (VCC) −0.5V to +7.0V
DC Input Voltage (V
IN
) −0.5V to +7.0V
DC Output Voltage (V
OUT
)
(Note 2) −0.5V to V
CC
+ 0.5V
(Note 3) −0.5V to 7.0V
Input Diode Current (I
IK
) −20 mA
Output Diode Current (I
OK
) (Note 4) ±20 mA
DC Output Current (I
OUT
) ±25 mA
DC V
CC
/GND Current (ICC) ±50 mA
Storage Temperature (T
STG
) −65°C to +150°C
Lead Temperature (T
L
)
(Soldering, 10 seconds) 260°C
Supply Voltage (V
CC
) 4.5V to 5.5V
Input Voltage (V
IN
) 0V to +5.5V
Output Voltage (V
OUT
)
(Note 2) 0V to V
CC
(Note 3) 0V to 5.5V
Operating Temperature (T
OPR
) −40°C to +85°C
Input Rise and Fall Time (t
r
, tf)
V
CC
= 5.0V ± 0.5V 0 ns/V ∼ 20 ns/V
Symbol Parameter
V
CC
(V)
TA = 25°C T
A
= −40°C to +85°C
Units Conditions
Min Typ Max Min Max
V
IH
HIGH Level 4.5 2.0 2.0
V
Input Voltage 5.5 2.0 2.0
V
IL
LOW Level 4.5 0.8 0.8
V
Input Voltage 5.5 0.8 0.8
V
OH
HIGH Level 4.5 4.40 4.50 4.40 V VIN = V
IH
or V
IL
IOH = −50 µA
Output Voltage 4.5 3.94 3.80 V IOH = −8 mA
V
OL
LOW Level Output Voltage 4.5 0.0 0.1 0.1 V VIN = V
IH
or V
IL
IOL = 50 µA
4.5 0.36 0.44 V IOL = 8 mA
I
IN
Input Leakage Current 0 − 5.5 ±0.1 ±1.0 µAVIN = 5.5V or GND
I
CC
Quiescent Supply Current 5.5 2.0 20.0 µAVIN = VCC or GND
I
CCT
Maximum ICC/ Input
5.5 1.35 1.50 mA
V
IN
= 3.4V
Other Inputs = VCC or GND
I
OFF
Output Leakage Current 0.0 0.5 5.0 µAV
OUT
= 5.5V
(Power Down State)
Symbol Parameter
V
CC
(V)
TA = 25°C
Units Conditions
Typ Limit
V
OLP
(Note 6)
Quiet Output Maximum Dynamic V
OL
5.0 0.4 0.8 V CL = 50 pF
V
OLV
(Note 6)
Quiet Output Minimum Dynamic V
OL
5.0 −0.4 −0.8 V CL = 50 pF
V
IHD
(Note 6)
Minimum HIGH Level Dynamic Input Voltage 5.0 2.0 V CL = 50 pF
V
ILD
(Note 6)
Maximum LOW Level Dynamic Input Voltage 5.0 0.8 V CL = 50 pF
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74VHCT08A
AC Electrical Characteristics
Note 7: CPD is defined as the value of the internal equivalent capacitance, which is calculated from the operating current consumption without load. Average
operating current ca n be obtained from the equ at ion: I
CC
(opr.) = CPD * VCC * fIN + ICC/4 (per gate)
Symbol Parameter
V
CC
(V)
TA = 25°C T
A
= −40°C to +85°C
Units Conditions
Min Typ Max Min Max
t
PLH
Propagation Delay 5.0 5.0 6.9 1.0 8.0 ns CL = 15 pF
t
PHL
±0.5 5.5 7.9 1.0 9.0 CL = 50 pF
C
IN
Input Capacitance 4 10 10 pF VCC = Open
C
PD
Power Dissipation Capacitance 18 pF (Note 7)
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74VHCT08A
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
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74VHCT08A
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
74VHCT08A Quad 2-Input AND Gate
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the
user.
2. A critical component i n any compon ent of a lif e support
device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the life su pp ort
device or system, or to affect its safety or effectiveness.
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
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