Datasheet 74VHC573SJX, 74VHC573SJ, 74VHC573N, 74VHC573MX, 74VHC573MTCX Datasheet (Fairchild Semiconductor)
...Page 1
March 1993
Revised April 1999
74VHC573 Octal D-Type Latch with 3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS011563.prf www.fairchildsemi.com
74VHC573
Octal D-Type Latch with 3-STATE Outputs
General Description
The VHC573 is an advanced high speed CMOS octal latch
with 3-STATE output fabricated with silicon gate CMOS
technology. It achieves the high speed opera tion simil ar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enabl e input (LE) and an Output Enable
input (OE
). When the OE input is HIGH, th e eight outputs
are in a high impedance state.
An input protection circuit en sures that 0V to 7V can be
applied to the input pins without re gard to the supply voltage. This device can be used to interface 5V to 3V systems
and two supply systems such as bat tery back up. This cir-
cuit prevents device d estr uct i on due to m isma tche d s upp l y
and input voltages.
Features
■ High Speed: tPD = 5.0 ns (typ) at VCC = 5V
■ High Noise Immunity: V
NIH
= V
NIL
= 28% VCC (Min)
■ Power Down Protection is provided on all inputs
■ Low Noise: V
OLP
= 0.6V (typ)
■ Low Power Dissipation: I
CC
= 4 µA (Max) @ TA = 25°C
■ Pin and function compatible with 74HC573
Ordering Code:
Surface mount pack ages are also available on Tape and Reel. Specify by appending the s uffix let te r “X” to the ordering code .
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Order Number Package Number Package Description
74VHC573M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74VHC573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC573N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
D
0–D7
Data Inputs
LE Latch Enable Input
OE
3-STATE Output Enable Input
O
0–O7
3-STATE Outputs
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74VHC573
Functional Description
The VHC573 contains eight D-type latches with 3-STATE
output buffers. When the La tch En able ( LE) inpu t is HI GH,
data on the D
n
inputs enters the latches. In this co ndition
the latches are transparent, i.e., a latch output will chang e
state each time its D input ch anges. Whe n LE is L OW the
latches store the information that was present on the D
inputs, a setup time p re cedin g the HIGH- to- LO W tra nsitio n
of LE. The 3-STATE buffers are controlled by the O utput
Enable (OE
) input. When OE is LOW, the buffers are
enabled. When OE
is HIGH the buffers are in the high
impedance mode, but, this doe s not interfere wi th entering
new data into the latches.
Tr uth Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Logic Diagram
Please note that this diagram is provided o nly f or t he understanding of logic operations and shou ld not be used to estimate pro pagation delays.
Inputs Outputs
OE
LE D O
n
LHH H
LHL L
LLX O
0
HXX Z
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74VHC573
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
(Note 2)
Note 1: Absolute Maximum Ratings are valu es beyond whic h the device
may be damaged or ha ve its useful life impaire d. The datab ook specifications should be met, without exception, to ensure that the system design is
reliable over its p ower supp ly, temperature, and o utput/input loading variables. Fairchild does not recommend operation outside databook specifications.
Note 2: Unused inputs must be held HIGH or LOW They may not float.
DC Electrical Characteristics
Noise Characteristics
Note 3: Parameter gu aranteed by design.
Supply Voltage (VCC) −0.5V to +7.0V
DC Input Voltage (V
IN
) −0.5V to +7.0V
DC Output Voltage (V
OUT
) −0.5V to VCC +0.5V
Input Diode Current (I
IK
) −20 mA
Output Diode Current ±20 mA
DC Output Current (I
OUT
) ±25 mA
DC V
CC
/GND Current (ICC) ±75 mA
Storage Temperature (T
STG
) −65°C to +150°C
Lead Temperature (T
L
)
(Soldering, 10 seconds) 260°C
Supply Voltage (V
CC
)2.0V to +5.5V
Input Voltage (V
IN
)0V to +5.5V
Output Voltage (V
OUT
)0V to V
CC
Operating Temperature (T
OPR
) −40°C to +85°C
Input Rise and Fall Time (t
r
, tf)
V
CC
= 3.3V ± 0.3V 0 ∼ 100 ns/V
V
CC
= 5.0V ± 0.5V 0 ∼ 20 ns/V
Symbol Parameter
V
CC
(V)
TA = 25°CT
A
= −40°C to +85°C
Units Conditions
Min Typ Max Min Max
V
IH
HIGH Level Input 2.0 1.50 1.50
V
Voltage 3.0 − 5.5 0.7 V
CC
0.7 V
CC
V
IL
LOW Level Input 2.0 0.50 0.50
V
Voltage 3.0 − 5.5 0.3 V
CC
0.3 V
CC
V
OH
HIGH Level Output 2.0 1.9 2.0 1.9
V
VIN = V
IH
Voltage 3.0 2.9 3.0 2.9 or VILIOH = −50 µA
4.5 4.4 4.5 4.4
3.0 2.58 2.48
V
IOH = −4 mA
4.5 3.94 3.80 IOH = −8 mA
V
OL
LOW Level Output 2.0 0.0 0.1 0.1
V
VIN = V
IH
Voltage 3.0 0.0 0.1 0.1 or VILIOL = 50 µA
4.5 0.0 0.1 0.1
3.0 0.36 0.44
V
IOL = 4 mA
4.5 0.36 0.44 IOL = 8 mA
I
OZ
3-STATE Output 5.5 ±0.25 ±2.5 µAVIN = VIH or V
IL
Off-State Current V
OUT
= VCC or GND
I
IN
Input Leakage Current 0 − 5.5 ±0.1 ±1.0 µAVIN = 5.5V or GND
I
CC
Quiescent Supply Current 5.5 4.0 40.0 µAVIN = VCC or GND
Symbol Parameter
V
CC
(V)
TA = 25°C
Units Conditions
Typ Limits
V
OLP
(Note 3)
Quiet Output Maximum Dynamic V
OL
5.0 0.9 1.2 V CL = 50 pF
V
OLV
(Note 3)
Quiet Output Minimum Dynamic V
OL
5.0 −0.8 −1.0 V CL = 50 pF
V
IHD
(Note 3)
Minimum HIGH Level Dynamic Input Voltage 5.0 3.5 V CL = 50 pF
V
ILD
(Note 3)
Maximum LOW Level Dynamic Input Voltage 5.0 1.5 V CL = 50 pF
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74VHC573
AC Electrical Characteristics
Note 4: Paramete r guaranteed by desig n. t
OSLH
= |t
PLH max
− t
PLH min
|; t
OSHL
= |t
PHL max
− t
PHL min
|
Note 5: C
PD
is defined as the value of the internal equivalent capacitance w hic h is calculated from t he operating current co ns umption without loa d. Av erage
operating curren t can b e o btain ed by the equat ion: I
CC
(opr.) = CPD * VCC * fIN + ICC/8 (per Latch). The to tal CPD when n pc s . of the Latch operates can be
calculated by the equation: C
PD
(total) = 21 + 8n.
AC Operating Requirements
Symbol Parameter
V
CC
(V)
TA = 25°CT
A
= −40°C to +85°C
Units Conditions
Min Typ Max Min Max
t
PLH
Propagation Delay 3.3 ± 0.3 7.6 11.9 1.0 14.0
ns
CL = 15 pF
t
PHL
Time (LE to On) 10.1 15.4 1.0 17.5 CL = 50 pF
5.0 ± 0.5 5.0 7.7 1.0 9.0
ns
CL = 15 pF
6.5 9.7 1.0 11.0 CL = 50 pF
t
PLH
Propagation Delay 3.3 ± 0.3 7.0 11.0 1.0 13.0
ns
CL = 15 pF
t
PHL
Time (D–On) 9.5 14.5 1.0 16.5 CL = 50 pF
5.0 ± 0.5 4.5 6.8 1.0 8.0 CL = 15 pF
6.0 8.8 1.0 10.0 CL = 50 pF
t
PZL
3-STATE Output 3.3 ± 0.3 7.3 11.5 1.0 13.5
ns
RL = 1 kΩ CL = 15 pF
t
PZH
Enable Time 9.8 15.0 1.0 17.0 CL = 50 pF
5.0 ± 0.5 5.2 7.7 1.0 9.0
ns
CL = 15 pF
6.7 9.7 1.0 11.0 CL = 50 pF
t
PLZ
3-STATE Output 3.3 ± 0.3 10.7 14.5 1.0 16.5
ns
RL = 1 kΩ CL = 50 pF
t
PHZ
Disable Time 5.0 ± 0.5 6.7 9.7 1.0 11.0 CL = 50 pF
t
OSLH
Output to Output Skew 3.3 ± 0.3 1.5 1.5
ns
(Note 4) CL = 50 pF
t
OSHL
5.0 ± 0.5 1.0 1.0 CL = 50 pF
C
IN
Input Capacitance 4 10 10 pF VCC = Open
C
OUT
Output Capacitance 6 pF VCC = 5.0V
C
PD
Power Dissipation 29 pF (Note 5)
Capacitance
Symbol Parameter
V
CC
(V)
TA = 25°CT
A
= −40°C to +85°C
Units
Min Typ Max Min Max
tw(H) Minimum Pulse 3.3 ± 0.3 5.0 5.0
ns
tw(L) Width (LE) 5.0 ± 0.5 5.0 5.0
t
S
Minimum Setup Time 3.3 ± 0.3 3.5 3.5
ns
5.0 ± 0.5 3.5 3.5
t
H
Minimum Hold Time 3.3 ± 0.3 1.5 1.5
ns
5.0 ± 0.5 1.5 1.5
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74VHC573
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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74VHC573
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
74VHC573 Octal D-Type Latch with 3-STATE Outputs
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support de vices o r syst ems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided i n the labe li ng, can be re asonably expected to result in a significant injury to the
user.
2. A critica l compo nent in any componen t of a life s uppor t
device or system whose failu re to perform can b e reasonably expected to c ause th e fa i lure of the li fe s upp or t
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
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