Datasheet 74VHC573 Datasheet (SGS Thomson Microelectronics)



74VHC573

OCTAL D-TYPE LATCH

WITH 3 STATE OUTPUT NON INVERTING

■ HIGHSPEED:t

■ LOW POWER DISSIPATION:

=4 µA (MAX.) at TA=25oC

I

CC

■ HIGHNOISEIMMUNITY:

V

NIH=VNIL

■ POWERDOWNPROTECTIONON INPUTS

■ SYMMETRICALOUTPUTIMPEDANCE:

|=IOL=8 mA(MIN)

|I

OH

■ BALANCEDPROPAGATIONDELAYS:

t

≅ t

PLH

■ OPERATINGVOLTAGERANGE:

V

(OPR)= 2Vto5.5V

CC

■ PINANDFUNCTION COMPATIBLEWITH

=28%VCC(MIN.)

PHL

=5.0ns(TYP.)atVCC=5V

PD

74SERIES573

■ IMPROVEDLATCH-UPIMMUNITY

■ LOWNOISE:V

= 0.9V(Max.)

OLP

DESCRIPTION

The 74VHC573 is an advanced high-speed
CMOS OCTAL D-TYPE LATCH with 3 STATE
OUTPUT NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiringC

2

MOStechnology.

This 8 bit D-Type latch is controlled by a latch
enable input (LE) and an output enable input
(OE).

While the LE input is held at a high level, the Q

M

(Micro Package)

(TSSOPPackage)

T

ORDERCODES :

74VHC573M 74VHC573T

outputswill follow thedata inputs precisely.
When the LE is taken low, the Q outputs will be

latchedpreciselyat thelogic level of D input data.
While the (OE) input is low, the 8 outputs will be

in a normal logic state (high or low logic level)
and while high level the outputs will be in a high
impedancestate.

Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.

All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.

PIN CONNECTION AND IEC LOGICSYMBOLS

June 1999

1/10

74VHC573

INPUT EQUIVALENTCIRCUIT PIN DESCRIPTION

PI N No SYMB OL NAME AND FU NCTION

1 OE 3 State Output Enable

2, 3, 4,
5, 6, 7,

8, 9

12, 13, 14,
15, 16, 17,

18, 19

11 LE Latch Enable

10 GND Ground (0V)
20 V

TRUTH TABLE

INPUTS OUTPUTS

OE LE D Q

HXXZ

L L X NO CHANGE *
LHLL
LHHH

X:Don’tcare
Z:Highimpedance
*Qoutputsarelatched atthetime whentheLEinputistakenlowlogiclevel.

D0 to D7 Data Inputs

Q0 to Q7 3 State Latch Outputs

CC

Input (Active LOW)

Input

Positive Supply Voltage

LOGICDIAGRAM

2/10

74VHC573

ABSOLUTE MAXIMUM RATINGS

Symb o l Paramet er Val u e Uni t

V

V

V

I

I

OK

I

or I

I

CC

T

T

AbsoluteMaximumRatingsarethosevaluesbeyond whichdamage tothedevicemayoccur.Functionaloperationunderthese conditionisnotimplied.

RECOMMENDEDOPERATINGCONDITIONS

Symb o l Paramet er Value Un it

V

V

V

T

dt/dv

1)VINfrom30%to70%ofV

Supply Voltage -0.5 to +7.0 V

CC

DC Input Voltage -0.5 to +7.0 V

I

DC Output Voltage -0.5 to VCC+ 0.5 V

O

DC Input Diode Current - 20 mA

IK

DC Output Diode Current ± 20 mA
DC Output Current

O

DC VCCor Ground Current

GND

Storage Temperature -65 to +150

stg

Lead Temperature (10 sec) 300

L

Supply Voltage 2.0 to 5.5 V

CC

Input Voltage 0 to 5.5 V

I

Output Voltage 0 to V

O

Operating Temperature -40 to +85

op

(V

CC
CC

=3.3±0.3V)
=5.0±0.5V)

Input Rise and Fall Time (see note 1) (V

CC

25 mA

±

75 mA

±

CC

0 to 100

0to20

o

C

o

C

V

o

C

ns/V
ns/V

DC SPECIFICATIONS

Symb o l Para met er Test C o n diti ons Val u e Uni t

=25oC -40 to 85oC

V

CC

(V)

High Level Input

V

IH

Voltage

V

Low Level Input

IL

Voltage

V

High Level Output

OH

Voltage

2.0 1.5 1.5

3.0 to 5.5 0.7V

2.0 0.5 0.5

3.0 to 5.5 0.3V

2.0 IO=-50µA 1.9 2.0 1.9

3.0 I

4.5 I

3.0 I

4.5 I

Low Level Output

V

OL

Voltage

2.0 IO=50 µ A 0.0 0.1 0.1

3.0 I

4.5 I

3.0 I

4.5 I

High Impedance

I

OZ

Output Leakage

5.5

VO=VCCor GND

Current
Input Leakage Current 0 to 5.5 VI= 5.5V or GND

I

I

Quiescent Supply

I

CC

5.5 VI=VCCorGND 4 40

Current

=-50µA 2.9 3.0 2.9

O

=-50 µA 4.4 4.5 4.4

O

=-4 mA 2.58 2.48

O

=-8 mA 3.94 3.8

O

=50µA 0.0 0.1 0.1

O

=50 µA 0.0 0.1 0.1

O

=4 mA 0.36 0.44

O

=8 mA 0.36 0.44

O

VI=VIHor V

IL

T

A

Min. Typ. Max. Min. Max.

CC

0.7V

CC

0.3V

CC

±0.25 ±2.5 µA

0.1

±

1.0

±

CC

µ
µ

V

V

V

V

A
A

3/10

74VHC573

AC ELECTRICAL CHARACTERISTICS

(Inputt

r=tf

=3 ns)

Symbol Parameter Test Condition Value Unit

t

Propagation Delay

PLH

t

Time (LE to Q)

PHL

t

Propagation Delay

PLH

t

Time (D to Q)

PHL

Output EnableTime 3.3

t

PZL

t

PZH

t

Output Disable Time 3.3

PLZ

t

PHZ

t

Pulse Width (LE) HIGH 3.3

w

t

Setup Time D to LE

s

HIGH or LOW
Hold Time D to LE

t

h

HIGH or LOW

t
t

(*) Voltagerangeis 3.3V± 0.3V
(**) Voltagerangeis 5V ± 0.5V
Note1:Parameterguaranteedbydesign.t

Output to Output Skew

OSLH

Time (note 1)

OSHL

soLH

V

(V)

3.3

3.3

5.0

5.0

3.3

3.3

5.0

5.0

3.3

5.0

5.0

5.0

5.0

3.3

5.0

3.3

5.0

3.3

5.0

=|t

pLHm-tpLHn

CC

(**)
(**)

(**)
(**)

(**)
(**)

(**)

(**)

(**)

(**)

(**)

C

L

(pF)

(*)

15 7.6 11.9 1.0 14.0

(*)

50 10.1 15.4 1.0 17.5

T

=25oC -40 to 85oC

A

Min. Typ. Max. Min. Max.

15 5.0 7.7 1.0 9.0
50 6.5 9.7 1.0 11.0

(*)

15 7.0 11.0 1.0 13.0

(*)

50 9.5 14.5 1.0 16.5
15 4.5 6.8 1.0 8.0
50 6.0 8.8 1.0 10.0

(*)

15 RL=1KΩ 7.3 11.5 1.0 13.5

(*)

50 RL=1KΩ 9.8 15.0 1.0 17.0
15 RL=1KΩ 5.2 7.7 1.0 9.0
50 RL=1KΩ 6.7 9.7 1.0 11.0

(*)

50 RL=1K

Ω

10.7 14.5 1.0 16.5

50 RL=1KΩ 6.7 9.7 1.0 11

(*)

5.0 5.0

5.0 5.0

(*)

3.5 3.5

3.5 3.5

(*)

1.5 1.5

1.5 1.5

(*)

50 1.5 1.5 ns
50

|,t

soHL

=|t

pHLm-tpHLn

|

1.0 1.0

ns

ns

ns

ns

ns

ns

ns

CAPACITIVE CHARACTERISTICS

Symb o l Para met er Test C o n diti ons Val u e Uni t

=25oC -40 to 85oC

T

A

Min. Typ. Max. Min. Max.

Input Capacitance 4 10 10

C

IN

C

Output Capacitance 6 pF

OUT

Power Dissipation

C

PD

29 pF

Capacitance (note 1)

1)CPDisdefinedasthevalueoftheIC’sinternalequivalentcapacitance whichis calculated fromtheoperatingcurrent consumption withoutload. (Referto
TestCircuit).Average operatingcurrentcanbeobtainedbythefollowingequation.I

(opr)= CPD• VCC• fIN+ICC/8(perLatch)

CC

4/10

pF

74VHC573

DYNAMICSWITCHING CHARACTERISTICS

Symb o l Para met er Test C o n diti ons Val u e Uni t

T

V

CC

(V)

V
V

V

Dynamic Low Voltage

OLP

Quiet Output (note 1, 2)

OLV

Dynamic High Voltage

IHD

5.0

5.0 3.5

C

L

=50pF

Min. Typ. Max. Min. Max.

Input (note 1, 3)

V

Dynamic Low Voltage

ILD

5.0 1.5

Input (note 1, 3)

1)Worst casepackage.

2)Maxnumberofoutputsdefinedas(n).Datainputsaredriven 0Vto5.0V,(n-1)outputsswitching andoneoutputatGND.

3)Maxnumberofdatainputs(n)switching.(n-1)switching0Vto5.0V. Inputsunder testswitching:5.0Vtothreshold (V

TESTCIRCUIT

=25oC -40 to 85oC

A

0.6 0.9

-0.9 -0.6

),0Vtothreshold(V

ILD

),f=1MHz.

IHD

V

TEST SWITCH

t

PLH,tPHL

t

PZL,tPLZ

t

PZH,tPHZ

CL= 15/50 pForequivalent (includes jig and probecapacitance)
R

=1KΩorequivalent

L=R1

R

ofpulsegenerator (typically50Ω)

T=ZOUT

Open

V

CC

GND

5/10

74VHC573

WAVEFORM1: LETO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH,
Dn TO LE SETUP AND HOLD TIMES(f=1MHz;50% duty cycle)

6/10

74VHC573

WAVEFORM2: OUTPUTENABLE AND DISABLE TIMES

(f=1MHz;50% duty cycle)

WAVEFORM3: PROPAGATIONDELAY TIME (f=1MHz; 50% duty cycle)

7/10

74VHC573

SO-20 MECHANICAL DATA

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

A 2.65 0.104
a1 0.10 0.20 0.004 0.007
a2 2.45 0.096

b 0.35 0.49 0.013 0.019
b1 0.23 0.32 0.009 0.012

C 0.50 0.020

c1 45 (typ.)

D 12.60 13.00 0.496 0.512

E 10.00 10.65 0.393 0.419

e 1.27 0.050
e3 11.43 0.450

F 7.40 7.60 0.291 0.299

L 0.50 1.27 0.19 0.050

M 0.75 0.029

S 8 (max.)

mm inch

8/10

P013L

TSSOP20 MECHANICAL DATA

74VHC573

DIM.

mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 1.1 0.433

A1 0.05 0.10 0.15 0.002 0.004 0.006

A2 0.85 0.9 0.95 0.335 0.354 0.374

b 0.19 0.30 0.0075 0.0118

c 0.09 0.2 0.0035 0.0079

D 6.4 6.5 6.6 0.252 0.256 0.260

E 6.25 6.4 6.5 0.246 0.252 0.256

E1 4.3 4.4 4.48 0.169 0.173 0.176

e 0.65 BSC 0.0256BSC

K0

o

o

4

o

8

o

0

o

4

L 0.50 0.60 0.70 0.020 0.024 0.028

o

8

A2

A

A1

PIN 1 IDENTIFICATION

b

e

K

c

L

E

D

E1

1

9/10

74VHC573

Information furnished is believed to beaccurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in thispublication are
subject tochange without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a trademark of STMicroelectronics

1999 STMicroelectronics – Printed in Italy – All Rights Reserved

STMicroelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China -France - Germany - Italy - Japan - Korea - Malaysia -Malta - Mexico - Morocco - The Netherlands -

Singapore - Spain -Sweden - Switzerland - Taiwan - Thailand - UnitedKingdom - U.S.A.

http://www.st.com

.

10/10