Datasheet 74VHC4316N, 74VHC4316MX, 74VHC4316MTCX, 74VHC4316MTC, 74VHC4316M Datasheet (Fairchild Semiconductor)
...Page 1
April 1994
Revised April 1999
74VHC4316 Quad Analog Switch with Level Tr anslator
© 1999 Fairchild Semiconductor Corporation DS011678.prf www.fairchildsemi.com
74VHC4316
Quad Analog Switch with Level Translator
General Description
These devices are digitally controlled analog switches
implemented in adva nced silicon-gate CMOS tech nology.
These switches have low “on” resistance and low “off” leakages. They are bidirectional switches, thus any analog
input may be used as an output and vice-versa. Three supply pins are provided on the 4316 to implement a level
translator which ena bles this circuit to op erate wi th 0V–6V
logic levels and up to ±6V analog switch levels. The 4316
also has a common enable input in addition to each
switch's control which when HIGH will disable all switches
to their off state. All analog inputs and ou tputs and digital
inputs are protecte d from electrostatic damage by diodes
to V
CC
and ground.
Features
■ Typical switch enable time: 20 ns
■ Wide analog input voltage range: ±6V
■ Low “on” resistance: 50 typ. (V
CC−VEE
= 4.5V)
30 typ. (V
CC−VEE
= 9V)
■ Low quiescent current: 80 µA maximum (74VHC)
■ Matched switch characteristics
■ Individual switch controls plus a common enable
■ Pin functional compatible with 74HC4316
Ordering Code:
Surface mount pack ages are also available on Tape and Reel. Spec if y by appending the suffix letter “X ” to th e ordering code.
Truth Table Connection Diagram
Top View
Logic Diagram
Order Number Package Number Package Description
74VHC4316M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74VHC4316WM M16B 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74VHC4316MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC4316N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs Switch
E
CTL I/O–O/I
HX “OFF”
LL“OFF”
LH “ON”
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74VHC4316
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referen c ed to ground.
Note 3: Power Dissipation temper ature dera ting — plas tic “N” packa ge: −
12 mW/°C from 65 °C to 85°C.
DC Electrical Characteristics (Note 4)
Note 4: For a power supply of 5V ±10% the worst case on resistances (RON) occurs for VHC a t 4. 5V. Thus the 4.5V values should be used when designi ng
with this supply. Worst case V
IH
and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst cas e leakage current occurs
for CMOS at the higher voltage and so the 5.5V values should be used.
Note 5: At supply voltag es (V
CC–VEE
) approaching 2V the analo g switch on resist ance becom es extr emely non- linear. Therefore it is recom mended that
these devices be us ed to transmit digital only w hen using these supply voltages.
Supply Voltage (VCC) −0.5 to +7.5V
Supply Voltage (V
EE
) +0.5 to −7.5V
DC Control Input Voltage (V
IN
) −1.5 to VCC+1.5V
DC Switch I/O Voltage (V
IO
)V
EE
−0.5 to VCC+0.5V
Clamp Diode Current (I
IK
, IOK) ±20 mA
DC Output Current, per pin (I
OUT
) ±25 mA
DC V
CC
or GND Current, per pin (ICC) ±50 mA
Storage Temperature Range (T
STG
) −65°C to +150°C
Power Dissipation (P
D
) (Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (T
L
)
(Soldering 10 seconds) 260°C
Min Max Units
Supply Voltage (V
CC
)26V
Supply Voltage (V
EE
)0−6V
DC Input or Output Voltage 0 V
CC
V
(V
IN
, V
OUT
)
Operating Temperature Range (T
A
) −40 +85 °C
Input Rise or Fall Times
(t
r
, tf)VCC = 2.0V 1000 ns
V
CC
= 4.5V 500 ns
V
CC
= 6.0V 400 ns
V
CC
= 12.0V 250 ns
Symbol Parameter Conditions
V
EE
V
CC
TA = 25°CTA = −40°C to +85°C
Units
Typ Guaranteed Limits
V
IH
Minimum HIGH 2.0V 1.5 1.5
Level Input 4.5V 3.15 3.15 V
Voltage 6.0V 4.2 4.2
V
IL
Maximum LOW 2.0V 0.5 0.5
Level Input 4.5V 1.35 1.35 V
Voltage 6.0V 1.8 1.8
R
ON
Minimum “ON” V
CTL
= VIH, GND 4.5V 100 170 200 Ω
Resistance IS = 2.0 mA −4.5V 4.5V 40 85 105
(Note 5) VIS = VCC to V
EE
−6.0V 6.0V 30 70 85
(
Figure 1
)
V
CTL
= VIH, GND 2.0V 100 180 215
IS = 2.0 mA GND 4.5V 40 80 100
VIS = VCC or V
EE
−4.5V 4.5V 50 60 75
(
Figure 1
) −6.0V 6.0V 20 40 60
R
ON
Maximum “ON” V
CTL
= V
IH
GND 4.5V 10 15 20
Resistance VIS = VCC to V
EE
−4.5V 4.5V 5 10 15 Ω
Matching −6.0V 6.0V 5 10 15
I
IN
Maximum Control VIN = VCC or GND GND 6.0V ±0.1 ±1.0 µA
Input Current
I
IZ
Maximum Switch VOS = VCC or V
EE
“OFF” Leakage VIS = VEE or V
CC
GND 6.0V ±30 ±300 nA
Current V
CTL
= V
IL
−6.0V 6.0V ±50 ±500
(
Figure 2
)
I
IZ
Maximum Switch VIS = VCC to V
EE
“ON” Leakage V
CTL
= VIH, GND 6.0V ±20 ±75 nA
Current VOS = OPEN −6.0V 6.0V ±30 ±150
(
Figure 3
)
I
CC
Maximum Quiescent VIN = VCC or GND GND 6.0V 1.0 10 µA
Supply Current I
OUT
= 0 µA −6.0V 6.0V 4.0 40
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74VHC4316
AC Electrical Characteristics
VCC = 2.0V − 6.0V, VEE = 0V − 6V, CL = 50 pF unless otherwise specified
Note 6: Adjust 0 dBm for f = 1 kHz (Null RL/Ron Attenuation).
Note 7: V
IS
is centered at VCC–VEE/2.
Note 8: Adjust for 0 dBm.
Symbol Parameter Conditions
V
EE
V
CC
TA=+25°CTA=−40°C to +85°C
Units
Typ Guaranteed Limits
t
PHL
, t
PLH
Maximum Propagation GND 3.3V 15 30 37
Delay Switch In to GND 4.5V 5 10 13 ns
Out −4.5V 4.5V 4 8 12
−6.0V 6.0V 3 7 11
t
PZL
, t
PZH
Maximum Switch Turn RL = 1 kΩ GND 3.3V 25 97 120
“ON” Delay GND 4.5V 20 35 43 ns
(Control) −4.5V 4.5V 15 32 39
−6.0V 6.0V 14 30 37
t
PHZ
, t
PLZ
Maximum Switch Turn RL = 1 kΩ GND 3.3V 35 145 180
“OFF” Delay GND 4.5V 25 50 63 ns
(Control) −4.5V 4.5V 20 44 55
−6.0V 6.0V 20 44 55
t
PZL
, t
PZH
Maximum Switch GND 3.3V 27 120 150
Turn “ON” Delay GND 4.5V 20 41 52 ns
(Enable) −4.5V 4.5V 19 38 48
−6.0V 6.0V 18 36 45
t
PLZ
, t
PHZ
Maximum Switch GND 3.3V 42 155 190
Turn “OFF” Delay GND 4.5V 28 53 67 ns
(Enable) −4.5V 4.5V 23 47 59
−6.0V 6.0V 21 47 59
Minimum Frequency RL = 600Ω, VIS = 2V
PP
0V 4.5 40
Response (
Figure 7
)at (VCC–VEE/2) −4.5V 4.5V 100 MHz
20 log (VOS/VIS)= −3 dB (Note 6)(Note 7)
Control to Switch RL = 600Ω, f = 1 MHz 0V 4.5V 100
Feedthrough Noise CL = 50 pF −4.5V 4.5V 250 mV
(
Figure 8
) (Note 7)(Note 8)
Crosstalk Between RL = 600Ω, f = 1 MHz 0V 4.5V −52
any Two Switches −4.5V 4.5V −50 dB
(
Figure 9
)
Switch OFF Signal RL = 600Ω, f = 1 MHz
Feedthrough V
CTL
= V
IL
0V 4.5V −42 dB
Isolation −4.5V 4.5V −44
(
Figure 10
) (Note 7)(Note 8)
THD Sinewave Harmonic RL = 10 KΩ, CL = 50 pF,
Distortion f = 1 KHz %
(
Figure 11
)V
IS
= 4 VPP0V 4.5V 0.013
VIS = 8 VPP−4.5V 4.5V 0.008
C
IN
Maximum Control 5 pF
Input Capacitance
C
IN
Maximum Switch 35 pF
Input Capacitance
C
IN
Maximum Feedthrough V
CTL
= GND 0.5 pF
Capacitance
C
PD
Power Dissipation 15 pF
Capacitance
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74VHC4316
AC Test Circuits and Switching Time Waveforms
FIGURE 1. “ON” Resistance FIGURE 2. “OFF” Channel Leakage Current
FIGURE 3. “ON” Channel Leakage Current
FIGURE 4. t
PHL
, t
PLH
Propagation Delay Time Signal Input to Signal Output
FIGURE 5. t
PZL
, t
PLZ
Propagation Delay Time Control to Signal Output
FIGURE 6. t
PZH
, t
PHZ
Propagation Delay Time Control to Signal Output
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74VHC4316
AC Test Circuits and Switching Time Waveforms (Continued)
FIGURE 7. Frequenc y Re sp on se
FIGURE 8. Crosstalk: Control Input to Signal Output
FIGURE 9. Cros stalk between Any Two Switches
FIGURE 10. Switch OFF Signal Feedthrough Isolation FIGURE 11. Sinewave Distortion
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74VHC4316
Typical Performance Characteristics
Typical “ON” Resistance Typical Crosstalk between
Any Two Switches
Typical Frequenc y Response
Special Considerations
In certain appli catio ns the external load-resistor cu rr ent may include both VCC and signal line com pon en ts. To avoid drawing V
CC
current when switc h current flows in to the anal og switch input pins, the volt age drop across th e switch must not
exceed 0.6V (calculated from the ON resistance).
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74VHC4316
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M16B
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74VHC4316
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
74VHC4316 Quad Analog Switch with Level Tr anslator
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided i n the labe li ng, can be re asonably expected to result in a significant injury to the
user.
2. A critical componen t in any com ponent o f a l ife supp ort
device or system whose failu re to perform can b e reasonably expected to c ause th e fa i lure of the li fe s upp or t
device or system, or to affect its safety or effectiveness.
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
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