Datasheet 74VHC4046N, 74VHC4046MX, 74VHC4046MTCX, 74VHC4046MTC, 74VHC4046M Datasheet (Fairchild Semiconductor)
...Page 1
April 1994
Revised April 1999
74VHC4046 CMOS Phase Lock Loop
© 1999 Fairchild Semiconductor Corporation DS011675.prf www.fairchildsemi.com
74VHC4046
CMOS Phase Lock Loop
General Description
The VHC4046 is a low power phase lock loop utilizing
advanced silicon-gate CMOS technology to obtain high frequency operation bot h in the phase com parator and VCO
sections. This device contai ns a low power linear voltage
controlled oscillator (VCO), a source follower, and three
phase comparators. The thre e phase comparators ha ve a
common signal input and a common comparator input. The
signal input has a self biasing ampli fier allowing sign als to
be either capacitively co upled to the phase comparators
with a small signal or direc tly coupled with standard inp ut
logic levels. This device is similar to the CD 4046 except
that the Zener diode of the metal gate CM OS device has
been replaced with a third phase comparator.
Phase Comparator I is an exclusive OR (XOR) gate. It provides a digital error signal that maintai ns a 90 phase shift
between the VCO’s center freque ncy and the input signal
(50% duty cycle input waveforms). This ph ase detector is
more susceptible to locking onto harmonics of the input frequency than phase comparator I, but pr ovi de s bet ter n oi se
rejection.
Phase comparator III is an S R fli p -flop ga te. It can b e used
to provide the phase co mp ara tor fun cti on s an d is similar to
the first comparator in performance.
Phase comparator II is an edge se nsitive digit al seque ntial
network. Two signal outputs are provided, a comparator
output and a phase pulse output. The comparator output is
a 3-STA TE output that provides a signal that locks the VCO
output signal to the i n pu t sign al with 0 phase shift b etwe en
them. This comparator is more susceptible to noise throw-
ing the loop out of lock, but is less likely to lock onto h armonics than the other two comparators.
In a typical application a ny one of the three comparator s
feed an external filter network which in tur n f eed s th e VCO
input. This input is a very high impedance CMOS input
which also drives the source follower. The VCO’s operating
frequency is set by three external components co nnected
to the C1
A
, C1B, R1 and R2 pins. An inhibit pi n is p rovi ded
to disable the VCO and the source follower, providing a
method of putting the IC in a low power state.
The source follower is a MOS transistor whose gate is connected to the VCO input and whose drain connects the
Demodulator output. This output normally i s used by tying
a resistor from pin 10 to ground , and provi des a means o f
looking at the VCO input without loading down modifying
the characteristics of the PLL filter.
Features
■ Low dynamic power consumption: (V
CC
= 4.5V)
■ Maximum VCO operating frequency: 12 MHz
(V
CC
= 4.5V)
■ Fast comparator response time (V
CC
= 4.5V)
Comparator I: 25 ns
Comparator II: 30 ns
Comparator III: 25 ns
■ VCO has high linearity and high temperature stability
■ Pin and function compatible with the 74HC4046
Ordering Code:
Surface mount pack ages are also available on Tape and Reel. Specify by appending the s uffix let te r “X” to the ordering code .
Order Number Package Number Package Description
74VHC4046M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74VHC4046MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC4046N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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74VHC4046
Connection Diagram
Block Diagram
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74VHC4046
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Note 1: Maximum Ratings are those values beyond which damage to the
device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derat ing — plastic “N” package: −
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics (Note 4)
Note 4: For a pow er supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for VHC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case V
IH
and VIL occur at V
CC
= 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3 .8 5V.) The worst c as e leakage cur-
rent (I
IN
, ICC, and IOZ) occur for CMOS at the higher voltage and so th e 6. 0V values should be used.
Supply Voltage (VCC) −0.5 to + 7.0V
DC Input Voltage (V
IN
) −1.5 to VCC +1.5V
DC Output Voltage (V
OUT
) −0.5 to VCC + 0.5V
Clamp Diode Current (I
IK
, IOK) ±20 mA
DC Output Current per pin (I
OUT
) ±25 mA
DC V
CC
or GND Current,
per pin (I
CC
) ±50 mA
Storage Temperature Range (T
STG
) −65°C +150°C
Power Dissipation (P
D
)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (T
L
)
(Soldering 10 seconds) 260°C
Min Max Units
Supply Voltage (V
CC
)26V
DC Input or Output Voltage 0 V
CC
V
(V
IN
, V
OUT
)
Operating Temperature Range (T
A
) −40 +85 °C
Input Rise or Fall Times
(t
r
, tf)V
CC
= 2.0V 1000 ns
V
CC
= 4.5V 500 ns
V
CC
= 6.0V 400 ns
Symbol Parameter Conditions
V
CC
TA=25°CTA=−40 to 85°C
Units
Typ Gu a ra nt eed Lim its
V
IH
Minimum HIGH Level 2.0V 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 V
6.0V 4.2 4.2 V
V
IL
Maximum LOW Level 2.0V 0.5 0.5 V
Input Voltage 4.5V 1.35 1.35 V
6.0V 1.8 1.8 V
V
OH
Minimum HIGH Level V
IN
= VIH or V
IL
2.0V 2.0 1.9 1.9 V
Output Voltage |I
OUT
| ≤ 20 µA 4.5V 4.5 4.4 4.4 V
6.0V 6.0 5.9 5.9 V
V
IN
= VIH or V
IL
|I
OUT
| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 V
|I
OUT
| ≤ 5.2 mA 6.0V 5.7 5.48 5.34 V
V
OL
Maximum LOW Level V
IN
= VIH or V
IL
2.0V 0 0.1 0.1 V
Output Voltage |I
OUT
| ≤ 20 µA4.5V00.10.1V
6.0V 0 0.1 0.1 V
V
IN
= VIH or V
IL
|I
OUT
| ≤ 4.0 mA 4.5V 0.2 0.26 0.33 V
|I
OUT
| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 V
I
IN
Maximum Input Current (Pins 3,5,9) V
IN
= VCC or GND 6.0V ±0.1 ±1.0 µA
I
IN
Maximum Input Current (Pin 14) V
IN
= VCC or GND 6.0V 20 50 80 µA
I
OZ
Maximum 3-STATE Output V
OUT
= VCC or GND 6.0V ±0.25 ±2.5 µA
Leakage Current (Pin 13)
I
CC
Maximum Quiescent Supply V
IN
= VCC or GND 6.0V 30 40 65 µA
Current I
OUT
= 0 µA
VIN = VCC or GND 6.0V 600 750 1200 µA
Pin 14 Open
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74VHC4046
AC Electrical Characteristics
V
CC
= 2.0 to 6.0V, CL = 50 pF, tr = t
f
= 6 ns (unless otherwise specified.)
Symbol Parameters Conditions
V
CC
TA=25C TA=−40 to 85°C
Units
Typ Guaranteed Limits
AC Coupled C (series) = 100 pF 2.0V 25 100 150 mV
Input Sensitivity, f
IN
= 500 kHz 4.5V 50 150 200 mV
Signal In 6.0V 135 250 300 mV
tr, t
f
Maximum Output 2.0V 30 75 95 ns
Rise and Fall Time 4.5V 9 15 19 ns
6.0V 8 12 15 ns
C
IN
Maximum Input 7 pF
Capacitance
Phase Comparator I
t
PHL
, t
PLH
Maximum Propagation 3.3V 65 117 146 ns
Delay 4.5V 25 40 50 ns
6.0V 20 34 43 ns
Phase Comparator II
t
PZL
Maximum 3-STATE 3.3V 75 130 160 ns
Enable Time 4.5V 25 45 56 ns
6.0V 22 38 48 ns
t
PZH
, t
PHZ
Maximum 3-STATE 3.3V 88 140 175 ns
Enable Time 4.5V 30 48 60 ns
6.0V 25 41 51 ns
t
PLZ
Maximum 3-STATE 3.3V 90 140 175 ns
Disable Time 4.5V 32 48 60 ns
6.0V 28 41 51 ns
t
PHL
, t
PLH
Maximum Propagation 3.3V 100 146 180 ns
Delay HIGH-to-LOW 4.5V 34 50 63 ns
to Phase Pulses 6.0V 27 43 53 ns
Phase Comparator III
t
PHL
, t
PLH
Maximum Propagation 3.3V 75 117 146 ns
Delay 4.5V 25 40 50 ns
6.0V 22 34 43 ns
C
PD
Maximum Power All Comparators 130 pF
Dissipation VIN = VCC and GND
Capacitance
Voltage Controlled Oscillator (Specified to operate from V
CC
= 3.0V to 6.0V)
f
MAX
Maximum C1 = 50 pF
Operating R1 = 100Ω 4.5V 7 4.5 MHz
Frequency R2 = ∞ 6.0V 11 7 MHz
VCOin = V
CC
C1 = 0 pF 4.5V 12 MHz
R1 = 100Ω 6.0 14 MHz
VCOin = V
CC
Duty Cycle 50 %
Demodulator Output
Offset Voltage Rs = 20 kΩ 4.5V 0.75 1.3 1.5 V
VCOin–V
dem
Offset Rs = 20 kΩ 4.5V
Variation VCOin = 1.75V 0.65 V
2.25V 0.1
2.75V 0.75
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74VHC4046
Typical Performance Characteristics
Typical Center Frequency
vs R
1
, C1VCC = 4.5V
Typical Center Frequency
vs R1, C1VCC = 6V
Typical Offset Frequency
vs R
2
, C1VCC = 4.5V
Typical Offset Frequency
vs R2, C1VCC = 6V
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74VHC4046
Typical Performance Characteristics (Continued)
VHC4046 Typical VCO Power Dissipation
@ Center Frequency vs R
1
VHC4046 Typical VCO Power
Dissipation @ f
MIN
vs R
2
VHC4046 VCO
in
vs f
OUTVCC
= 4.5V VHC4046 VCOin vs f
OUTVCC
= 4.5V
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74VHC4046
Typical Performance Characteristics (Continued)
VHC4046 VCO
out
vs
Temperature V
CC
= 4.5V
VHC4046 VCO
out
vs
Temperature V
CC
= 6V
VHC4046 Typical Source Follower
Power Dissipation vs RS
Typical f
MAX/fMIN
vs R2/R
1
VCC = 4.5V & 6V f
MAX/fMIN
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74VHC4046
Typical Performance Characteristics (Continued)
VHC4046 Typical VCO Linearity vs R
1
& C
1
VHC4046 Typical VCO Linearity vs R1 & C
1
VCO WITHOUT OFFSET
R
2
= ∞
VCO WITH OFFSET
Comparator I Comparator II & III
R
2
=∞ R2≠∞ R2=∞ R2≠∞
–Given: f
O
–Given: fO and f
L
–Given: f
MAX
–Given: f
MIN
and f
MAX
–Use fO with curve titled –Calculate f
MIN
from the –Calculate fO from the –Use f
MIN
with curve titled
center frequency vs R
1
, C equation f
MIN
= fO − f
L
equation fO = f
MAX
/2 offset frequency vs R2,
to determine R
1
and C
1
–Use f
MIN
with curve titled –Use fO with curve titled C to determine R2 and C
1
offset frequency vs R2, C center frequency vs R1, C –Calculate f
MAX/fMIN
to determine R2 and C
1
to determine R1 and C
1
–Use f
MAX/fMIN
with curve
–Calculate f
MAX/fMIN
from titled f
MAX/fMIN
vs R2/R
1
the equation f
MAX/fMIN
= to determine ratio R2/R
1
fO + fL/fO − f
L
to obtain R
1
–Use f
MAX/fMIN
with curve
titled f
MAX/fMIN
vs R2/R
1
to determine ratio R2/R
1
to obtain R
1
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74VHC4046
Detailed Circuit Description
VOLTAGE CONTROLLED OSCILLATOR/SOURCE
FOLLOWER
The VCO requires two or three external components to
operate. These are R
1
, R2, C1. Resistor R1 and capacitor
C
1
are selected to d etermine the center frequency of the
VCO. R
1
controls the lock range. As R1’s resistance
decreases the range of f
MIN
to f
MAX
increases. Thus the
VCO’s gain decreases. As C
1
is changed the offset (if
used) of R
2
, and the center fre quency is changed. (See
typical performance curves) R
2
can be used to set the off-
set frequency with 0V at VCO input. If R
2
is omitted the
VCO range is from 0Hz. As R
2
is decreased the offset fre-
quency is increased. The effect of R
2
is shown in the
design information table an d typical performance curves.
By increasing the value of R
2
the lock range of the PLL is
offset above 0Hz and the gain (Volts/rad.) does not
change. In general, when offset is desired, R
2
and C
1
should be chosen first, and then R1 should be chosen to
obtain the proper center frequency.
FIGURE 1. Logic Diagram for VCO
Internally the resi stors set a curren t in a curr ent mirror as
shown in
Figure 1
. The mirrored curre nt drive s o ne side of
the capacitor once the capacitor charges up to the th reshold of the Schmitt Trigger the oscillator logic flips the
capacitor over and causes th e mirror to charge the opposite side of the capacitor. The output from the inter na l logic
is then taken to pin 4.
The input to the VCO is a very high impedance CMOS
input and so it will not load down the loop filter, easing the
filters design. In order t o make signals at the VCO input
accessible without degrading the loop performance a
source follower transistor is provided. This transistor can
be used by connecting a resistor to groun d and its drain
output will follow the VCO input signal.
An inhibit signal is provide d to allow disabling of th e VCO
and the source follower. This is useful if the internal VCO is
not being used. A l ogic high on inhibit disab les the VCO
and source follower.
The output of th e VCO is a standard high speed CMOS
output with an equivalent LSTTL fanout of 10. The VCO
output is approximately a square wave. This output can
either directly feed the com pa rat or in pu t of t he phase comparators or feed ex ternal prescalers (counters) to enable
frequency synthesis.
PHASE COMPARATORS
All three phase comparators share two inputs, Signal In
and Comparator In. Th e Signal In has a special DC bias
network that enable s AC coupling of input signals. If the
signals are not AC coup led then this input requires logic
levels the same as standard 74VHC. The Comparator input
is a standard digital input. Both i nput structur es are shown
in
Figure 2
.
The outputs of the se com parato rs are essent ially sta ndard
74VHC voltage outputs. (Comparator II is 3-STATE.)
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74VHC4046
FIGURE 2. Logic Diagram for Phase Comparator I and the Common Input Circuit for All Three Comparators
FIGURE 3. Typical Phase Comparator I. Waveforms
Thus in normal oper ation V
CC
and ground voltage le vels
are fed to the loop filter. This differs from some phase
detectors which supply a current output to the loop filter
and this should be considered in the design. (The CD4046
also provides a voltage.)
Figure 4
shows the state tables for all three comparators.
PHASE COMPARATOR I
This comparator is a simple XOR gate similar to the
74HC86, and its oper ation is similar to an over driven balanced modulator. To maximize lock range the input frequencies must have a 50% duty cycle. Typical input and
output waveforms are shown in
Figure 3
. The output of the
phase detector feeds the loop filter which averages the output voltage. The frequency range upon which the PLL will
lock onto if initially out of lock is defined as the capture
range. The capture range for phase detector I is dependent
on the loop filter employe d. The capture range ca n be as
large as the lock range which is equal to the VCO frequency range.
To see how the detector operates refer to
Figure 3
. When
two square wave inp uts are ap plied to thi s compar ator, an
output waveform whose duty cycle is dependent on the
phase difference betwe en the two signals results . As the
phase difference increases th e o utpu t du ty cyc l e incr ea ses
and the voltage after the loop filter increases. Thus in order
to achieve lock, when th e PLL input frequency increases
the VCO input volta ge mu st incre ase and the p hase d ifference between comparator in and signal in will increase. At
an input frequency equal f
MIN
, the VCO input is at 0V and
this requires the phase de tect or ou tpu t to be gro und hen ce
the two input signals must be in phase. When the input fre-
quency is f
MAX
then the VCO in put must be VCC and the
phase detector inputs must be 180° out of phase.
The XOR is more sus cepti ble to lo cking onto h armon ics of
the signal input than the d igital phas e detector II . This can
be seen by noticing that a signal 2 times the VCO frequency results in the same outpu t duty cycle as a signal
equal the VCO freque ncy. The difference is t hat the output
frequency of the 2f example is twice that of the other example. The loop filter and the VCO ra nge shou ld be design ed
to prevent locking on to harmonics.
PHASE COMPARATOR II
This detector is a digital memory network. It consists of four
flip-flops and some gating logic, a three state outp ut an d a
phase pulse output a s shown i n
Figure 5
. This comparator
acts only on the po sitive edges of the inpu t signals an d is
thus independent of signal duty cycle.
Phase comparator II operates in such a way as to force the
PLL into lock with 0 phase difference betw een the VCO
output and the signal input posit ive waveform edges.
Fig-
ure 6
shows some typical loop wav eforms. First assume
that the signal input pha se i s lead i ng t he c om par ato r inp ut.
This means that the VCO’s frequency must be increased to
bring its leading edg e into proper phase alignm ent. Thus
the phase detector II output is set HIGH. This will cause the
loop filter to charge up th e VCO input increa sing the VCO
frequency. Once the leading edge of t he comparato r input
is detected the output goes 3-STATE holding the VCO
input at the loop filter voltage. If th e VCO still lags the signal then the phase detector will again charge up to VCO
input for the time between the leading edges of both waveforms.
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74VHC4046
Phase Comparator State Dia gra ms
FIGURE 4. PLL State Tables
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74VHC4046
FIGURE 5. Logic Diagram for Phase Comparator II
FIGURE 6. Typical Phase Comparator II Output Waveforms
If the VCO leads the signal then when the leadi ng edge of
the VCO is seen the output of th e phase comp arator go es
LOW. This discharges the loop filter until the lead ing edge
of the signal is detected at which time the output 3-STATEs
itself again. This has the effect of slowing down the VCO to
again make the rising edges of both waveform coincident.
When the PLL is out of lock the VCO will be running either
slower or faster than the signal input. If it i s runnin g slowe r
the phase detector will see more signal rising edges and so
the output of the phase co mparator w ill be high a majo rity
of the time, raising t he VCO’s freque ncy. Conversely, if the
VCO is running faster than the signal the output of the
detector will be low most of the time and the VCO’s output
frequency will be decreased.
As one can see when the PLL is locked the output of phase
comparator II will be almost always 3-STATE except for
minor corrections at the leading edge of the waveforms.
When the detector is 3- STATE the phase pulse output is
HIGH. This output can be used to de ter mi ne when the PLL
is in the locked condition.
This detector has several inter esting characteristics. Over
the entire VCO frequency rang e there is no phase difference between the comparator input and the s ignal input.
The lock range of the PLL is the same as the capture
range. Minimal power is consumed in the loop filter since in
lock the detector output is a high impedance. Also when no
signal is present the detector will see only VCO leading
edges, and so the comparator output will stay low forcing
the VCO to f
MIN
operating frequency.
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74VHC4046
Phase comparator II is more susceptible to noise causing
the phase lock loop to u nlock. If a noise pulse is seen on
the signal input, the comparator treats it as another positive
edge of the signal and will ca use the output to go HIGH
until the VCO leading edge is see n, potentiall y for a whole
signal input period. This would cause the VCO to speed up
during that time. When using the phase compara tor I the
output of that phase detector would be distu rbed for only
the short duration o f the n oise spik e a nd would cause less
upset.
PHASE COMPARATOR III
This comparator is a simple S-R Flip-Flop which can function as a phase co mparator
Figure 7
. It has some similar
characteristics to the edge sensitive comparator. To see
how this detector works assume input pulses are applied to
the signal and comparator inp uts as shown in
Figure 8
.
When the signal input leads the comparator input the flop is
set. This will charge up the loop filter and cause the VCO to
speed up, bringing th e comp arato r into p hase wi th the signal input. When using short pulses as input this comparator
behaves very similar to t he second comparator. But one
can see that if the signal input is a long pulse, the output of
the comparator will be forced to a one no matter how many
comparator input pulses are received. Also if the VCO input
is a square wave (as it is) and the signal input is pulse then
the VCO will force the comparator output LOW much of the
time. Therefore it is ideal to condi tion the signa l and comparator input to short pulses. This is most easily done by
using a series capacitor.
FIGURE 7. Phase Comparator III Logic Diagram
FIGURE 8. Typical Waveforms for Phase Comparator III
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74VHC4046
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
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74VHC4046
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
Page 16
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
74VHC4046 CMOS Phase Lock Loop
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the
user.
2. A critical component i n any compon ent of a lif e support
device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the life su pp ort
device or system, or to affect its safety or effectiveness.
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
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