Datasheet 74VHC27CW, 74VHC27SJX, 74VHC27SJ, 74VHC27N, 74VHC27MX Datasheet (Fairchild Semiconductor)
...Page 1
July 1994
Revised April 1999
74VHC27 Triple 3-Input NOR Gate
© 1999 Fairchild Semiconductor Corporation DS011682.prf www.fairchildsemi.com
74VHC27
Triple 3-Input NOR Gate
General Description
The VHC27 is an advanced high speed CMOS 3-Input
NOR Gate fabricated with silicon gate CMOS technology. It
achieves the high-speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation.
The internal circuit is composed of 3 stages including buffer
output, which provi de high noise immunity and stable ou tput. An input protection circuit insures that 0V to 7V can be
applied to the input pins without re gard to the supply voltage. This device can be used to interface 5V to 3V systems
and two supply systems such as b attery backup. This cir-
cuit prevents device destruction due to m isma tched supply
and input voltages.
Features
■ High speed: tPD = 4.1 ns (typ) at TA = 25°C
■ Low power dissipation: I
CC
= 2 µA (max) at TA = 25°C
■ High noise immunity: V
NIH
= V
NIL
= 28% VCC (min)
■ Power down protection is provided on all inputs
■ Low noise: V
OLP
= 0.8V (max)
■ Pin and function compatible with 74HC27
Ordering Code:
Surface mount pack ages are also available on Tape and Reel. Specify by appending the s uffix let te r “X” to the ordering code.
Logic Symbol
IEEE/IEC
Pin Descriptions
Connection Diagram
Truth Table
X = Don't Care
Order Number Package Number Package Description
74VHC27M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74VHC27SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC27MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC27N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
A
n
, Bn, C
n
Inputs
Y
n
Outputs
A B C Y
H X X L
X H X L
X X H L
L L L H
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74VHC27
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
(Note 2)
Note 1: Absolute Maximum Ratings are values beyond which the device
may be damaged or ha ve its useful li fe impaire d. The datab ook specifications should be met, without exception, to ensure that the system design is
reliable over its p ower supp ly, temperature, and ou tput/input loading variables. Fairchild does not recom mend operation outside databook specifications.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Noise Characteristics
Note 3: Paramete r guaranteed by design.
Supply Voltage (VCC) −0.5V to +7.0V
DC Input Voltage (V
IN
) −0.5V to +7.0V
DC Output Voltage (V
OUT
) −0.5V to VCC + 0.5V
Input Diode Current (I
IK
) −20 mA
Output Diode Current (I
OK
) ±20 mA
DC Output Current (I
OUT
) ±25 mA
DC V
CC
/GND Current (ICC) ±50 mA
Storage Temperature (T
STG
) −65°C to +150°C
Lead Temperature (T
L
)
(Soldering, 10 seconds) 260°C
Supply Voltage (V
CC
) 2.0V to +5.5V
Input Voltage (V
IN
) 0V to +5.5V
Output Voltage (V
OUT
) 0V to V
CC
Operating Temperature (T
OPR
) −40°C to +85°C
Input Rise and Fall Time (t
r
, tf)
V
CC
= 3.3V ± 0.3V 0 ns/V ∼ 100 ns/V
V
CC
= 5.0V ± 0.5V 0 ns/V ∼ 20 ns/V
Symbol Parameter
V
CC
(V)
TA = 25°C T
A
= −40°C to +85°C
Units Conditions
Min Typ Max Min Max
V
IH
HIGH Level 2.0 1.50 1.50
V
Input Voltage 3.0 − 5.5 0.7 V
CC
0.7 V
CC
V
IL
LOW Level 2.0 0.50 0.50
V
Input Voltage 3.0 − 5.5 0.3 V
CC
0.3 V
CC
V
OH
HIGH Level 2.0 1.9 2.0 1.9 VIN = VIH IOH = −50 µA
Output Voltage 3.0 2.9 3.0 2.9 V or V
IL
4.5 4.4 4.5 4.4
3.0 2.58 2.48
V
IOH = −4 mA
4.5 3.94 3.80 IOH = −8 mA
V
OL
LOW Level 2.0 0.0 0.1 0.1 VIN = VIH IOL = 50 µA
Output Voltage 3.0 0.0 0.1 0.1 V or V
IL
4.5 0.0 0.1 0.1
3.0 0.36 0.44
V
IOL = 4 mA
4.5 0.36 0.44 IOL = 8 mA
I
IN
Input Leakage Current 0 − 5.5 ±0.1 ±1.0 µA VIN = 5.5V or GND
I
CC
Quiescent Supply
Current
5.5 2.0 20.0
µA
VIN = VCC or GND
Symbol Parameter
V
CC
(V)
TA = 25°C
Units Conditions
Typ Limits
V
OLP
Quiet Output Maximum 5.0 0.3 0.8 V CL = 50 pF
(Note 3) Dynamic V
OL
V
OLV
Quiet Output Minimum 5.0 −0.3 −0.8 V CL = 50 pF
(Note 3) Dynamic V
OL
V
IHD
Minimum HIGH Level 5.0 3.5 V CL = 50 pF
(Note 3) Dynamic Input Voltage
V
ILD
Maximum LOW Level 5.0 1.5 V CL = 50 pF
(Note 3) Dynamic Input Voltage
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74VHC27
AC Electrical Characteristics
Note 4: CPD is defined as the value of the internal equiv alent capacitance whic h is calculated from the operating current c ons umption without load. Av erage
operating current ca n be obtained by the equat ion: I
CC
(opr.) = CPD * VCC * fIN + ICC/3 (per gate).
Symbol Parameter
V
CC
(V)
TA = 25°C T
A
= −40°C to +85°C
Units Conditions
Min Typ Max Min Max
t
PHL
Propagation Delay 3.3 ± 0.3 6.2 8.8 1.0 10.5
ns
CL = 15 pF
t
PLH
8.7 12.3 1.0 14.0 CL = 50 pF
5.0 ± 0.5 4.1 5.9 1.0 7.0
ns
CL = 15 pF
5.6 7.9 1.0 9.0 CL = 50 pF
C
IN
Input Capacitance 4 10 10 pF VCC = Open
C
PD
Power Dissipation 20 pF (Note 4)
Capacitance
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74VHC27
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
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74VHC27
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
74VHC27 Triple 3-Input NOR Gate
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the
user.
2. A critical component i n any compon ent of a lif e support
device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the life su pp ort
device or system, or to affect its safety or effectiveness.
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
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