The 74VHC05 is an advanced high-speed CMOS
OPEN DRAIN HEX INVERTER fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
The internal circuit is composed of 3 stages
including buffer ou tput, whi ch provid es hig h no ise
immunity and stable output.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
TSSOPSOP
Table 1: Order Codes
PACKAGET & R
SOP74VHC05MTR
TSSOP74VHC05TTR
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static disc harge, giving
them 2KV ESD immunity and transient excess
voltage.
Figure 1: Pin Connection An d I E C Logic Symbols
Rev. 5
1/11November 2004
Page 2
74VHC05
Figure 2: Inp ut Eq ui v al e nt C irc ui t Table 2: Pin Des cription
PIN N°SYMBOLNAME AND FUNCTION
1, 3, 5, 9, 1 1,
13
2, 4, 6, 8, 10,
12
7GNDGround (0V)
14
Table 3: Trut h Table
Z: High Imped ance
Table 4: Absolute Maximum Ratings
SymbolParameterValueUnit
V
V
V
I
I
OK
I
or I
I
CC
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Supply Voltage
CC
DC Input Voltage
I
DC Output Voltage-0.5 to VCC + 0.5
O
DC Input Diode Current
IK
DC Output Diode Current
DC Output Current
O
DC VCC or Ground Current
GND
Storage Temperature
stg
Lead Temperature (10 sec)
L
Table 5: Recommended Operating Conditions
1A to 6AData Inputs
1Y to 6YData Outputs
V
CC
Positive Supply Voltage
AY
LZ
HL
-0.5 to +7.0V
-0.5 to +7.0V
V
- 20mA
± 20mA
± 25mA
± 75mA
-65 to +150°C
300°C
SymbolParameterValueUnit
V
V
V
T
dt/dv
1) VIN from 30% to 70% of V
Supply Voltage
CC
Input Voltage
I
Output Voltage0 to V
O
Operating Temperature
op
Input Rise and Fall Time (note 1) (V
(V
CC
= 3.3 ± 0.3V)
CC
= 5.0 ± 0.5V)
CC
2 to 5.5V
0 to 5.5V
CC
-55 to 125°C
0 to 100
0 to 20
2/11
V
ns/V
Page 3
Table 6: DC Specifications
SymbolParameter
V
V
High Level Input
IH
Voltage
V
Low Level Input
IL
Voltage
Low Level Output
OL
Voltage
I
High Impedance
OZ
Output Leakage
Current
Input Leakage
I
I
Current
Quiescent Supply
I
CC
Current
V
(V)
2.01.51.51.5
3.0 to
5.5
2.00.50.50.5
3.0 to
5.5
2.0
3.0
4.5
3.0
4.5
5.5
0 to
5.5
5.5
Test ConditionValue
= 25°C
T
CC
A
Min.Typ. Max.Min.Max. Min. Max.
0.7V
CC
0.3V
CC
IO=50 µA
I
=50 µA
O
=50 µA
I
O
=4 mA
I
O
=8 mA
I
O
= VIH or V
V
I
IL
VO = VCC or GND
= 5.5V or GND
V
I
= VCC or GND
V
I
0.00.10.10.1
0.00.10.10.1
0.00.10.10.1
0.360.440.55
0.360.440.55
±0.25± 2.5± 2.5µA
± 0.1± 1± 1µA
22020µA
74VHC05
-40 to 85°C -55 to 125°C
0.7V
CC
0.3V
CC
0.7V
CC
0.3V
CC
Unit
V
V
V
Table 7: AC Electrical Characteristics (Input t
Test ConditionValue
SymbolParameter
t
t
(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5.0V ±
PZL
PLZ
Output Enable
Time
Output Disable
Time
0.5V
V
3.3
3.3
5.0
5.0
3.3
5.0
(V)
CC
(*)
(*)
(**)
(**)
(*)
(**)
C
(pF)
15
50
15
50
50
50
L
R
= 1 KΩ
L
R
= 1 KΩ
L
R
= 1 KΩ
L
R
= 1 KΩ
L
R
= 1 KΩ
L
R
= 1 KΩ
L
= tf = 3ns)
r
= 25°C
T
A
-40 to 85°C -55 to 125°C
Min.Typ. Max.Min.Max. Min. Max.
5.07.11.08.51.08.5
7.510.61.012.01.012.0
3.85.51.06.51.06.5
5.37.51.08.51.08.5
7.510.61.012.01.012.0
5.37.51.08.51.08.5
Unit
ns
ns
3/11
Page 4
74VHC05
Table 8: Capacitive Characteristics
Test ConditionValue
= 25°C
SymbolParameter
T
A
Min.Typ. Max.Min.Max. Min. Max.
C
C
C
Input Capacitance
IN
Output
OUT
Capacitance
Power Dissipation
PD
Capacitance
6101010pF
8pF
3pF
(note 1)
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
Table 9: Dynamic Switching Characteristics
Test ConditionValue
= 25°C
SymbolParameter
V
V
Dynamic Low
OLP
Voltage Quiet
OLV
Output (note 1, 2)
Dynamic High
V
IHD
Voltage Input
(note 1, 3)
Dynamic Low
V
ILD
Voltage Input
(note 1, 3)
V
CC
(V)
5.0
= 50 pF
5.03.5V
C
L
5.01.5V
T
A
Min.Typ. Max.Min.Max. Min. Max.
0.40.8
-0.8-0.4
-40 to 85°C -55 to 125°C
= CPD x VCC x fIN + ICC/6 (per gate)
CC(opr)
-40 to 85°C -55 to 125°C
Unit
Unit
V
1) Worst case package.
2) Max number of outp ut s defined as (n). Data inpu t s are driven 0V to 5.0V, (n-1) outputs switc hi ng and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (V
(V
), f=1MHz.
IHD
ILD
Figure 3: Test Circuit
CL = 15/50pF or e qui valent (inc lu des jig and pro be capacitan ce)
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