Datasheet 74VHC00MX, 74VHC00MTCX, 74VHC00MTC, 74VHC00MSCX, 74VHC00M Datasheet (Fairchild Semiconductor)
...Page 1
October 1992
Revised April 1999
74VHC00 Quad 2-Input NAND Gate
© 1999 Fairchild Semiconductor Corporation DS011504.prf www.fairchildsemi.com
74VHC00
Quad 2-Input NAND Gate
General Description
The VHC00 is an advanced high-speed CMOS 2-Input
NAND Gate fabricated with silicon gate CMOS technology.
It achieves the high-speed operation similar to equival ent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation. The internal circuit is composed of 3
stages, including buffer ou tput, which provide high noise
immunity and stable output. An input protection circuit
insures that 0V to 7V can be ap pli ed to th e in pu t p in s wi t hout regard to the supp ly voltage. T his device can be used
to interface 5V to 3V systems and two supply systems such
as battery backup. T his circuit prevents d evice destru ction
due to mismatched supply and input voltages.
Features
■ High Speed: tPD = 3.7ns (typ) at TA = 25°C
■ High noise immunity: V
NIH
= V
NIL
= 28% VCC (min)
■ Power down protection is provided on all inputs
■ Low noise: V
OLP
= 0.8V (max)
■ Low power dissipation: I
CC
= 2 µA (max) at TA = 25°C
■ Pin and function compatible with 74HC00
Ordering Code:
Surface mount pack ages are also available on Tape and Reel. Specify by appending the s uffix let te r “X” to the ordering code.
Logic Symbol
IEEE/IEC
Pin Descriptions
Connection Diagram
Truth Table
Order Number Package Number Package Description
74VHC00M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
74VHC00SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC00MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC00N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
A
n
, B
n
Inputs
O
n
Outputs
ABO
LLH
LHH
HLH
HHL
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74VHC00
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
(Note 2)
Note 1: Absolute Maximum Ratings are values beyond which the device
may be damaged or ha ve its useful li fe impaire d. The datab ook specifications should be met, without exception, to ensure that the system design is
reliable over its p ower supp ly, temperature, and ou tput/input loading variables. Fairchild does not recom mend operation outside data book specifications.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Noise Characteristics
Note 3: Paramete r guaranteed by design
Supply Voltage (VCC) −0.5V to +7.0V
DC Input Voltage (V
IN
) −0.5V to +7.0V
DC Output Voltage (V
OUT
) −0.5V to VCC +0.5V
Input Diode Current (I
IK
) −20 mA
Output Diode Current (I
OK
) ±20 mA
DC Output Current (I
OUT
) ±25 mA
DC V
CC
/GND Current (ICC) ±50 mA
Storage Temperature (T
STG
) −65°C to +150°C
Lead Temperature (T
L
)
(Soldering, 10 seconds) 260°C
Supply Voltage (V
CC
) 2.0V to +5.5V
Input Voltage (V
IN
)0V to +5.5V
Output Voltage (V
OUT
) 0V to V
CC
Operating Temperature (T
OPR
) −40°C to +85°C
Input Rise and Fall Time (t
r
, tf)
V
CC
= 3.3V ± 0.3V 0 ns/V ∼ 100 ns/V
V
CC
= 5.0V ± 0.5V 0 ns/V ∼ 20 ns/V
Symbol Parameter
V
CC
(V)
TA = 25°CT
A
= −40°C to +85°C
Units Conditions
Min Typ Max Min Max
V
IH
HIGH Level 2.0 1.50 1.50
V
Input Voltage 3.0 − 5.5 0.7 V
CC
0.7 V
CC
V
IL
LOW Level 2.0 0.50 0.50
V
Input Voltage 3.0 − 5.5 0.3 V
CC
0.3 V
CC
V
OH
HIGH Level 2.0 1.9 2.0 1.9
V
VIN = VIHIOH = −50 µA
Output Voltage 3.0 2.9 3.0 2.9 or V
IL
4.5 4.4 4.5 4.4
3.0 2.58 2.48
V
IOH = −4mA
4.5 3.94 3.80 IOH = −8mA
V
OL
LOW Level 2.0 0.0 0.1 0.1
V
VIN = VIHIOL = 50 µA
Output Voltage 3.0 0.0 0.1 0.1 or V
IL
4.5 0.0 0.1 0.1
3.0 0.36 0.44
V
IOL = 4 mA
4.5 0.36 0.44 IOL = 8 mA
I
IN
Input Leakage Current 0 − 5.5 ±0.1 ±1.0 µAVIN = 5.5V or GND
I
CC
Quiescent Supply Current 5.5 2.0 20.0 µAVIN = VCC or GND
Symbol Parameter
V
CC
(V)
TA = 25°C
Units Conditions
Typ Limit
V
OLP
Quiet Output Maximum 5.0 0.3 0.8 V CL = 50 pF
(Note 3) Dynamic V
OL
V
OLV
Quiet Output Minimum 5.0 −0.3 −0.8 V CL = 50 pF
(Note 3) Dynamic V
OL
V
IHD
Minimum HIGH Level 5.0 3.5 V CL = 50 pF
(Note 3) Dynamic Input Voltage
V
ILD
Maximum LOW Level 5.0 1.5 V CL = 50 pF
(Note 3) Dynamic Input Voltage
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74VHC00
AC Electrical Characteristics
Note 4: CPD is defined as the value of the internal equiv alent capacitance which is calculated from the operating current c ons umption without load. Average
operating current ca n be obtained from the equ at ion: I
CC
(opr.) = CPD * VCC * fIN + ICC/4 (per gate).
Symbol Parameter
V
CC
(V)
TA = 25°CT
A
= −40°C to +85°C
Units Conditions
Min Typ Max Min Max
t
PLH
Propagation 3.3 ± 0.3 5.5 7.9 1.0 9.5
ns
CL = 15 pF
t
PHL
Delay 8.0 11.4 1.0 13.0 CL = 50 pF
5.0 ± 0.5 3.7 5.5 1.0 6.5
ns
CL = 15 pF
5.2 7.5 1.0 8.5 CL = 50 pF
C
IN
Input Capacitance 4 10 10 pF VCC = Open
C
PD
Power Dissipation 19 pF (Note 4)
Capacitance
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74VHC00
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
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74VHC00
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
74VHC00 Quad 2-Input NAND Gate
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the
user.
2. A critical component i n any compon ent of a lif e support
device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the life su pp ort
device or system, or to affect its safety or effectiveness.
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N14A
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