The 74V1G80 is an advanced high-speed CMOS
SINGLE POSITIVE EDGE TRIGGERED D-TYPE
FLIP-FLOP WITH INVERTED OUTPUT
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology. it is
designed to operate from 2V to 5.5V , making t his
device ideal for portable applications.
This D-Type flip-flop is controlled by a clock input
(CK). On the positive transition of the clock, the Q
output will be set to the logic inverted sta te that
was setup at the D input.
SOT323-5LSOT23-5L
ORDER CODES
PACKAGET & R
SOT23-5L74V1G80STR
SOT323-5L74V1G80CTR
Following the hold time interval, data at the D input
can be changed without affecting the level at the
output. Power down protection is provided on
input and 0 to 7V can be accepted on input with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
It’s available in the commercial temperature
range. All inputs and output are equipped with
protection circuits against stat ic discharge, giving
them ESD immunity and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/10July 2001
Page 2
74V1G80
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN NoSYMBOLNAME AND FUNCTION
1DData Input
2CK
4Q
3GNDGround (0V)
5
TRUTH TABLE
DCKQ
LH
HL
LQn
HQn
ABSOLUTE MAXIMUM RATINGS
V
CC
Clock Input (Positive
Edge)
Inverted Flip-Flop Output
Positive Supply Voltage
SymbolParameterValueUnit
V
V
V
I
I
OK
I
I
or I
CC
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
Supply Voltage
CC
DC Input Voltage
I
DC Output Voltage-0.5 to VCC + 0.5
O
DC Input Diode Current
IK
DC Output Diode Current
DC Output Current
O
DC VCC or Ground Current
GND
Storage Temperature
stg
Lead Temperature (10 sec)
L
-0.5 to +7.0V
-0.5 to +7.0V
V
- 20mA
± 20mA
± 25mA
± 50mA
-65 to +150°C
260°C
RECOMMENDED OPERATING CONDITIONS
SymbolParameterValueUnit
V
V
V
T
dt/dv
1) VIN from 30 % to 70% of V
Supply Voltage
CC
Input Voltage
I
Output Voltage0 to V
O
Operating Temperature
op
Input Rise and Fall Time (note 1) (V
(V
CC
= 3.3 ± 0.3V)
CC
= 5.0 ± 0.5V)
CC
2 to 5.5V
0 to 5.5V
CC
-55 to 125°C
0 to 100
0 to 20
ns/V
ns/V
V
2/10
Page 3
DC SPECIFICATIONS
SymbolParameter
V
V
V
V
I
High Level Input
IH
Voltage
Low Level Input
IL
Voltage
High Level Output
OH
Voltage
Low Level Output
OL
Voltage
I
Input Leakage
I
Current
Quiescent Supply
CC
Current
Test ConditionValue
V
(V)
CC
= 25°C
A
Min.Typ. Max.Min.Max. Min. Max.
-40 to 85°C -55 to 125°C
T
2.01.51.51.5
3.0 to
5.5
0.7V
CC
0.7V
CC
0.7V
CC
2.00.50.50.5
3.0 to
5.5
2.0
3.0
4.5
3.0
4.5
2.0
3.0
4.5
3.0
4.5
0 to
5.5
5.5
=-50 µA
I
O
I
=-50 µA
O
I
=-50 µA
O
I
=-4 mA
O
I
=-8 mA
O
IO=50 µA
I
=50 µA
O
I
=50 µA
O
I
=4 mA
O
I
=8 mA
O
V
= 5.5V or GND
I
= VCC or GND
V
I
1.92.01.91.9
2.93.02.92.9
4.44.54.44.4
2.582.482.4
3.943.83.7
0.3V
CC
0.3V
CC
0.00.10.10.1
0.00.10.10.1
0.00.10.10.1
0.360.440.55
0.360.440.55
± 0.1± 1± 1µA
11020µA
74V1G80
Unit
0.3V
CC
V
V
V
V
AC ELECTRICAL CHARACTERISTICS (Input t
Test ConditionValue
SymbolParameter
t
PLH tPHL
f
MAX
(*) Vol tage range is 3.3V ±0.3V
(**) Voltage range is 5.0V ±
Propagation Delay
Time CK to Q
CK Pulse Width,
t
W
HIGH or LOW
Setup Time D to
t
s
CK, HIGH or LOW
Hold Time D to CK,
t
h
HIGH or LOW
Maximum Clock
Frequency
0.5V
3.3
3.3
5.0
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
C
V
CC
(V)
L
(pF)
(*)
154.98.41.09.81.010.8
(*)
505.912.01.014.01.015.0
(**)
153.55.61.07.01.08.0
(**)
504.58.01.010.01.011.0
(*)
(**)
(*)
(**)
(*)
(**)
(*)
501001209090
(**)
50165180150150
= tf = 3ns)
r
T
= 25°C
A
-40 to 85°C -55 to 125°C
Min.Typ. Max.Min.Max. Min. Max.
4.04.04.0
3.03.03.0
4.04.04.0
3.03.03.0
1.01.01.0
1.01.01.0
Unit
ns
ns
ns
ns
MHz
3/10
Page 4
74V1G80
CAPACITIVE CHARACTERISTICS
Test ConditionValue
= 25°C
SymbolParameter
T
A
Min.Typ. Max.Min.Max. Min. Max.
C
C
Input Capacitance
IN
Power Dissipation
PD
Capacitance
4101010pF
8pF
(note 1)
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (R ef er to Test Circ ui t). Averag e operating current can be obtained by t he following equation. I
TEST CIRCUIT
-40 to 85°C -55 to 125°C
= CPD x VCC x fIN + I
CC(opr)
CC
Unit
CL = 15/50pF or e qui valent (includes jig and probe capa ci t ance)
R
= Z
of pulse generator (typically 50Ω)
T
OUT
4/10
Page 5
74V1G80
WAVEFORM: PROPAGATION DELAY, SETUP AND HOLD TIM ES (f=1MHz; 50% duty cycl e)
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