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June 1993
Revised March 1999
74LVX573
Low Voltage Octal Latch with 3-STATE Outputs
74LVX573 Low Voltage Octal Latch with 3-STATE Outputs
General Description
The LVX573 is a high-speed octal latch with buffered com mon Latch Enable (LE) and buffered common Output
Enable (O E
the LVX373 but with inputs and outputs on opposite sides
of the package. The inp uts tole ra te u p to 7V allowing interface of 5V systems to 3V systems.
) inputs. The LVX573 is fu nct io na lly id entical to
Features
■ Input voltage translation from 5V to 3V
■ Ideal for low power/low noise 3.3V applications
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number Package Number Package Description
74LVX573M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74LVX573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also availab le in Tape and Reel. Specify by appending su ffix let te r “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
Pin Names Description
D
0–D7
LE Latch Enable Input
OE
O
0–O7
© 1999 Fairchild Semiconductor Corporation DS011616.prf www.fairchildsemi.com
Data Inputs
3-STATE Output Enable Input
3-STATE Latch Outputs
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Functional Description
The LVX573 contains eight D-type latches. When the
enable (LE) input is HIGH, data on the D
latches. In this condition the latches are tran sparent, i.e., a
74LVX573
latch output will change state each time its D input
changes. When LE is LOW the la tches store the information that was pres ent on th e D inp uts a s etu p time preced ing the HIGH-to-LOW transition of LE. The 3-STATE
buffers are controlled by the Output Enable (OE
When OE
HIGH the buffers are in the high imp edance mo de but this
does not interfere with entering new data into the latches.
is LOW, the buffers are enabled. When OE is
inputs enters the
n
Logic Diagram
) input.
Truth T able
Inputs Outputs
OE
LHH H
LHL L
LLX O
HXX Z
H = HIGH Voltage
L = LOW Voltage
Z = High Impedance
X = Immaterial
O0 = Previous O0 before HIGH-to-LOW transition of Lat ch Enable
LE D O
n
0
Please note that this diagram is provided only for the understan ding of logic operation s and should not be used t o es t im ate propagation delays.
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Absolute Maximum Ratings(Note 1) Recommended Operating
Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I
= −0.5V −20 mA
V
I
DC Input Voltage (V
DC Output Diode Current (I
= −0.5V −20 mA
V
O
= VCC + 0.5V +20 mA
V
O
DC Output Voltage (V
)
IK
) −0.5V to 7V
I
)
OK
) −0.5V to VCC + 0.5V
O
DC Output Source
or Sink Current (I
or Ground Current
DC V
CC
or I
(I
CC
GND
Storage Temperature (T
) ±25 mA
O
) ±75 mA
) −65°C to +150°C
STG
Power Dissipation 180 mW
Conditions
Supply Voltage (V
Input Voltage (V
Output Voltage (V
Operating Temperature (TA) −40°C to +85°C
Input Rise and Fall Time (∆t/∆V) 0 ns/V to 100 ns/V
Note 1: The “Absolute Maximum Ratings ” are those val ues beyond w hich
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommend ed O peratin g Cond itions” t able w ill defin e the condit ions
for actual device operation.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
(Note 2)
) 2.0V to 3.6V
CC
) 0V to 5.5V
I
)0V to V
O
DC Electrical Characteristics
Symbol Parameter
V
HIGH Level 2.0 1.5 1.5
IH
Input Voltage 3.0 2.0 2.0 V
V
LOW Level 2.0 0.5 0.5
IL
Input Voltage 3.0 0.8 0.8 V
V
HIGH Level 2.0 1.9 2.0 1.9 VIN = VIH or VILIOH = −50 µA
OH
Output Voltage 3.0 2.9 3.0 2.9 V IOH = −50 µA
V
LOW Level 2.0 0.0 0.1 0.1 VIN = VIH or VILIOL = 50 µA
OL
Output Voltage 3.0 0.0 0.1 0.1 V IOL = 50 µA
I
3-STATE Output 3.6 ±0.25 ±2.5 µAVIN = VIH or V
OZ
Off-State Current V
I
Input Leakage Current 3.6 ±0.1 ±1.0 µAVIN = 5.5V or GND
IN
I
Quiescent Supply Current 3.6 4.0 40.0 µAVIN = VCC or GND
CC
V
CC
3.6 2.4 2.4
3.6 0.8 0.8
3.0 2.58 2.48 IOH = −4 mA
3.0 0.36 0.44 IOL = 4 mA
TA = +25°CT
Min Typ Max Min Max
= −40°C to +85°C
A
Units Conditions
= VCC or GND
OUT
74LVX573
CC
IL
Noise Characteristics
Symbol Parameter
V
Quiet Output Maximum Dynamic V
OLP
V
Quiet Output Minimum Dynamic V
OLV
V
Minimum HIGH Level Dynamic Input Voltage 3.3 2.0 V 50
IHD
V
Maximum LOW Level Dynamic Input Voltage 3.3 0.8 V 50
ILD
Note 3: (Input tr = tf = 3ns)
(Note 3)
OL
V
CC
(V)
OL
3.3 0.5 0.8 V 50
3.3 −0.5 −0.8 V 50
TA = 25°C
Typ Limit
Units
CL (pF)
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AC Electrical Characteristics
Symbol Parameter
74LVX573
t
Propagation 2.7 7.6 14.5 1.0 17.5
PLH
t
Delay Time 10.1 18.0 1.0 21.0 CL = 50 pF
PHL
Dn to O
n
t
Propagation 2.7 8.2 15.6 1.0 18.5
PLH
t
Delay Time 10.7 19.1 1.0 22.0 CL = 50 pF
PHL
LE to O
n
t
3-STATE Output 2.7 7.8 15.0 1.0 18.5
PZL
t
Enable Time 10.3 18.5 1.0 22.0 CL = 50 pF, RL = 1 kΩ
PZH
t
3-STATE Output 2.7 12.1 19.1 1.0 22.0
PLZ
t
Disable Time 3.3 ± 0.3 10.1 13.6 1.0 15.5 CL = 50 pF, RL = 1 kΩ
PHZ
t
LE Pulse 2.7 6.5 7.5
W
Width 3.3 ± 0.3 5.0 5.0
t
Setup Time 2.7 5.0 5.0
S
Dn to LE 3.3 ± 0.3 3.5 3.5
t
Hold Time 2.7 1.5 1.5
H
Dn to LE 3.3 ± 0.3 1.5 1.5
t
Output to Output 2.7 1.5 1.5
OSHL
t
Skew (Note 4) 2.3 1.5 1.5
OSLH
Note 4: Paramete r guaranteed by design. t
V
CC
(V)
TA = +25°CT
Min Typ Max Min Max
3.3 ± 0.3 5.9 9.3 1.0 11.0 CL = 15 pF
8.4 12.8 1.0 14.5 CL = 50 pF
3.3 ± 0.3 6.4 10.1 1.0 12.0 CL = 15 pF
8.9 13.6 1.0 15.5 CL = 50 pF
3.3 ± 0.3 6.1 9.7 1.0 12.0 CL = 15 pF, RL = 1 kΩ
8.6 13.2 1.0 15.5 CL = 50 pF, RL = 1 kΩ
= |t
− t
|, t
= |t
OSLH
PLHm
PLHn
OSHL
PHLm
− t
PHLn
|.
= −40°C to +85°C
A
Units Conditions
CL = 15 pF
ns
CL = 15 pF
ns
CL = 15 pF, RL = 1 kΩ
ns
CL = 50 pF, RL = 1 kΩ
ns
ns
ns
ns
CL = 50 pF
ns
Capacitance
Symbol Parameter
C
C
C
Input Capacitance 4 10 10 pF
IN
Output Capacitance 6 pF
OUT
Power Dissipation 27 pF
PD
TA = +25°CT
Min Typ Max Min Max
Capacitance (Note 5)
Note 5: CPD is defined as the value of the internal equiv alent capacitance whic h is calculated from the operating current cons umption without load.
= −40°C to +85°C
A
Units
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Physical Dimensions inches (millimeters) unless otherwise noted
74LVX573
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20B
Package Number M20D
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
74LVX573 Low Voltage Octal Latch with 3-ST ATE Outputs
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r systems a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significan t injury to the
user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
Package Number MTC20
2. A critical compon ent i n any compon ent of a life su pport
device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the li fe su pp ort
device or system, or to affect its safety or effectiveness.
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