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74LVX32
Low Voltage Quad 2-Input OR Gate
74LVX32 Low Voltage Quad 2-Input OR Gate
May 1993
Revised March 1999
General Description
The LVX32 contains four 2-inp ut OR ga tes. T he in puts t olerate voltages up to 7V allowing the interface of 5V systems to 3V systems.
Features
■ Input voltage level translation from 5V to 3V
■ Ideal for low power/low noise 3.3V applications
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number Package Number Package Description
74LVX32M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
74LVX32SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX32MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also availab le in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Description
Pin Names Description
, B
A
n
n
O
n
© 1999 Fairchild Semiconductor Corporation DS011604.prf www.fairchildsemi.com
Inputs
Outputs
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Absolute Maximum Ratings(Note 1) Recommended Operating
Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I
74LVX32
= −0.5V −20 mA
V
I
DC Input Voltage (V
DC Output Diode Current (I
= −0.5V −20 mA
V
O
= VCC + 0.5V +20 mA
V
O
DC Output Voltage (V
)
IK
) −0.5V to 7V
I
)
OK
) −0.5V to VCC + 0.5V
O
DC Output Source
or Sink Current (I
or Ground Current
DC V
CC
or I
(I
CC
GND
Storage Temperature (T
) ±25 mA
O
) ±50 mA
) −65°C to +150°C
STG
Power Dissipation 180 mW
Conditions
Supply Voltage (V
Input Voltage (V
Output Voltage (V
Operating Temperature (TA) −40°C to +85°C
Input Rise and Fall Time (∆t/∆V) 0 ns/V to 100 ns/V
Note 1: The “Absolute Maximum Ratin gs” are those v alues beyon d which
the safety of the dev ice cannot be guaranteed. T he device sh ould not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommend ed O peratin g Cond itions” t able w ill defin e the c ondit ions
for actual device operation.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
(Note 2)
) 2.0V to 3.6V
CC
)0V to 5.5V
I
) 0V to V
O
DC Electrical Characteristics
Symbol Parameter
V
HIGH Level Input 2.0 1.5 1.5
IH
Voltage 3.0 2.0 2.0 V
V
LOW Level Input 2.0 0.5 0.5
IL
Voltage 3.0 0.8 0.8 V
V
HIGH Level Output 2.0 1.9 2.0 1.9 VIN = VIL or VIHIOH = −50 µA
OH
Voltage 3.0 2.9 3.0 2.9 V IOH = −50 µA
V
LOW Level Output 2.0 0.0 0.1 0.1 VIN = VIL or VIHIOL = 50 µA
OL
Voltage 3.0 0.0 0.1 0.1 V IOL = 50 µA
I
Input Leakage Current 3.6 ±0.1 ±1.0 µAVIN = 5.5V or GND
IN
I
Quiescent Supply Current 3.6 2.0 20 µAVIN = VCC or GND
CC
V
CC
3.6 2.4 2.4
3.6 0.8 0.8
3.0 2.58 2.48 IOH = −4 mA
3.0 0.36 0.44 IOL = 4 mA
TA = +25°CT
Min Typ Max Min Max
= −40°C to +85°C
A
Units Conditions
CC
Noise Characteristics
Symbol Parameter
V
Quiet Output Maximum Dynamic V
OLP
V
Quiet Output Minimum Dynamic V
OLV
V
Minimum HIGH Level Dynamic Input Voltage 3.3 2.0 V 50
IHD
V
Maximum LOW Level Dynamic Input Voltage 3.3 0.8 V 50
ILD
Note 3: (Input tr = tf = 3 ns)
(Note 3)
OL
OL
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V
CC
(V)
3.3 0.3 0.5 V 50
3.3 −0.3 −0.5 V 50
TA = 25°C
Typ Limit
Units
CL (pF)
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AC Electrical Characteristics
Symbol Parameter
t
t
t
t
Propagation 2.7 5.8 10.7 1.0 12.5
PLH
Delay Time 8.3 14.2 1.0 16.0 50
PHL
Output to Output 2.7 1.5 1.5
OSLH
Skew (Note 4) 3.3 1.5 1.5
OSHL
Note 4: Parameter gu aranteed by design. t
V
CC
(V)
TA = +25°CT
Min Typ Max Min Max
3.3 ± 0.3 4.4 6.6 1.0 7.5 15
6.9 10.1 1.0 11.5 50
= |t
− t
|, t
= |t
OSLH
PLHm
PLHn
OSHL
PHLm
− t
PHLn
|
= −40°C to +85°C
A
Units
ns
ns
Capacitance
Symbol Parameter
C
Input Capacitance 4 10 10 pF
IN
C
Power Dissipation 14 pF
PD
TA = +25°CT
Min Typ Max Min Max
Capacitance (Note 5)
Note 5: CPD is defined as the value of the internal equiv alent capacitance w hic h is calculated from th e operating current co ns umption without load.
= −40°C to +85°C
A
74LVX32
CL (pF)
15
50
Units
3 www.fairchildsemi.com
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Physical Dimensions inches (millimeters) unless otherwise noted
74LVX32
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
14-Lead Small Outline Package ( SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14A
Package Number M14D
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
74LVX32 Low Voltage Quad 2-Input OR Gate
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provide d in the labe l ing, can be re asonably expected to result in a significant injury to the
user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
Package Number MTC14
2. A critical componen t in any com ponen t of a life s upport
device or system whose failu re to perform can b e reasonably expected to cause the failure of the li fe s upp or t
device or system, or to affect its safety or effectiveness.
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