The 74LVX257 i s a low voltage CMOS QUAD 2
CHANNEL MULTIPLEXER (3-STATE) fabricated
with sub-micron silicon gate and double-layer
metal wiring C
2
MOS technology. It is ideal for low
power, battery operated and low noise 3.3V
applications.
It is composed of four independent 2-channel
multiplexers with commo n SELECT and ENABLE
(OE
) INPUT. The 74LVX257 is a non-inverting
TSSOPSOP
ORDER CODES
PACKAGETUBET & R
SOP74LVX257M74LVX257MTR
TSSOP74LVX257TTR
multiplexer. When the ENABLE INPUT is held
"High", all outputs become in high impedance
state. If SELECT INPUT is held "L ow", "A" dat a is
selected, when SELECT INPUT is "High", "B"
data is chosen.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V. It
combines high speed performance with the true
CMOS low power consumption.
All inputs and outputs are equipped with
protection circuits against stat ic discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/10July 2001
Page 2
74LVX257
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN NoSYMBOLNAME AND FUNCTION
1SELECTCommon Data Select
2, 5, 11, 141A to 4AData Inputs From Source
3, 6, 10, 131B to 4BData Inputs From Source
4, 7, 9, 121Y to 4Y3 State Multiplexer
15OE
8GNDGround (0V)
16V
TRUTH TABLE
INPUTSOUTPUT
CC
Inputs
A
B
Outputs
3 State Output Enable
Inputs (Active LOW)
Positive Supply Voltage
OE
HXXXZ
LLLXL
LLHXH
LHXLL
LHXHH
X :Don‘t Care
Z : High Impedance
LOGIC DIAGRAM
SELECTABY
This log i c diagram has not be used to estimat e propagation del ays
2/10
Page 3
74LVX257
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
V
V
I
I
OK
I
I
or I
CC
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
RECOMMENDED OPERATING CONDITIONS
SymbolParameterValueUnit
V
V
V
T
dt/dv
1) Truth T abl e guaranteed: 1.2V to 3.6V
2) V
from 0.8V to 2.0V
IN
Supply Voltage
CC
DC Input Voltage
I
DC Output Voltage-0.5 to VCC + 0.5
O
DC Input Diode Current
IK
DC Output Diode Current
DC Output Current
O
DC VCC or Ground Current
GND
Storage Temperature
stg
Lead Temperature (10 sec)
L
Supply Voltage (note 1)
CC
Input Voltage
I
Output Voltage0 to V
O
Operating Temperature
op
Input Rise and Fall Time (note 2) (V
CC
= 3V)
-0.5 to +7.0V
-0.5 to +7.0V
- 20mA
± 20mA
± 25mA
± 50mA
-65 to +150°C
300°C
2 to 3.6V
0 to 5.5V
CC
-55 to 125°C
0 to 100ns/V
V
V
DC SPECIFICATIONS
SymbolParameter
V
V
V
V
I
I
High Level Input
IH
Voltage
Low Level Input
IL
Voltage
High Level Output
OH
Voltage
Low Level Output
OL
Voltage
High Impedance
OZ
Output Leakage
Current
I
Input Leakage
I
Current
Quiescent Supply
CC
Current
Test ConditionValue
V
(V)
CC
= 25°C
A
Min.Typ. Max.Min.Max. Min. Max.
-40 to 85°C -55 to 125°C
T
2.01.51.51.5
2.02.02.0
3.6
2.42.42.4
2.00.50.50.5
3.60.80.80.8
2.0
3.0
2.0
3.0
3.6
3.6
3.6
IO=-50 µA
I
=-50 µA
O
I
=-4 mA
O
IO=50 µA
I
=50 µA
O
I
=4 mA
O
= VIH or V
V
I
IL
VO = VCC or GND
= 5.5V or GND
V
I
= VCC or GND
V
I
1.92.01.91.9
2.93.02.92.9
2.582.482.4
0.00.10.10.1
0.00.10.10.1
0.360.440.55
±0.25± 2.5± 5µA
± 0.1± 1± 1µA
44040µA
Unit
V3.0
V3.00.80.80.8
V3.0
V3.0
3/10
Page 4
74LVX257
DYNAMIC SWITCHING CHARACTERISTICS
Test ConditionValue
T
SymbolParameter
V
V
Dynamic Low
OLP
Voltage Quiet
OLV
Output (note 1, 2)
V
CC
(V)
3.3
= 25°C
A
Min.Typ. Max.Min.Max. Min. Max.
0.30.5
-0.5-0.3
Dynamic High
V
IHD
Voltage Input
3.32.0
= 50 pF
C
L
(note 1, 3)
Dynamic Low
V
ILD
Voltage Input
3.30.8
(note 1, 3)
1) Worst c ase package.
2) Max number of output s defined as (n). Dat a i nputs are driven 0V to 3.3V, (n -1) outputs switc hi ng and one out put at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V
(V
), f=1MHz.
IHD
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns)
Test ConditionValue
T
SymbolParameter
t
Propagation Delay
PLH
PHL
Time
A, B, to Y
t
3.3
3.3
t
t
Propagation Delay
PLH
Time
PHL
SELECT to Y
3.3
3.3
PZL
PZH
Output Enable
Time
t
t
3.3
3.3
t
t
t
OSLH
t
OSHL
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same directio n, either HIGH or LO W
2) Param eter guarante ed by design
(*) Vol tage rang e i s 3.3V ±
WAVEFORM 2 : PROPAGATION DELAYS FOR NON-INVERTING CONDITIONS
(f=1MHz; 50% duty cycle)
6/10
Page 7
WAVEFORM 3 : OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
74LVX257
7/10
Page 8
74LVX257
SO-16 MECHANICAL DATA
DIM.
A1.750.068
a10.10.20.0030.007
a21.650.064
b0.350.460.0130.018
b10.190.250.0070.010
C0.50.019
c145° (typ.)
D9.8100.3850.393
E5.86.20.2280.244
e1.270.050
e38.890.350
F3.84.00.1490.157
G4.65.30.1810.208
L0.51.270.0190.050
M0.620.024
S8° (max.)
MIN.TYPMAX.MIN.TYP.M AX.
mm.inch
8/10
PO13H
Page 9
74LVX257
TSSOP16 MECHANICAL DATA
mm.inch
DIM.
MIN.TYPMAX.MIN.TYP.M AX.
A1.20.047
A10.050.150.0020.0040.006
A20.811.050.0310.0390.041
b0.190.300.0070.012
c0.090.200.0040.0089
D4.955.10.1930.1970.201
E6.26.46.60.2440.2520.260
E14.34.44.480.1690.1730.176
e0.65 BSC0.0256 BSC
K0°8°0°8°
L0.450.600.750.0180.0240.030
A2
A
A1
b
e
c
K
L
E
D
E1
PIN 1 IDENTIFICATION
1
0080338D
9/10
Page 10
74LVX257
Information furnished is bel ieved to be accurate and reliable. However, STMicroe lectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No li cense is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication ar e subject to change without notice. This publication supersedes and replaces all information
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