Datasheet 74LVX257TTR, 74LVX257MTR, 74LVX257M Datasheet (SGS Thomson Microelectronics)

Page 1
74LVX257
LOW VOLTAGE CMOS QUAD 2 CHANNEL MULTIPLEXER
(3-STATE) WITH 5V TOLERANT INPUTS
HIGH SPEED:
t
=5.8ns (TYP.) at VCC = 3.3V
PD
5V TOLERANT INPUTS
INPUT VOLTAGE LEVEL:
V
= 0.8V, VIH = 2V at VCC =3V
IL
LOW POWER DISSIPATION:
I
= 4 µA (MAX.) at TA=25°C
CC
LOW NOISE:
V
= 0.3V (TYP.) at VCC =3.3V
OLP
SYMMETRICAL OUTPUT IMPEDANCE:
|I
| = IOL = 4 mA (MIN) at VCC =3V
OH
BALANCED PROPAGATION DELAYS:
t
t
PLH
OPERATING VOLTAGE R ANGE:
V
CC
PIN AND FUNCTION COMPATIBLE WITH
PHL
(OPR) = 2V to 3.6V (1.2V Data Retention)
74 SERIES 257
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVX257 i s a low voltage CMOS QUAD 2 CHANNEL MULTIPLEXER (3-STATE) fabricated with sub-micron silicon gate and double-layer metal wiring C
2
MOS technology. It is ideal for low power, battery operated and low noise 3.3V applications. It is composed of four independent 2-channel multiplexers with commo n SELECT and ENABLE (OE
) INPUT. The 74LVX257 is a non-inverting
TSSOPSOP
ORDER CODES
PACKAGE TUBE T & R
SOP 74LVX257M 74LVX257MTR
TSSOP 74LVX257TTR
multiplexer. When the ENABLE INPUT is held "High", all outputs become in high impedance state. If SELECT INPUT is held "L ow", "A" dat a is selected, when SELECT INPUT is "High", "B" data is chosen. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. It combines high speed performance with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against stat ic discharge, giving them 2KV ESD immunity and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/10July 2001
Page 2
74LVX257
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION
1 SELECT Common Data Select
2, 5, 11, 14 1A to 4A Data Inputs From Source
3, 6, 10, 13 1B to 4B Data Inputs From Source
4, 7, 9, 12 1Y to 4Y 3 State Multiplexer
15 OE
8 GND Ground (0V)
16 V
TRUTH TABLE
INPUTS OUTPUT
CC
Inputs
A
B
Outputs 3 State Output Enable
Inputs (Active LOW)
Positive Supply Voltage
OE
HXXXZ
LLLXL LLHXH LHXLL LHXHH
X :Don‘t Care Z : High Impedance
LOGIC DIAGRAM
SELECT A B Y
This log i c diagram has not be used to estimat e propagation del ays
2/10
Page 3
74LVX257
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
V
V
I
I
OK
I
I
or I
CC
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Value Unit
V
V
V
T
dt/dv
1) Truth T abl e guaranteed: 1.2V to 3.6V
2) V
from 0.8V to 2.0V
IN
Supply Voltage
CC
DC Input Voltage
I
DC Output Voltage -0.5 to VCC + 0.5
O
DC Input Diode Current
IK
DC Output Diode Current DC Output Current
O
DC VCC or Ground Current
GND
Storage Temperature
stg
Lead Temperature (10 sec)
L
Supply Voltage (note 1)
CC
Input Voltage
I
Output Voltage 0 to V
O
Operating Temperature
op
Input Rise and Fall Time (note 2) (V
CC
= 3V)
-0.5 to +7.0 V
-0.5 to +7.0 V
- 20 mA
± 20 mA ± 25 mA ± 50 mA
-65 to +150 °C 300 °C
2 to 3.6 V 0 to 5.5 V
CC
-55 to 125 °C 0 to 100 ns/V
V
V
DC SPECIFICATIONS
Symbol Parameter
V
V
V
V
I
I
High Level Input
IH
Voltage
Low Level Input
IL
Voltage
High Level Output
OH
Voltage
Low Level Output
OL
Voltage
High Impedance
OZ
Output Leakage Current
I
Input Leakage
I
Current Quiescent Supply
CC
Current
Test Condition Value
V
(V)
CC
= 25°C
A
Min. Typ. Max. Min. Max. Min. Max.
-40 to 85°C -55 to 125°C
T
2.0 1.5 1.5 1.5
2.0 2.0 2.0
3.6
2.4 2.4 2.4
2.0 0.5 0.5 0.5
3.6 0.8 0.8 0.8
2.0
3.0
2.0
3.0
3.6
3.6
3.6
IO=-50 µA I
=-50 µA
O
I
=-4 mA
O
IO=50 µA I
=50 µA
O
I
=4 mA
O
= VIH or V
V
I
IL
VO = VCC or GND
= 5.5V or GND
V
I
= VCC or GND
V
I
1.9 2.0 1.9 1.9
2.9 3.0 2.9 2.9
2.58 2.48 2.4
0.0 0.1 0.1 0.1
0.0 0.1 0.1 0.1
0.36 0.44 0.55
±0.25 ± 2.5 ± 5 µA
± 0.1 ± 1 ± 1 µA
44040µA
Unit
V3.0
V3.0 0.8 0.8 0.8
V3.0
V3.0
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Page 4
74LVX257
DYNAMIC SWITCHING CHARACTERISTICS
Test Condition Value
T
Symbol Parameter
V V
Dynamic Low
OLP
Voltage Quiet
OLV
Output (note 1, 2)
V
CC
(V)
3.3
= 25°C
A
Min. Typ. Max. Min. Max. Min. Max.
0.3 0.5
-0.5 -0.3
Dynamic High
V
IHD
Voltage Input
3.3 2.0
= 50 pF
C
L
(note 1, 3) Dynamic Low
V
ILD
Voltage Input
3.3 0.8
(note 1, 3)
1) Worst c ase package.
2) Max number of output s defined as (n). Dat a i nputs are driven 0V to 3.3V, (n -1) outputs switc hi ng and one out put at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V (V
), f=1MHz.
IHD
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns)
Test Condition Value
T
Symbol Parameter
t
Propagation Delay
PLH PHL
Time A, B, to Y
t
3.3
3.3 t t
Propagation Delay
PLH
Time
PHL
SELECT to Y
3.3
3.3
PZL PZH
Output Enable Time
t t
3.3
3.3 t
t
t
OSLH
t
OSHL
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch­ing in the same directio n, either HIGH or LO W
2) Param eter guarante ed by design (*) Vol tage rang e i s 3.3V ±
Output Disable
PLZ
Time
PHZ
Output to Output Skew Time (note 1,2)
3.3
3.3
0.3V
C
V
CC
(V)
2.7
2.7
2.7
2.7
L
(pF)
15 7.0 13.0 1.0 15.4 1.0 16.4 50 9.5 18.0 1.0 20.3 1.0 21.3
(*)
15 5.8 9.3 1.0 11.0 1.0 12.0
(*)
50 8.3 12.8 1.0 14.5 1.0 15.5 15 8.5 15.4 1.0 18.2 1.0 20.0 50 10.5 20.3 1.0 23.1 1.0 24.5
(*)
15 7.0 11.0 1.0 13.0 1.0 14.0
(*)
50 9.5 14.5 1.0 16.5 1.0 18.0
2.7 15 8.0 14.7 1.0 17.5 1.0 18.5
2.7 50 10.5 19.6 1.0 22.4 1.0 24.0
(*)
15 6.7 10.5 1.0 12.5 1.0 13.5
(*)
50 9.2 14.0 1.0 16.0 1.0 17.0
2.7 50 9.5 16.8 1.0 18.9 1.0 20.0
(*)
50 8.6 12.0 1.0 13.5 1.0 15.0
2.7 50 0.5 1.0 1.5 1.5
(*)
50 0.5 1.0 1.5 1.5
= 25°C
A
Min. Typ. Max. Min. Max. Min. Max.
-40 to 85°C -55 to 125°C
), 0V to threshold
ILD
-40 to 85°C -55 to 125°C
Unit
V
Unit
ns
ns
ns
ns
ns
4/10
Page 5
74LVX257
CAPACITIVE CHARACTERISTICS
Test Condition Value
T
Symbol Parameter
C
C
C
Input Capacitance
IN
Output
OUT
Capacitance Power Dissipation
PD
Capacitance
V
CC
(V)
3.3 4101010pF
3.3 6 pF
3.3 23 pF
= 25°C
A
Min. Typ. Max. Min. Max. Min. Max.
(note 1)
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (R ef er to Test Circuit). Average operating current can be obta i ned by the followi ng equation. I channel)
TEST CIRCUIT
-40 to 85°C -55 to 125°C
= CPD x VCC x fIN + ICC/4 (per
CC(opr)
Unit
TEST SWITCH
t
, t
PLH
PHL
, t
t
PZL
PLZ
t
, t
PZH
PHZ
CL =15/50pF or equivalent (includes jig and probe capacitance)
= R1 = 1Kor equivalent
R
L
= Z
R
of pulse generator (typically 50)
T
OUT
Open
V
CC
GND
5/10
Page 6
74LVX257
WAVEFORM 1 : PROPAGATION DELAYS FOR INVERTING CONDITIONS (f=1MHz; 50% duty cy cle))
WAVEFORM 2 : PROPAGATION DELAYS FOR NON-INVERTING CONDITIONS
(f=1MHz; 50% duty cycle)
6/10
Page 7
WAVEFORM 3 : OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
74LVX257
7/10
Page 8
74LVX257
SO-16 MECHANICAL DATA
DIM.
A 1.75 0.068 a1 0.1 0.2 0.003 0.007 a2 1.65 0.064
b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010
C 0.5 0.019
c1 45° (typ.)
D 9.8 10 0.385 0.393 E 5.8 6.2 0.228 0.244
e 1.27 0.050 e3 8.89 0.350
F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208
L 0.5 1.27 0.019 0.050
M 0.62 0.024 S8° (max.)
MIN. TYP MAX. MIN. TYP. M AX.
mm. inch
8/10
PO13H
Page 9
74LVX257
TSSOP16 MECHANICAL DATA
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. M AX.
A 1.2 0.047
A1 0.05 0.15 0.002 0.004 0.006
A2 0.8 1 1.05 0.031 0.039 0.041
b 0.19 0.30 0.007 0.012
c 0.09 0.20 0.004 0.0089
D 4.9 5 5.1 0.193 0.197 0.201
E 6.2 6.4 6.6 0.244 0.252 0.260
E1 4.3 4.4 4.48 0.169 0.173 0.176
e 0.65 BSC 0.0256 BSC
K0° 8°0° 8°
L 0.45 0.60 0.75 0.018 0.024 0.030
A2
A
A1
b
e
c
K
L
E
D
E1
PIN 1 IDENTIFICATION
1
0080338D
9/10
Page 10
74LVX257
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