LOW VOLTAGE CMOS 16-BIT D-TYPE FLIP FLOP (3-STATE)
WITH 5V TOLERANT INPUTS
■ HIGH SPEED:
f
= 160 MHz (TYP.) at VCC=3V
MAX
■ 5V TOLERANT INPUTS
■ POWER DOWN PROTECTION ON INPUTS
■ INPUT VOLTAGE LEVEL:
V
=0.8V,VIH=2VatVCC=3V
IL
■ LOW POWER DISSIPATION:
I
=4µA (MAX.) at TA=25°C
CC
■ LOW NOISE:
V
=0.3V(TYP.)atVCC=3.3V
OLP
■ SYMMETRICAL OUTPUT IMPEDANCE:
|I
|=IOL=4mA(MIN)atVCC=3V
OH
■ BALANCED PROPAGATION DELAYS:
≅ t
t
PLH
PHL
■ OPERATING VOLTAGE RANGE:
V
(OPR) = 2V to 3.6V (1.2V Data R etention)
CC
■ PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16373
■
IMPROVED LATCH-UP IMMUNITY
ORDER CODES
PACKAGETUBET & R
TSSOP74LVX16374TTR
PIN CO NNECTION
TSSOP
DESCRIPTION
The 74LVX16374 is a low voltage CMOS 16 BIT
D-TYPE FLIP-FLOP with 3 STATE OUTPUTS
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
These 16 bit D-TYPE flip-flop is controlled by two
clock inputs (CK) and two output enable inputs
(nOE
). The device can be used as two 8-bit
flip-flops or on e 16-bit flip-flop.On the pos itive
transition of the clock, the Q outputs will be set to
the logic state that were setup at the D inputs.
While the (OE
) input is low , the outputs will be in
a normal logic state (high or low logic level); while
OE
is high, the outputs will be in a high impedance
state.The output cont ro l does not affect the int ernal operation of flip-flops; that is, the old data can
be retained or the new data can be entered even
while the outputs are off.Power down protection is
provided on all inputs and 0 to 7V can be accepted
on inputs with no regard to the supply voltage .This
device can be used to interface 5V to 3V. All inputs and outputs are equipped wit h prot ec tion c ircuits against static discharge, giving them 2KV
ESD immunity and transient excess voltage .
1/10February 2003
Page 2
74LVX16374
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN NoSYMBOLNAME AND FUNCTION
11OE
2, 3,5,6,8, 9,
11, 12
13,14,16, 17,
19, 20, 22, 23
242OE
252CKClock Input
36,35,33, 32,
30, 29, 27, 26
47,46,44, 43,
41, 40, 38, 37
481CKClock Input
4, 10, 15, 21,
28, 34, 39, 45
7, 18, 31, 42V
1Q0 to 1Q7 3-State Outputs
2Q0 to 2Q7 3-State Outputs
2D0 to 2D7 Data Inputs
1D0 to 1D7 Data Inputs
GNDGround (0V)
CC
3 State Output Enable
Input (Active LOW)
3 State Output Enable
Input (Active LOW)
Positive Supply Voltage
TRUTH TABLE
INPUTSOUTPUT
OE
HXXZ
LXNO CHANGE
LLL
LHH
X : Don‘t Care
Z : High Impedance
CKDQ
IEC LOGIC SYMBOLS
2/10
Page 3
74LVX16374
LOGIC DIAGRAM
This logic diagram has not to be used to estimate propagation delays
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
V
V
I
I
OK
I
or I
I
CC
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Supply Voltage
CC
DC Input Voltage
I
DC Output Voltage-0.5 to VCC+ 0.5
O
DC Input Diode Current
IK
DC Output Diode Current
DC Output Current
O
DC VCCor Ground Current
GND
Storage Temperature
stg
Lead Temperature (10 sec)
L
-0.5 to +7.0V
-0.5 to +7.0V
V
-20mA
± 20mA
± 25mA
± 50mA
-65 to +150°C
300°C
RECOMMENDED OPERATING CONDITIONS
SymbolParameterValueUnit
V
V
V
T
dt/dv
1) Truth Table guaranteed: 1.2V to 3.6V
2) V
from0.8V to 2.0V
IN
Supply Voltage (note 1)
CC
Input Voltage
I
Output Voltage0 to V
O
Operating Temperature
op
Input Rise and Fall Time (note 2) (V
CC
=3V)
2 to 3.6V
0 to 5.5V
CC
-55 to 125°C
0 to 100ns/V
V
3/10
Page 4
74LVX16374
DC SPECIFICATIONS
SymbolParameter
V
V
V
I
High Level Input
IH
Voltage
V
Low Level Input
IL
Voltage
High Level Output
OH
Voltage
Low Level Output
OL
Voltage
High Impedance
I
OZ
Output Leakage
Current
Input Leakage
I
I
Current
Quiescent Supply
CC
Current
Test ConditionValue
V
(V)
CC
T
A
Min.Typ. Max.Min.Max. Min. Max.
-40 to 85°C -55 to 125°C
= 25°C
2.01.51.51.5
2.02.02.0
3.6
2.42.42.4
2.00.50.50.5
3.60.80.80.8
2.0
3.0
2.0
3.0
3.6
3.6
3.6
IO=-50 µA
=-50 µA
I
O
=-4 mA
I
O
IO=50 µA
=50 µA
I
O
=4 mA
I
O
I=VIH
or V
IL
V
VO=VCCor GND
=5VorGND
V
I
V
I=VCC
or GND
1.92.01.91.9
2.93.02.92.9
2.582.482.4
0.00.10.10.1
0.00.10.10.1
0.360.440.55
±0.25± 2.5± 2.5µA
±0.1± 1± 1µA
44040µA
Unit
V3.0
V3.00.80.80.8
V3.0
V3.0
DYNAMIC SWITCH ING CHARACTERISTICS
Test ConditionValue
= 25°C
SymbolParameter
V
V
Dynamic Low
OLP
Voltage Quiet
OLV
Output (note 1, 2)
V
CC
(V)
3.3
T
A
Min.Typ. Max.Min.Max. Min. Max.
0.30.8
-0.8-0.3
Dynamic High
V
IHD
Voltage Input
3.32.0
C
L
=50pF
(note 1, 3)
Dynamic Low
V
ILD
Voltage Input
3.30.8
(note 1, 3)
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V
(V
), f=1MHz.
IHD
-40 to 85°C -55 to 125°C
ILD
Unit
V
), 0V to threshold
4/10
Page 5
74LVX16374
AC ELECTRICAL CHARACTERISTICS (Input tr=tf=3ns)
Test ConditionValue
= 25°C
SymbolParameter
t
t
Propagation Delay
PLH
Time
PHL
CK to Q
3.3
3.3
t
t
PZH
PZL
Output Enable
Time
3.3
3.3
t
t
PHZ
f
MAX
Output Disable
PLZ
Time
CK pulse Width,
t
W
HIGH
Setup Time D to CK
t
S
HIGH or LOW
Hold Time D to CK
t
h
HIGH or LOW
Maximum Clock
Frequency
3.3
3.3
3.3
3.3
3.3
3.3
t
OSLH
t
OSHL
1) Skew isdefined asthe absolutevalue ofthe difference between theactual propagation delay for anytwo outputs of the same device switching in the same direction, either HIGH or LOW
2) Parameter guaranteed by design
(*) Voltagerange is 3.3V ± 0.3V
Output to Output
Skew Time (note
1,2)
3.3
C
V
CC
(V)
2.7
2.7
L
(pF)
159.516.31.019.51.020.5
5011.019.81.023.01.024.0
(*)
15915117117
(*)
5010.616.2118.5118.5
2.7158.614.51.017.51.018.5
2.75010.118.01.021.01.022.0
(*)
15813115115
(*)
509.614.9116116
2.75011.518.51.022.01.023.0
(*)
509.613.21.015.01.016.0
2.7505555
(*)
505555
2.7504.544
(*)
50333
2.750222
(*)
50222
2.715601155045
2.75045604035
(*)
151001608575
(*)
5080130707080
2.7500.51.01.51.5
(*)
500.51.01.51.5
T
A
Min.Typ. Max.Min.Max. Min. Max.
-40 to 85°C -55 to 125°C
Unit
ns
ns
ns
ns
ns
ns
MHz
ns
CAPACITIVE CHARACTERISTICS
Test ConditionValue
= 25°C
SymbolParameter
V
CC
(V)
C
C
C
Input Capacitance
IN
Output
OUT
Capacitance
Power Dissipation
PD
Capacitance
3.0
= 10MHz
f
IN
T
A
Min.Typ. Max.Min.Max. Min. Max.
2.5101010pF
4pF
17pF
(note 1)
1) CPDis defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
circuit)
-40 to 85°C -55 to 125°C
CC(opr)=CPDxVCCxfIN+ICC
Unit
/16 (per
5/10
Page 6
74LVX16374
TEST CIRCUIT
TESTSWITCH
t
PLH,tPHL
t
PZL,tPLZ
t
PZH,tPHZ
CL= 15/50 pF or equivalent (includes jig and probe capacitance)
R
=R1=1KΩ or equivalent
L
R
T=ZOUT
of pulse generator (typically 50Ω)
Open
V
CC
GND
WAVEFORM 1 PROPAGATION DELAYS, SETUP AND HOLD TIMES, MAXIMUM CLOCK
FREQUENCY (f=1MHz; 50% duty cycle)
6/10
Page 7
WAVEFORM 2: OUTPUT ENABLE AND D ISABLE TIME (f= 1MHz; 50% duty cycle)
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use o f suc h inf ormat ion n or f or an y infr ingeme nt of paten ts or oth er ri gh ts of third part ies whic h may resul t f rom
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco