Datasheet 74LVX16374TTR Datasheet (SGS Thomson Microelectronics)

Page 1
74LVX16374
LOW VOLTAGE CMOS 16-BIT D-TYPE FLIP FLOP (3-STATE)
WITH 5V TOLERANT INPUTS
HIGH SPEED:
f
= 160 MHz (TYP.) at VCC=3V
MAX
5V TOLERANT INPUTS
INPUT VOLTAGE LEVEL:
V
=0.8V,VIH=2VatVCC=3V
IL
LOW POWER DISSIPATION:
I
=4µA (MAX.) at TA=25°C
CC
LOW NOISE:
V
=0.3V(TYP.)atVCC=3.3V
OLP
SYMMETRICAL OUTPUT IMPEDANCE:
|I
|=IOL=4mA(MIN)atVCC=3V
OH
BALANCED PROPAGATION DELAYS:
t
t
PLH
PHL
OPERATING VOLTAGE RANGE:
V
(OPR) = 2V to 3.6V (1.2V Data R etention)
CC
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16373
IMPROVED LATCH-UP IMMUNITY
ORDER CODES
PACKAGE TUBE T & R
TSSOP 74LVX16374TTR
PIN CO NNECTION
TSSOP
DESCRIPTION
The 74LVX16374 is a low voltage CMOS 16 BIT D-TYPE FLIP-FLOP with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C
2
MOS technology. It is ideal for low power, battery operated and low noise 3.3V applications.
These 16 bit D-TYPE flip-flop is controlled by two clock inputs (CK) and two output enable inputs (nOE
). The device can be used as two 8-bit flip-flops or on e 16-bit flip-flop.On the pos itive transition of the clock, the Q outputs will be set to the logic state that were setup at the D inputs. While the (OE
) input is low , the outputs will be in a normal logic state (high or low logic level); while OE
is high, the outputs will be in a high impedance state.The output cont ro l does not affect the int er­nal operation of flip-flops; that is, the old data can be retained or the new data can be entered even while the outputs are off.Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage .This device can be used to interface 5V to 3V. All in­puts and outputs are equipped wit h prot ec tion c ir­cuits against static discharge, giving them 2KV ESD immunity and transient excess voltage .
1/10February 2003
Page 2
74LVX16374
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION
1 1OE
2, 3,5,6,8, 9,
11, 12
13,14,16, 17,
19, 20, 22, 23
24 2OE
25 2CK Clock Input
36,35,33, 32,
30, 29, 27, 26
47,46,44, 43,
41, 40, 38, 37
48 1CK Clock Input
4, 10, 15, 21, 28, 34, 39, 45
7, 18, 31, 42 V
1Q0 to 1Q7 3-State Outputs
2Q0 to 2Q7 3-State Outputs
2D0 to 2D7 Data Inputs
1D0 to 1D7 Data Inputs
GND Ground (0V)
CC
3 State Output Enable Input (Active LOW)
3 State Output Enable Input (Active LOW)
Positive Supply Voltage
TRUTH TABLE
INPUTS OUTPUT
OE
HXX Z
L X NO CHANGE LLL LHH
X : Don‘t Care Z : High Impedance
CK D Q
IEC LOGIC SYMBOLS
2/10
Page 3
74LVX16374
LOGIC DIAGRAM
This logic diagram has not to be used to estimate propagation delays
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
V
V
I
I
OK
I
or I
I
CC
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied
Supply Voltage
CC
DC Input Voltage
I
DC Output Voltage -0.5 to VCC+ 0.5
O
DC Input Diode Current
IK
DC Output Diode Current DC Output Current
O
DC VCCor Ground Current
GND
Storage Temperature
stg
Lead Temperature (10 sec)
L
-0.5 to +7.0 V
-0.5 to +7.0 V V
-20 mA
± 20 mA ± 25 mA ± 50 mA
-65 to +150 °C
300 °C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Value Unit
V
V
V
T
dt/dv
1) Truth Table guaranteed: 1.2V to 3.6V
2) V
from0.8V to 2.0V
IN
Supply Voltage (note 1)
CC
Input Voltage
I
Output Voltage 0 to V
O
Operating Temperature
op
Input Rise and Fall Time (note 2) (V
CC
=3V)
2 to 3.6 V 0 to 5.5 V
CC
-55 to 125 °C 0 to 100 ns/V
V
3/10
Page 4
74LVX16374
DC SPECIFICATIONS
Symbol Parameter
V
V
V
I
High Level Input
IH
Voltage
V
Low Level Input
IL
Voltage
High Level Output
OH
Voltage
Low Level Output
OL
Voltage
High Impedance
I
OZ
Output Leakage Current
Input Leakage
I
I
Current Quiescent Supply
CC
Current
Test Condition Value
V
(V)
CC
T
A
Min. Typ. Max. Min. Max. Min. Max.
-40 to 85°C -55 to 125°C
= 25°C
2.0 1.5 1.5 1.5
2.0 2.0 2.0
3.6
2.4 2.4 2.4
2.0 0.5 0.5 0.5
3.6 0.8 0.8 0.8
2.0
3.0
2.0
3.0
3.6
3.6
3.6
IO=-50 µA
=-50 µA
I
O
=-4 mA
I
O
IO=50 µA
=50 µA
I
O
=4 mA
I
O
I=VIH
or V
IL
V
VO=VCCor GND
=5VorGND
V
I
V
I=VCC
or GND
1.9 2.0 1.9 1.9
2.9 3.0 2.9 2.9
2.58 2.48 2.4
0.0 0.1 0.1 0.1
0.0 0.1 0.1 0.1
0.36 0.44 0.55
±0.25 ± 2.5 ± 2.5 µA
±0.1 ± 1 ± 1 µA
44040µA
Unit
V3.0
V3.0 0.8 0.8 0.8
V3.0
V3.0
DYNAMIC SWITCH ING CHARACTERISTICS
Test Condition Value
= 25°C
Symbol Parameter
V V
Dynamic Low
OLP
Voltage Quiet
OLV
Output (note 1, 2)
V
CC
(V)
3.3
T
A
Min. Typ. Max. Min. Max. Min. Max.
0.3 0.8
-0.8 -0.3
Dynamic High
V
IHD
Voltage Input
3.3 2.0
C
L
=50pF
(note 1, 3) Dynamic Low
V
ILD
Voltage Input
3.3 0.8
(note 1, 3)
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V (V
), f=1MHz.
IHD
-40 to 85°C -55 to 125°C
ILD
Unit
V
), 0V to threshold
4/10
Page 5
74LVX16374
AC ELECTRICAL CHARACTERISTICS (Input tr=tf=3ns)
Test Condition Value
= 25°C
Symbol Parameter
t t
Propagation Delay
PLH
Time
PHL
CK to Q
3.3
3.3 t t
PZH
PZL
Output Enable Time
3.3
3.3 t
t
PHZ
f
MAX
Output Disable
PLZ
Time CK pulse Width,
t
W
HIGH Setup Time D to CK
t
S
HIGH or LOW Hold Time D to CK
t
h
HIGH or LOW Maximum Clock
Frequency
3.3
3.3
3.3
3.3
3.3
3.3
t
OSLH
t
OSHL
1) Skew isdefined asthe absolutevalue ofthe difference between theactual propagation delay for anytwo outputs of the same device switch­ing in the same direction, either HIGH or LOW
2) Parameter guaranteed by design (*) Voltagerange is 3.3V ± 0.3V
Output to Output Skew Time (note 1,2)
3.3
C
V
CC
(V)
2.7
2.7
L
(pF)
15 9.5 16.3 1.0 19.5 1.0 20.5 50 11.0 19.8 1.0 23.0 1.0 24.0
(*)
15 915117117
(*)
50 10.6 16.2 1 18.5 1 18.5
2.7 15 8.6 14.5 1.0 17.5 1.0 18.5
2.7 50 10.1 18.0 1.0 21.0 1.0 22.0
(*)
15 813115115
(*)
50 9.6 14.9 1 16 1 16
2.7 50 11.5 18.5 1.0 22.0 1.0 23.0
(*)
50 9.6 13.2 1.0 15.0 1.0 16.0
2.7 50 5 5 5 5
(*)
50 5 5 5 5
2.7 50 4.5 4 4
(*)
50 3 3 3
2.7 50 2 2 2
(*)
50 2 2 2
2.7 15 60 115 50 45
2.7 50 45 60 40 35
(*)
15 100 160 85 75
(*)
50 80 130 70 70 80
2.7 50 0.5 1.0 1.5 1.5
(*)
50 0.5 1.0 1.5 1.5
T
A
Min. Typ. Max. Min. Max. Min. Max.
-40 to 85°C -55 to 125°C
Unit
ns
ns
ns
ns
ns
ns
MHz
ns
CAPACITIVE CHARACTERISTICS
Test Condition Value
= 25°C
Symbol Parameter
V
CC
(V)
C
C
C
Input Capacitance
IN
Output
OUT
Capacitance Power Dissipation
PD
Capacitance
3.0
= 10MHz
f
IN
T
A
Min. Typ. Max. Min. Max. Min. Max.
2.5 10 10 10 pF 4pF
17 pF
(note 1)
1) CPDis defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I circuit)
-40 to 85°C -55 to 125°C
CC(opr)=CPDxVCCxfIN+ICC
Unit
/16 (per
5/10
Page 6
74LVX16374
TEST CIRCUIT
TEST SWITCH
t
PLH,tPHL
t
PZL,tPLZ
t
PZH,tPHZ
CL= 15/50 pF or equivalent (includes jig and probe capacitance) R
=R1=1KΩ or equivalent
L
R
T=ZOUT
of pulse generator (typically 50)
Open
V
CC
GND
WAVEFORM 1 PROPAGATION DELAYS, SETUP AND HOLD TIMES, MAXIMUM CLOCK FREQUENCY (f=1MHz; 50% duty cycle)
6/10
Page 7
WAVEFORM 2: OUTPUT ENABLE AND D ISABLE TIME (f= 1MHz; 50% duty cycle)
74LVX16374
WAVEFORM 3 : CLO CK PULSE WIDTH (f=1MHz; 50% duty cycle)
7/10
Page 8
74LVX16374
TSSOP48 MECHANICAL DATA
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 1.2 0.047
A1 0.05 0.15 0.002 0.006
A2 0.9 0.035
b 0.17 0.27 0.0067 0.011
c 0.09 0.20 0.0035 0.0079
D 12.4 12.6 0.488 0.496
E 8.1 BSC 0.318 BSC
E1 6.0 6.2 0.236 0.244
e 0 .5 BSC 0.0197 BSC
K0˚ 8˚0˚ 8˚
L 0.50 0.75 0.020 0.030
A2
A
A1
b
e
D
K
c
E1
L
E
PIN 1 IDENTIFICATION
8/10
1
7065588C
Page 9
74LVX16374
Tape & Reel TSSOP48 MECHANICAL DATA
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 330 12.992 C 12.8 13.2 0.504 0.519 D 20.2 0.795 N 60 2.362
T 30.4 1.197 Ao 8.7 8.9 0.343 0.350 Bo 13.1 13.3 0.516 0.524 Ko 1.5 1.7 0.059 0.067 Po 3.9 4.1 0.153 0.161
P 11.9 12.1 0.468 0.476
9/10
Page 10
74LVX16374
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use o f suc h inf ormat ion n or f or an y infr ingeme nt of paten ts or oth er ri gh ts of third part ies whic h may resul t f rom its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco
© The ST logo is a registered trademark of STMicroelectronics
© 2003 STMicroelectronics - Printed in Italy - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.
© http://www.st.com
10/10
Loading...