Datasheet 74LVTH16244MTD, 74LVTH16244MEAX, 74LVTH16244MEA, 74LVTH16244MTDX Datasheet (Fairchild Semiconductor)

© 1999 Fairchild Semiconductor Corporation DS500151 www.fairchildsemi.com

Print form created on April 12, 1999 2:43 pm

March 1999
Revised April 1999

74LVT16244 • 74LVTH16244 Low Voltage16-Bit Buffer/Line Driver with 3-STATE Outputs

74LVT16244 • 74LVTH16244
Low Voltage16-Bit Buffer/Line Driver

with 3-STATE Outputs

General Description

The LVT16244 and LVTH16244 contain sixteen non-invert­ing buffers with 3-STATE outputs designed to be employed
as a memory and address driver, clock driver, or bus ori­ented transmitter/rece iver. The device is nibble controlled.
Individual 3-STATE control inputs can be shorte d together
for 8-bit or 16-bit operation.

The LVTH16244 data inputs includ e bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.

These buffers and line drivers are designed for low-voltage
(3.3V) V

CC

applications, but with the capability to provide a

TTL interface to a 5V environment. The LVT16244 and
LVTH16244 are fabricated with an advanced BiCMOS

technology to achieve high speed operation si milar to 5V
ABT while maintaining a low power dissipation

Features

■ Input and output interface capa bility to systems at 5V
V

CC

■ Bushold data inputs elimina te the nee d for exte rnal pul l­up resistors to hold unused inputs (74LVTH16244), also
available without bushold feature (74LVT16244).

■ Live insertion/extraction per mitt ed

■ Power Up/Down high impedance provides glitch-free

bus loading

■ Outputs source/sink −32 mA/+64 mA

■ Functionally compatible with the 74 series 16244

■ Latch-up performance exceeds 500 mA

Ordering Code:

Device also available in Tape and Reel. Specify by appending su ffix le tter “X” to the ordering code.

Logic Symbol

Order Number Package

Number

Package Descript ion

74LVT16244MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LVT16244MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH16244MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LVTH16244MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

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74LVT16244 • 74LVTH16244

Connection Diagram

Functional Description

The LVT16244 and LVTH16244 contain sixteen non-invert­ing buffers with 3 -STATE outputs. The devi ce is nibble (4
bits) controlled with ea ch nibble functi oning identically, but
independent of the oth er. The control pins can be shorted
together to obtain full 16-bit operation.

Pin Descriptions

Tr uth Table

H = High Voltage Level
L = Low Voltage Level
X = Immaterial
Z = High Impedance

Logic Diagram

Pin Names Description

OE

n

Output Enable Inputs (Active Low)

I

0–I15

Inputs

O

0–O15

Outputs

Inputs Outputs

OE

1

I0–I

3

O0–O

3

LL L
LH H
HX Z

Inputs Outputs

OE

2

I4–I

7

O4–O

7

LL L
LH H
HX Z

Inputs Outputs

OE

3

I8–I

11

O8–O

11

LL L
LH H
HX Z

Inputs Outputs

OE

4

I12–I

15

O12–O

15

LL L
LH H
HX Z

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74LVT16244 • 74LVTH16244

Absolute Maximum Ratings(Note 1)

Recommended Operating Conditions

Note 1: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. E xposure to these conditions or conditions

beyond those indica te d m ay adversely affect dev ic e reliability. Functional operation under absolute maxim um rated conditions is not imp lied.
Note 2: I

O

Absolute Maximum Rating must be observed.

DC Electrical Characteristics

Symbol Parameter Value Conditions Units

V

CC

Supply Voltage −0.5 to +4.6 V

V

I

DC Input Voltage −0.5 to +7.0 V

V

O

Output Voltage −0.5 to +7.0 Output in 3-STATE

V

−0.5 to +7.0 Output in High or Low State (Note 2)

I

IK

DC Input Diode Current −50 VI < GND mA

I

OK

DC Output Diode Current −50 VO < GND mA

I

O

DC Output Current 64 VO > VCCOutput at HIGH State

mA

128 V

O

> VCCOutput at LOW State

I

CC

DC Supply Current per Supply Pin ±64 mA

I

GND

DC Ground Current per Ground Pin ±128 mA

T

STG

Storage Temperature −65 to +150 °C

Symbol Parameter Min Max Units

V

CC

Supply Voltage 2.7 3.6 V

V

I

Input Voltage 0 5.5 V

I

OH

High-Level Output Current −32 mA

I

OL

Low-Level Output Current 64 mA

T

A

Free Air Operating Temperature −40 +85 °C

∆t/∆V Input Edge Rate, V

IN

= 0.8V–2.0V, VCC = 3.0V 0 10 ns/V

Symbol Parameter

V

CC

(V)

TA = −40°C to +85°C

Units Conditions

Min Typ Max

(Note 3)

V

IK

Input Clamp Diode Voltage 2.7 −1.2 V II = −18 mA

V

IH

Input HIGH Voltage 2.7–3.6 2.0 V VO ≤ 0.1V or

V

IL

Input LOW Voltage 2.7–3.6 0.8 V VO ≥ VCC − 0.1V

V

OH

Output HIGH Voltage 2.7–3.6 VCC − 0.2

V

IOH = −100 µA

2.7 2.4 IOH = −8 mA

3.0 2.0 IOH = −32 mA

V

OL

Output LOW Voltage 2.7 0.2

V

IOL = 100 µA

2.7 0.5 IOL = 24 mA

3.0 0.4 IOL = 16 mA

3.0 0.5 IOL = 32 mA

3.0 0.55 IOL = 64 mA

I

I(HOLD)

Bushold Input Minimum Drive 3.0 75

µA

VI = 0.8V
(Note 4) −75 VI = 2.0V
I

I(OD)

(Note 4)

Bushold Input Over-Drive
Current to Change State

3.0 500
µA

(Note 5)

−500 (Note 6)

I

I

Input Current 3.6 10

µA

VI = 5.5V

Control Pins 3.6 ±1V

I

= 0V or V

CC

Data Pins 3.6 −5V

I

= 0V

1V

I

= V

CC

I

OFF

Power Off Leakage Current 0 ±100 µA0V ≤ VI or VO ≤ 5.5V

I

PU/PD

Power Up/Down 0 – 1.5V ±100 µAVO = 0.5V to 3.0V
3-STATE Current VI = GND or V

CC

I

OZL

3-STATE Output Leakage Current 3.6 −5 µAVO = 0.5V

I

OZH

3-STATE Output Leakage Current 3.6 5 µAVO = 3.0V

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74LVT16244 • 74LVTH16244

DC Electrical Characteristics (Continued)

Note 3: All typical va lues are at VCC = 3.3V, TA = 25°C.
Note 4: Applies tob us hold versions only (LVTH16244).

Note 5: An externa l driv er must source at leas t the specified current to s w it c h f rom LOW to HIGH.
Note 6: An externa l driv er must sink at least the sp ec if ied current to switch from H I GH to LOW.
Note 7: This is the increase in supply current f or each input that is at the spe c if ied voltage level rather t han V

CC

or GND.

Dynamic Switching Characteristics (Note 8)

Note 8: Characteriz ed in SSOP package. Guaranteed parameter, but not tested.
Note 9: Max number of outputs defined a s (n ). n−1 data inputs are driven 0V to 3V. Output under test held LOW.

AC Electrical Characteristics

Note 10: All typical v alues are at VCC = 3.3V, TA = 25°C.
Note 11: Skew is defined as the ab s olute value of the difference betwe en the actual propagation dela y for any two separate outputs of the same device. The

specification applies to any outputs swit c hing in the same direction, eit her HIGH to LOW (t

OSHL

) or LOW to HIGH (t

OSLH

).

Capacitance (Note 12)

Note 12: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.

Symbol Parameter

V

CC

(V)

TA = −40°C to +85°C

Units Conditions

Min Typ Max

(Note 3)

I

OZH

+ 3-STATE Output Leakage Current 3.6 10 µAVCC < VO ≤ 5.5V

I

CCH

Power Supply Current 3.6 0.19 mA Outputs High

I

CCL

Power Supply Current 3.6 5.0 mA Outputs Low

I

CCZ

Power Supply Current 3.6 0.19 mA Outputs Disabled

I

CCZ

+ Power Supply Current 3.6 0.19 mA VCC ≤ VO ≤ 5.5V,

Outputs Disabled

∆I

CC

Increase in Power Supply Current 3.6 0.2 mA One Input at VCC − 0.6V
(Note 7) Other Inputs at VCC or GND

Symbol Parameter

V

CC

(V)

TA = 25°C

Units

Conditions

CL = 50 pF, RL = 500Ω

Min Typ Max

V

OLP

Quiet Output Maximum Dynamic V

OL

3.3 0.8 V (Note 9)

V

OLV

Quiet Output Minimum Dynamic V

OL

3.3 −0.8 V (Note 9)

Symbol Parameter

TA = −40°C to +85°C

Units

CL = 50 pF, RL = 500Ω

VCC = 3.3V ±0.3V VCC = 2.7V

Min Typ Max Min Max

(Note 10)

t

PLH

Propagation Delay Data to Output 1.2 3.5 1.2 3.9

ns

t

PHL

1.2 3.5 1.2 3.9

t

PZH

Output Enable Time 1.2 4.0 1.2 5.0

ns

t

PZL

1.2 5.0 1.2 6.5

t

PHZ

Output Disable Time 2.0 4.7 2.0 5.2

ns

t

PLZ

1.5 4.2 1.5 4.4

t

OSHL

Output to Output Skew 1.0 1.0 ns

t

OSLH

(Note 11)

Symbol Parameter Conditions Typical Units

C

IN

Input Capacitance VCC = 0V, VI = 0V or V

CC

4pF

C

OUT

Output Capacitance VCC = 3.0V, VO = 0V or V

CC

8pF

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74LVT16244 • 74LVTH16244 Low Voltage16-Bit Buffer/Line Driver with 3-STAT E Outputs

Physical Dimensions inches (millimeters) unless otherwise noted

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide

Package Number MS48A

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Package Number MTD48

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74LVT16244 • 74LVTH16244

Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
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SEMICONDUCTOR CORPORATION. As used herein:

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which, (a) are intended for surgical implant into the
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to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea­sonably expected to result in a significant inju ry to the
user.

2. A critical component i n any compon ent of a lif e support
device or system whose failu re to perform can be rea­sonably expected to ca use the fa i lure of the life su pp ort
device or system, or to affect its safety or effectiveness.

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