Page 1
INTEGRATED CIRCUITS
74LVT74
3.3V Dual D-type flip-flop
Product specification 1996 Aug 28
IC24 Data Handbook
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Philips Semiconductors Product specification
74L VT743.3V Dual D-type flip-flop
QUICK REFERENCE DATA
CONDITIONS
SYMBOL PARAMETER
IN
CC
Propagation
delay
CPn to Qn
Input
capacitance
Total supply
current
t
PLH
t
PHL
C
I
T
CL = 50pF;
V
CC
VI = 0V or 3.0V 3 pF
VCC = 3.6V 0.5 mA
PIN CONFIGURATION
1
D0
R
2
D0
3
CP0
4
S
D0
5
Q0
6
Q
0
GND
LOGIC SYMBOL
D0 D1
CP0
S
D0
D0
R
CP1
D1
S
RD1
Q0 Q0Q1Q1
56 98
VCC = Pin 14
GND = Pin 7
3
4
1
11
10
13
= 25°C;
amb
GND = 0V
= 3.3V
212
DESCRIPTION
The 74LVT74 is a dual positive edge-triggered D-type flip-flop
TYPICAL UNIT
featuring individual data, clock, set, and reset inputs; also true and
complementary outputs. Set (S
D) and reset (RD) are asynchronous
active low inputs and operate independently of the clock input.
3.1
3.6
ns
When set and reset are inactive (high), data at the D input is
transferred to the Q and Q
outputs on the low-to-high transition of
the clock. Data must be stable just one setup time prior to the
low-to-high transition of the clock for predictable operation. Clock
triggering occurs at a voltage level and is not directly related to the
transition time of the positive-going pulse. Following the hold time
interval, data at the D input may be changed without affecting the
levels of the output.
PIN DESCRIPTION
14
V
CC
13
D1
R
12
D1
11
CP1
10
SD1
9
Q1
87
Q1
SF00045
SA00359
PIN NUMBER SYMBOL NAME AND FUNCTION
2, 12 D0, D1 Data inputs
3, 11 CP0, CP1 Clock inputs (active rising edge)
4, 10 SD0, SD1 Set inputs (active LOW)
1, 13 RD0, RD1 Reset inputs (active LOW)
5, 6, 8, 9 Qn, Qn Data outputs
LOGIC SYMBOL (IEEE/IEC)
4
3
2
1
10
11
12
13
&
S
C1
1D
R
S
C2
2D
R
5
6
9
8
SF00047
ORDERING INFORMA TION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
14-Pin Plastic SO –40°C to +85°C 74LVT74 D 74LVT74 D SOT108-1
14-Pin Plastic SSOP –40°C to +85°C 74LVT74 DB 74LVT74 DB SOT337-1
14-Pin Plastic TSSOP –40°C to +85°C 74LVT74 PW 74LVT74PW DH SOT402-1
1996 Aug 28 853-1872 17244
2
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Philips Semiconductors Product specification
I
DC out ut current
mA
SYMBOL
PARAMETER
UNIT
74LVT743.3V Dual D-type flip-flop
LOGIC DIAGRAM
4, 10
S
D
1, 13
D
R
3, 11
CP
5, 9
6, 8
Q
Q
FUNCTION TABLE
INPUTS OUTPUTS
SD RD CP D Q Q
L H X X H L Asynchronous set
H L X X L H Asynchronous reset
L L X X H H Undetermined*
H H ↑ h H L Load “1”
H H ↑ l L H Load “0”
OPERATING
MODE
H H ↑ X NC NC Hold
D
VCC = Pin 14
GND = Pin 7
2, 12
SF00048
NOTES:
H = High voltage level
h = High voltage level one setup time prior to low-to-high
clock transition
L = Low voltage level
l = Low voltage level one setup time prior to low-to-high
clock transition
NC= No change from the previous setup
X = Don’t care
↑ = Low-to-high clock transition
= Not low-to-high clock transition
↑
* = This setup is unstable and will change when either set
or reset return to the high level.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
OUT
T
stg
DC supply voltage –0.5 to +4.6 V
DC input diode current VI < 0 –50 mA
DC input voltage
DC output diode current VO < 0 –50 mA
DC output voltage
p
Storage temperature range –65 to 150 °C
PARAMETER CONDITIONS RATING UNIT
3
3
1, 2
–0.5 to +7.0 V
Output in Off or High state –0.5 to +7.0 V
Output in High state –32
Output in Low state 64
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
1996 Aug 28
LIMITS
MIN MAX
V
CC
V
V
V
I
OH
I
OL
DC supply voltage 2.7 3.6 V
Input voltage 0 5.5 V
I
High-level input voltage 2.0 V
IH
Low-level Input voltage 0.8 V
IL
High-level output current –20 mA
Low-level output current 32 mA
∆t/∆v Input transition rise or fall rate; Outputs enabled 10 ns/V
T
amb
Operating free-air temperature range –40 +85 °C
3
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Philips Semiconductors Product specification
IIIn ut leakage current
µA
ns
74LVT743.3V Dual D-type flip-flop
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions
Voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL
V
IK
Input clamp voltage VCC = 2.7V; IIK = –18mA –1.2 V
PARAMETER
VCC = 2.7 to 3.6V; IOH = –100µA VCC–0.2
V
OH
High-level output voltage
VCC = 2.7V; IOH = –6mA 2.4
VCC = 3.0V; IOH = –20mA 2.0
VCC = 2.7V; IOL = 100µA 0.2
V
OL
Low-level output voltage
VCC = 2.7V; IOL = 24mA 0.5
VCC = 3.0V; IOL = 32mA 0.5
VCC = 0 or 3.6V; VI = 5.5V 10
VCC = 3.6V; VI = VCC or GND ±1
VCC = 3.6V; Outputs High, VI = GND or
V
CC,
VCC = 3V to 3.6V; One input at VCC–0.6V,
2
Other inputs at V
I
∆I
OFF
I
CC
CC
C
p
Output off current VCC = 0V; VI or VO = 0 to 4.5V ±100 µA
Quiescent supply current
Additional supply current per input pin
I
Input capacitance VI = 3V or 0 3 pF
NOTES:
1. All typical values are at V
2. This is the increase in supply current for each input at the specificed voltage level other than V
= 3.3V and T
CC
amb
= 25°C.
TEST CONDITIONS Temp = -40°C to +85°C UNIT
MIN TYP1MAX
I
0
O =
or GND
CC
or GND.
CC
0.5 1 mA
V
V
0.2 µA
AC CHARACTERISTICS
GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω; T
SYMBOL PARAMETER WAVEFORM VCC = 3.3V ± 0.3V VCC = 2.7V UNIT
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
Maximum clock frequency 1 150 345 MHz
Propagation delay
CPn to Qn or Q
n
Propagation delay
Dn, RDn to Qn or Qn
S
NOTE:
1. All typical values are at V
= 3.3V and T
CC
amb
= –40°C to +85°C.
amb
= 25°C.
LIMITS
3.1
3.6
3.1
3.0
1
MAX MAX
4.8
5.0
5.0
4.4
5.8
5.0
6.2
4.8
MIN TYP
1
2
1.0
1.0
1.0
1.0
AC SETUP REQUIREMENTS
LIMITS
SYMBOL PARAMETER WAVEFORM VCC = 3.3V ± 0.3V VCC = 2.7V UNIT
MIN TYP MIN
tS (H)
(L)
t
S
t
(H)
h
(L)
t
h
tW (H)
(L)
t
W
tW (L) SDn, RDn Pulse Width 2 2.0 1.0 3.0
t
rec
Setup time
Dn to CPn
Holdtime
Dn to CPn
CPn Pulse Width 1
Recovery time
Dn, RDn tp CPn
S
1
1
1.7
1.4
0.3
0
2.0
2.0
0.6
0.4
–0.3
–0.6
1.0
1.2
1.8
1.6
0.3
3.0
3.0
3 0.5 –0.3 0.5
0
ns
ns
ns
ns
1996 Aug 28
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Philips Semiconductors Product specification
74LVT743.3V Dual D-type flip-flop
AC WAVEFORMS
VM = 1.5V, VIN = GND to 2.7V
Dn
CPn
V
tsu(L) th(L)
Qn
Qn
V
M
M
1/f
max
V
M
t
PLH
t
PHL
tw(H)
V
M
V
M
V
M
V
tsu(H) th(H)
t
(L)
w
M
Waveform 1. Propagation delay for data to output,
data setup time and hold times, and clock width,
and maximum clock frequency
t
PLH
t
PHL
tw(L)
V
M
(L)
t
t
PHL
t
PLH
w
V
M
V
M
V
M
V
M
V
M
V
M
SF00050
V
M
V
M
t
PHL
V
M
t
PLH
V
M
SF00049
SDn
V
M
RDn
Qn
Qn
Waveform 2. Propagation delay for set and reset to output,
set and reset pulse width
SDn or RDn
CPn
V
M
t
rec
V
M
SF00051
Waveform 3. Recovery time for set or reset to clock
TEST CIRCUIT AND WAVEFORMS
V
CC
PULSE
GENERATOR
V
IN
D.U.T.
R
T
V
OUT
C
L
Test Circuit for Outputs
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value.
= Load capacitance includes jig and probe capacitance;
C
L
see AC CHARACTERISTICS for value.
= T ermination resistance should be equal to Z
R
T
pulse generators.
OUT
t
90%
NEGATIVE
PULSE
R
L
POSITIVE
PULSE
10%
V
M
10% 10%
t
THL
t
TLH
90% 90%
V
M
W
V
M
(tF)
(tR)t
V
M
t
W
90%
10%
t
TLH
THL
AMP (V)
0V
(tR)
(tF)
AMP (V)
0V
VM = 1.5V
Input Pulse Definition
INPUT PULSE REQUIREMENTS
FAMILY
Amplitude Rep. Rate t
t
W
t
R
F
74LVT 2.7V ≤10MHz 500ns ≤2.5ns ≤2.5ns
of
SV00022
1996 Aug 28
5
Page 6
Philips Semiconductors Product specification
74L VT743.3V Dual D-type flip-flop
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
1996 Aug 28
6
Page 7
Philips Semiconductors Product specification
74LVT743.3V Dual D-type flip-flop
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1
1996 Aug 28
7
Page 8
Philips Semiconductors Product specification
74LVT743.3V Dual D-type flip-flop
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
1996 Aug 28
8
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Philips Semiconductors Product specification
74LVT743.3V Dual D-type flip-flop
NOTES
1996 Aug 28
9
Page 10
Philips Semiconductors Product specification
74LVT743.3V Dual D-type flip-flop
DEFINITIONS
Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICA TIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation
register eligible circuits under the Semiconductor Chip Protection Act.
Copyright Philips Electronics North America Corporation 1996
All rights reserved. Printed in U.S.A.
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