Datasheet 74LVT573PW, 74LVT573DB, 74LVT573D Datasheet (Philips)

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Page 1

INTEGRATED CIRCUITS

74LVT573

3.3V Octal D-type transparent latch (3-State)

Product specification Supersedes data of 1995 Nov 14 IC23 Data Handbook

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1998 Feb 19

Page 2

Philips Semiconductors Product specification

3.3V Octal D-type transparent latch (3-State)

FEA TURES

•Inputs and outputs on opposite side of package allow easy

interface to microprocessors

•3-State output buffers

•Common output enable

•TTL input and output switching levels

•Input and output interface capability to systems at 5V supply

•Bus-hold data inputs eliminate the need for external pull-up

resistors to hold unused inputs

•Live insertion/extraction permitted

•No bus current loading when output is tied to 5V bus

•Latch-up protection exceeds 500mA per JEDEC Std 17

•Power-up 3-State

•Power-up reset

•ESD protection exceeds 2000V per MIL STD 883 Method 3015

and 200V per Machine Model

QUICK REFERENCE DATA

SYMBOL PARAMETER

PLH

PHL

CCZ

OUT

Propagation delay Dn to Qn

Input capacitance VI = 0V or 3.0V 4 pF Output capacitance Outputs disabled; VO = 0V or 3.0V 8 pF Total supply current Outputs disabled; VCC = 3.6V .13 mA

DESCRIPTION

The LVT573 is a high-performance BiCMOS product designed for VCC operation at 3.3V. This device is an octal transparent latch coupled to eight 3-State output buffers. The two sections of the device are controlled independently by Enable (E) and Output Enable (OE configuration to facilitate PC board layout and allow easy interface with microprocessors.

The data on the D inputs are transferred to the latch outputs when the Latch Enable (E) input is High. The latch remains transparent to the data inputs while E is High, and stores the data that is present one setup time before the High-to-Low enable transition.

The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active-Low Output Enable (OE independent of the latch operation.

When OE outputs. When OE “OFF” state, which means they will neither drive nor load the bus.

amb

CL = 50pF; VCC = 3.3V

is Low, the latched or transparent data appears at the

CONDITIONS = 25°C; GND = 0V

74L VT573

) control gates. The 74LVT573 has a broadside pinout

) controls all eight 3-State buffers

is High, the outputs are in the High-impedance

TYPICAL UNIT

2.5

2.7

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

20-Pin Plastic SOL –40°C to +85°C 74LVT573 D 74LVT573 D SOT163-1 20-Pin Plastic SSOP Type II –40°C to +85°C 74LVT573 DB 74LVT573 DB SOT339-1 20-Pin Plastic TSSOP Type I –40°C to +85°C 74LVT573 PW 74LVT573PW DH SOT360-1

PIN CONFIGURATION

120 2

D3 D4

GND

19 18 17 16 15 14 13 12 11

SV00031

V Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 E

PIN DESCRIPTION

PIN NUMBER SYMBOL FUNCTION

1 OE

2, 3, 4, 5, 6, 7, 8, 9 D0-D7 Data inputs

19, 18, 17, 16, 15,

14, 13, 12

Q0-Q7 Data outputs

11 E 10 GND Ground (0V)

20 V

Output enable input (active-Low)

Enable input (active-High)

Positive supply voltage

1998 Feb 19 853–1750 18988

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Philips Semiconductors Product specification

INTERNAL

OPERATING MODE

3.3V Octal D-type transparent latch (3-State)

LOGIC SYMBOL

23456789

D0 D1 D2 D3 D4 D5 D6 D7

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

19 18 17 16 15 14 13 12

SV00032

LOGIC SYMBOL (IEEE/IEC)

5 6

7 8

74LVT573

19 18

16 15

14 13

SV00033

FUNCTION TABLE

INPUTS

OE E Dn

L L

H H

↓ ↓

INTERNAL REGISTER

L L X NC NC Hold

H X X NC Z Disable outputs

H = High voltage level h = High voltage level one set-up time prior to the High-to-Low E transition L = Low voltage level l = Low voltage level one set-up time prior to the High-to-Low E transition NC= No change X = Don’t care Z = High impedance “off” state ↓ = High-to-Low E transition

OUTPUTS

Q0 – Q7

Enable and read register

Latch and read register

LOGIC DIAGRAM

1998 Feb 19

E Q

SV00034

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Philips Semiconductors Product specification

DC output current

SYMBOL

PARAMETER

UNIT

3.3V Octal D-type transparent latch

74LVT573

(3-State)

ABSOLUTE MAXIMUM RATINGS

SYMBOL

OUT

stg

DC supply voltage –0.5 to +4.6 V DC input diode current VI < 0 –50 mA DC input voltage

DC output diode current VO < 0 –50 mA DC output voltage

Storage temperature range –65 to 150 °C

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.

PARAMETER CONDITIONS RATING UNIT

1, 2

–0.5 to +7.0 V

Output in Off or High state –0.5 to +7.0 V

Output in Low state 128

Output in High state –64

RECOMMENDED OPERATING CONDITIONS

LIMITS

MIN MAX

∆t/∆v Input transition rise or fall rate; outputs enabled 10 ns/V T

amb

DC supply voltage 2.7 3.6 V Input voltage 0 5.5 V

High-level input voltage 2.0 V

Input voltage 0.8 V

High-level output current –32 mA Low-level output current 32 Low-level output current; current duty cycle ≤ 50%, f ≥ 1kHz 64

Operating free-air temperature range –40 +85 °C

1998 Feb 19

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Philips Semiconductors Product specification

Data pins

3.3V Octal D-type transparent latch

74LVT573

(3-State)

DC ELECTRICAL CHARACTERISTICS

LIMITS

SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT

MIN TYP1MAX

RST

OFF

HOLD

PU/PD

OZH

OZL

CCH

CCL

CCZ

∆I

NOTES:

1. All typical values are at V

2. This is the increase in supply current for each input at the specified voltage level other than V

3. This parameter is valid for any V transition time of 100µsec is permitted. This parameter is valid for T

4. Unused pins at V

5. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.

6. I

CCZ

7. This is the bus hold overdrive current required to force the input to the opposite logic state.

Input clamp voltage VCC = 2.7V; IIK = –18mA –0.9 –1.2 V

VCC = 2.7 to 3.6V; IOH = –100µA VCC-0.2 VCC-0.1

High-level output voltage VCC = 2.7V; IOH = –8mA 2.4 2.5 V

VCC = 3.0V; IOH = –32mA 2.0 2.2 VCC = 2.7V; IOL = 100µA 0.1 0.2 VCC = 2.7V; IOL = 24mA 0.3 0.5

Low-level output voltage VCC = 3.0V; IOL = 16mA 0.25 0.4 V

VCC = 3.0V; IOL = 32mA 0.3 0.5 VCC = 3.0V; IOL = 64mA 0.4 0.55

Power-up output low voltage5VCC = 3.6V; IO = 1mA; VI = GND or V

0.13 0.55 V

VCC = 0 or 3.6V; VI = 5.5V 1 10 VCC = 3.6V; VI = VCC or GND Control pins ±0.1 ±1

Input leakage current

VCC = 3.6V; VI = V VCC = 3.6V; VI = 0

–1 -5

0.1 1

Output off current VCC = 0V; VI or VO = 0 to 4.5V 1 ±100 µA

VCC = 3V; VI = 0.8V 75 150

Bus Hold current A inputs

VCC = 3V; VI = 2.0V –75 –150 VCC = 0V to 3.6V; VCC = 3.6V ±500

Current into an output in the High state when VO > V

Power up/down 3-State output

current

3-State output High current VCC= 3.6V; V 3-State output Low current VCC= 3.6V; V

Quiescent supply current VCC = 3.6V; Outputs Low, VI = GND or V

Additional supply current per

input pin

or GND.

= 3.3V and T

between 0V and 1.2V with a transition time of up to 10msec. From V

VO = 5.5V; VCC = 3.0V 60 125 µA

VCC ≤ 1.2V; VO = 0.5V to VCC; VI = GND or VCC; OE/OE = Don’t care

= 3V; VI = VIL or V

= 0.5V; VI = VIL or V

VCC = 3.6V; Outputs High, VI = GND or V

CC,

VCC = 3.6V; Outputs Disabled; VI = GND or V VCC = 3V to 3.6V; One input at VCC-0.6V,

Other inputs at VCC or GND

= 25°C.

amb

= 25°C only

amb

0 0.13 0.19

O =

0 3 12 mA

O =

CC,

O =

or GND

= 1.2V to VCC = 3.3V ± 0.3V a

1 ±100 µA

1 5

–1 –5

0.13 0.19

0.1 0.2 mA

is measured with outputs pulled to VCC or GND.

µA

1998 Feb 19

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Philips Semiconductors Product specification

ÉÉÉ

3.3V Octal D-type transparent latch

74LVT573

(3-State)

AC CHARACTERISTICS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω; T

SYMBOL PARAMETER WAVEFORM VCC = 3.3V ± 0.3V VCC = 2.7V UNIT

PLH

PHL

PLH

PHL

PZH

PZL

PHZ

PLZ

Propagation delay Dn to Qn

Propagation delay E to Qn

Output enable time to High and Low level

Output disable time from High and Low level

NOTE:

1. All typical values are at V

= 3.3V and T

amb

AC SETUP REQUIREMENTS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω; T

SYMBOL PARAMETER WAVEFORM VCC = 3.3V ± 0.3V VCC = 2.7V UNIT

tS(H) tS(L)

TH(H) TH(L)

TW(H) E pulse width High 1 3.3 3.3 ns

Setup time, High or Low, Dn to E 3

Hold time, High or Low, Dn to E 3

= –40°C to +85°C.

amb

= 25°C.

= –40°C to +85°C.

amb

LIMITS

2.5

2.7

3.5

4.3

2.8

3.3

3.7

3.0

MAX MAX

4.2

4.3

5.6

6.5

5.1

5.5

5.7

4.6

4.7

5.2

6.3

7.2

6.2

6.6

6.7

5.1

MIN TYP

1 4

5 4

1.0

1.6

2.5

1.0

1.3

2.0

1.5

LIMITS

MIN MAX MIN

0.7

1.6

0.6

1.8

AC WAVEFORMS

VM = 1.5V, VIN = GND to 2.7V

2.7V

tw(H)

PHL

1.5V1.5V

Waveform 1. Propagation Delay, Enable to Output, and Enable

Pulse Width

1.5V 1.5V

PLH

1.5V 1.5V

Waveform 2. Propagation Delay for Data to Outputs

1.5V

PHL

PLH

1.5V1.5V V

SV00035

2.7V

SV00117

1.5V 1.5V 1.5V 1.5V

ts(H)

(H)

(L)

1.5V1.5V

NOTE: The shaded areas indicate when the input is permitted

to change for predictable output performance.

Waveform 3. Data Setup and Hold Times

2.7V

SV00118

1998 Feb 19

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Philips Semiconductors Product specification

3.3V Octal D-type transparent latch (3-State)

2.7V

Waveform 4. 3-State Output Enable Time to High Level and

TEST CIRCUIT AND WAVEFORM

PULSE

GENERATOR

SWITCH POSITION

TEST SWITCH

PLH/tPHL

PLZ/tPZL

PHZ/tPZH

1.5V 1.5V

PZH

1.5V

PHZ

Output Disable Time from High Level

D.U.T.

OUT

Test Circuit for 3-State Outputs

Open

GND

–0.3V

SV00119

74LVT573

2.7V

Waveform 5. 3-State Output Enable Time to Low Level and

6.0V

Open

GND

90%

NEGATIVE PULSE

POSITIVE PULSE

10%

1.5V 1.5V

PZL

1.5V

PLZ

Output Disable Time from Low Level

10% 10%

(tF)

THL

(tR)t

TLH

90% 90%

90%

10%

VM = 1.5V

Input Pulse Definition

VOL +0.3V V

SV00120

(tR)

TLH

(tF)

THL

AMP (V)

DEFINITIONS

RL = Load resistor; see AC CHARACTERISTICS for value.

= Load capacitance includes jig and probe capacitance;

see AC CHARACTERISTICS for value.

= Termination resistance should be equal to Z

pulse generators.

1998 Feb 19

OUT

FAMILY

74LVT

INPUT PULSE REQUIREMENTS

Amplitude Rep. Rate t

2.7V 10MHz 500ns 2.5ns 2.5ns

SV00092

Page 8

Philips Semiconductors Product specification

3.3V Octal D-type transparent latch

74LVT573

(3-State)

SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

1998 Feb 19

Page 9

Philips Semiconductors Product specification

3.3V Octal D-type transparent latch

74LVT573

(3-State)

SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1

1998 Feb 19

Page 10

Philips Semiconductors Product specification

3.3V Octal D-type transparent latch

74LVT573

(3-State)

TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1

1998 Feb 19

Page 11

Philips Semiconductors Product specification

3.3V Octal D-type transparent latch (3-State)

74LVT573

NOTES

1998 Feb 19

Page 12

Philips Semiconductors Product specification

3.3V Octal D-type transparent latch (3-State)

Data sheet status

Objective specification

Preliminary specification

Product specification

Product status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

[1]

74LVT573

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381

 Copyright Philips Electronics North America Corporation 1998

print code Date of release: 05-96 Document order number: 9397-750-03538

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