Datasheet 74LVQ280 Datasheet (ST)

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74LVQ280

9 BIT PARITY GENERATOR

■ HIGH SPEED:

= 8 ns (TYP.) at VCC = 3.3 V

t

PD

■ COMPA TIBLE WITH TTL OUTPUTS

■ LOW POWER DISSIPATION:

I

= 2µA(MAX.) at TA=25°C

CC

■ LOW NOISE:

= 0.3V (TYP.) at VCC = 3.3V

V

OLP

■ 75Ω TRANSMISSION LINE DRIVING

CAPABILITY

■ SYMMETRICAL OUTPUT IMPEDANCE:

| = IOL = 12mA (MIN) at VCC = 3.0 V

|I

OH

■ PCI BUS LEVELS GUARANTEED AT 24 mA

■ BALANCED PROPAGATION DELAYS:

≅ t

t

PLH

■ OPERATING VOLTAGE RANGE:

V

CC

■ PIN AND FUNCTION COMPATIBLE WITH

PHL

(OPR) = 2V to 3.6V

74 SERIES 280

■ IMPROVED LATCH-U P IMMUNITY

DESCRIPTION

The 74LVQ280 is a low voltage CMOS 9 BIT
PARITY GENERATOR fabricated with sub-micron
silicon gate and double-layer metal wiring C2MOS
technology. It is ideal for low power and low noise

3.3V applications.
It is composed of nine data inputs (A to I) and odd/
even parity outputs (ΣODD and ΣEVEN). The nine

TSSOPSOP

ORDER CODES

PACKAGE TUBE T & R

SOP 74LVQ280M 74LVQ280MTR

TSSOP 74LVQ280TTR

data inputs control the output conditions. When
the number of high level input is odd, ΣODD
output is kept high and ΣEVEN output low.
Conversely, when the number of high level is
even, ΣEVEN output is kept high and ΣODD low.
The IC generates either odd or even parity making
it flexible application. The word-length capability is
easily expanded by cascading.
All inputs and outputs are equipped with
protection circuits against stat ic discharge, giving
them 2KV ESD immunity and transient excess
voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

1/8July 2001

74LVQ280

INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION

PIN No SYMBOL NAME AND FUNCTION

5 ΣEVEN Even Parity Output
6 ΣODD Odd Parity Output

8, 9, 10, 11,
12, 13, 1, 2,

4
3 NC No Connection
7 GND Ground (0V)

14

TRUTH TABLE

A to I Data Inputs

V

CC

Positive Supply Voltage

NUMBER OF INPUTS A - I THAT ARE HIGH

LOGIC DIAGRAM

OUTPUTS

ΣEVEN ΣODD

0, 2, 4, 6, 8 H L
1, 3, 5, 7, 9 L H

2/8

74LVQ280

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

V

V

I

I

OK

I

I

or I

CC

T

T

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Value Unit

V

V

V

T

1) Truth T abl e guarante ed: 1.2V to 3.6 V

Supply Voltage

CC

DC Input Voltage -0.5 to VCC + 0.5

I

DC Output Voltage -0.5 to VCC + 0.5

O

DC Input Diode Current

IK

DC Output Diode Current
DC Output Current

O

DC VCC or Ground Current

GND

Storage Temperature

stg

Lead Temperature (10 sec)

L

Supply Voltage (note 1)

CC

Input Voltage 0 to V

I

Output Voltage 0 to V

O

Operating Temperature

op

-0.5 to +7 V

± 20 mA
± 20 mA
± 50 mA

± 300 mA

-65 to +150 °C
300 °C

2 to 3.6 V

CC
CC

-55 to 125 °C

V
V

V
V

DC SPECIFICATIONS

Test Condition Value

T

Symbol Parameter

V

CC

(V)

V

V

V

V

I

I

OLD

I

OHD

1) Maxim um test duration 2ms, one out put loaded at time

2) Incid ent wave sw i tc hi ng is guara nt eed on transmi ssion lines with impedances a s low as 75Ω

High Level Input

IH

Voltage
Low Level Input

IL

Voltage
High Level Output

OH

Voltage

Low Level Output

OL

Voltage

I

Input Leakage

I

Current
Quiescent Supply

CC

Current
Dynamic Output

Current (note 1, 2)

3.0 to

3.6

3.0

3.0

3.6

3.6

3.6

=-50 µA

I

O

I

=-12 mA

O

I

=-24 mA

O

IO=50 µA

I

=12 mA

O

I

=24 mA

O

V

= VCC or GND

I

= VCC or GND

V

I

= 0.8 V max

V

OLD

V

= 2 V min

OHD

= 25°C

A

Min. Typ. Max. Min. Max. Min. Max.

2.0 2.0 2.0 V

0.8 0.8 0.8 V

2.9 2.99 2.9 2.9

2.58 2.48 2.48

0.002 0.1 0.1 0.1
0 0.36 0.44 0.44

± 0.1 ± 1 ± 1 µA

22020µA

-40 to 85°C -55 to 125°C

Unit

2.2 2.2

0.55 0.55

36 25 mA

-25 -25 mA

V

V

3/8

74LVQ280

DYNAMIC SWITCHING CHARACTERISTICS

Test Condition Value

T

Symbol Parameter

V
V

V

Dynamic Low

OLP

Voltage Quiet

OLV

Output (note 1, 2)
Dynamic High

IHD

Voltage Input

V

CC

(V)

3.3

3.3 2 V
= 50 pF

C

L

= 25°C

A

Min. Typ. Max. Min. Max. Min. Max.

0.3 0.8

-0.8 -0.3

(note 1, 3)

V

ILD

Dynamic Low
Voltage Input

3.3 0.8 V

(note 1, 3)

1) Worst c ase package .

2) Max number of outp ut s defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.

3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V
(V

), f=1MHz.

IHD

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns)

Test Condition Value

T

Symbol Parameter

V

CC

(V)

t

PLH tPHL

t

OSLH

t

OSHL

1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch­ing in the same direction, either HIGH or LOW ( t

2) Param eter guaran teed by design
(*) Vol tage range is 3.3V ±

Propagation Delay
Time

Output To Output
Skew Time
(note1, 2)

0.3V

2.7 9.9 16.0 19.0 22.0

(*)

3.3

2.7 0.5 1.0 1.0 1.0

(*)

3.3

= |t

- t

OSLH

PLHm

PLHn

|, t

= 25°C

A

Min. Typ. Max. Min. Max. Min. Max.

8.0 11.5 13.5 16.0

0.5 1.0 1.0 1.0

= |t

PHLm

- t

PHLn

OSHL

-40 to 85°C -55 to 125°C

-40 to 85°C -55 to 125°C

|)

), 0V to threshold

ILD

Unit

V

Unit

ns

ns

CAPACITIVE CHARACTERISTICS

Test Condition Value

T

Symbol Parameter

C

C

Input Capacitance

IN

Power Dissipation

PD

Capacitance

V

CC

(V)

3.3 4 pF

= 10MHz

3.3

f

IN

= 25°C

A

Min. Typ. Max. Min. Max. Min. Max.

59 pF

(note 1)

1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without

load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I

4/8

-40 to 85°C -55 to 125°C

= CPD x VCC x fIN + ICC/n (per c ircuit )

CC(opr)

Unit

TEST CIRCUIT

CL = 50pF or equivalent (in cludes jig and probe capaci tance)

= 500Ω or equivalent

R

L

R

= Z

of pulse generator (typically 50Ω)

T

OUT

WAVEFORM : PROPAGATION DELAYS (f=1MHz; 50% duty cycle)

74LVQ280

5/8

74LVQ280

SO-14 MECHANICAL DATA

DIM.

A 1.75 0.068
a1 0.1 0.2 0.003 0.007
a2 1.65 0.064

b 0.35 0.46 0.013 0.018
b1 0.19 0.25 0.007 0.010

C 0.5 0.019

c1 45° (typ.)

D 8.55 8.75 0.336 0.344
E 5.8 6.2 0.228 0.244

e 1.27 0.050
e3 7.62 0.300

F 3.8 4.0 0.149 0.157
G 4.6 5.3 0.181 0.208

L 0.5 1.27 0.019 0.050

M 0.68 0.026
S8° (max.)

MIN. TYP MAX. MIN. TYP. MAX.

mm. inch

6/8

PO13G

74LVQ280

TSSOP14 MECHANICAL DATA

mm. inch

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

A 1.2 0.047

A1 0.05 0.15 0.002 0.004 0.006

A2 0.8 1 1.05 0.031 0.039 0.041

b 0.19 0.30 0.007 0.012

c 0.09 0.20 0.004 0.0089

D 4.9 5 5.1 0.193 0.197 0.201

E 6.2 6.4 6.6 0.244 0.252 0.260

E1 4.3 4.4 4.48 0.169 0.173 0.176

e 0.65 BSC 0.0256 BSC

K0° 8°0° 8°

L 0.45 0.60 0.75 0.018 0.024 0.030

A2

A

A1

b

e

c

K

L

E

D

E1

PIN 1 IDENTIFICATION

1

0080337D

7/8

74LVQ280

Information furnished is bel ieved to be accurate and reliable. However, STMicroe lectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No li cense is granted by implication or otherwise unde r any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication ar e subject to change without notice. This publication supersedes and replaces all information
previously supplied. S TMicroelectronics products are not authorized for use as critica l components in life suppo rt devices or
systems without express written approval of STMicroelectronics.

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