Datasheet 74LVQ174 Datasheet (SGS Thomson Microelectronics)



HEX D-TYPE FLIP FLOP WITH CLEAR

■ HIGHSPEED:

=150MHz(TYP.)atVCC=3.3V

f

MAX

■ COMPATIBLEWITHTTLOUTPUTS

■

LOW POWERDISSIPATION:
I

=4 µA (MAX.) atTA=25oC

CC

■ LOWNOISE:

=0.3V (TYP.)atVCC=3.3V

V

OLP

■ 75ΩTRANSMISSIONLINEDRIVING

CAPABILITY

■ SYMMETRICALOUTPUTIMPEDANCE:

|I

|=IOL=12 mA (MIN)

OH

■

PCIBUSLEVELSGUARANTEEDAT24mA

■ BALANCEDPROPAGATIONDELAYS:

t

≅ t

PLH

PHL

■ OPERATINGVOLTAGERANGE:

V

(OPR)= 2V to3.6V(1.2VDataRetention)

CC

■

PINANDFUNCTION COMPATIBLEWITH
74SERIES174

■ IMPROVEDLATCH-UPIMMUNITY

DESCRIPTION

The LVQ174 is a low voltage CMOS HEX
D-TYPE FLIP FLOP WITH CLEAR NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C
technology.It is idealfor low power and low noise

2

MOS

74LVQ174

M

(Micro Package)

(TSSOPPackage)

ORDERCODES :

74LVQ174M 74LVQ174T

3.3Vapplications.
Information signals applied to D inputs are

transfered to the Q outputs on the positive going
edgeof the clock pulse.

Whenthe CLEAR input is held low, the Q outputs
are held low independentelyof the other inputs .

It has better speed performance at 3.3V than 5V
LS-TTL family combined with the true CMOS low
powerconsumption.

All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.

T

PIN CONNECTION AND IEC LOGIC SYMBOLS

February 1999

1/10

74LVQ174

INPUT AND OUTPUT EQUIVALENTCIRCUIT

TRUTH TABLE

INPUTS OUTPUTS FUNCTION

CLE AR D CLOCK Q

L X X L CLEAR
HL L
HH H
HX Q

X:Don’tCare

PIN DESCRIPTION

PI N No SYM BO L NAM E AND F UNCT I O N

1 CLEAR Asyncronous Master Reset

(ActiveLOW)

2, 5, 7, 10,

12, 15

3, 4, 6, 11,

13, 14

9 CLOCK ClockInput (LOW-to-HIGH,

8 GND Ground(0V)

16 V

n

Q0 to Q5 Flip-Flop Outputs

D0 to D5 DataInputs

Edge-Triggered)

CC

PositiveSupply Voltage

NO CHANGE

LOGICDIAGRAM

Thislogic diagram has not be used to estimate propagation delays

2/10

74LVQ174

ABSOLUTE MAXIMUM RATINGS

Symb o l Para met er Val u e Uni t

V

V

V

I

I

OK

I

or I

I

CC

T

T

AbsoluteMaximumRatingsarethose values beyond whichdamagetothedevicemayoccur.Functionaloperationunderthese conditionisnotimplied.

RECOMMENDED OPERATINGCONDITIONS

Symb o l Para met er Value Un it

V

V

V

T

dt/dv InputRiseand FallTime (V

1) Truth Table guaranteed: 1.2V to 3.6V

2)V

from0.8Vto 2V

IN

SupplyVoltage -0.5 to +7 V

CC

DC InputVoltage -0.5 to VCC+ 0.5 V

I

DC OutputVoltage -0.5 to VCC+ 0.5 V

O

DC InputDiode Current ± 20 mA

IK

DC OutputDiodeCurrent ± 20 mA
DC OutputCurrent

O

DC VCCorGround Current

GND

Storage Temperature -65 to +150

stg

LeadTemperature (10 sec) 300

L

SupplyVoltage(note1) 2 to 3.6 V

CC

InputVoltage 0 to V

I

OutputVoltage 0 to V

O

OperatingTemperature: -40 to +85

op

=3V)(note2) 0 to 10 ns/V

CC

50 mA

±

300 mA

±

CC
CC

o

C

o

C

V
V

o

C

3/10

74LVQ174

DC SPECIFICATIONS

Symbol Parameter Test Conditions Value Unit

T

V

CC

(V)

HighLevelInput Voltage

V

IH

LowLevelInput Voltage 0.8 0.8 V

V

IL

HighLevelOutputVoltage 3.0 V

V

OH

LowLevelOutputVoltage 3.0 V

V

OL

InputLeakage Current

I

I

Quiescent SupplyCurrent 3.6 VI=VCCor GND 4 40

I

CC

Dynamic OutputCurrent

I

OLD

OHD

(note 1, 2)

I

1) Maximum test duration 2ms, one output loaded at time

2)Incidentwaveswitchingisguaranteed ontransmissionlineswithimpedances aslowas50 Ω.
(*)All outputs loaded.

3.0 to

3.6

3.6

3.6 V

(*)

=

IO=-50 µA 2.9 2.99 2.9

I

or

V

IH

V

IL

(*)

I

V

IH

V

IL

=-12 mA 2.58 2.48

I

O

=-24 mA 2.2

I

O

=

IO=50 µA 0.002 0.1 0.1

or

=12 mA 0 0.36 0.44

I

O

=24 mA 0.55

I

O

VI=VCCor GND ±0.1 ±1 µA

= 0.8 V max 36 mA

OLD

V

= 2 V min -25 mA

OHD

=25oC -40 to 85oC

A

Min. Typ. Max. Min. Max.

2.0 2.0

µ

V

V

V

A

DYNAMICSWITCHINGCHARACTERISTICS

Symbol Parameter Test Conditions Value Unit

T

V

CC

(V)

V
V

V

Dynamic Low Voltage

OLP

QuietOutput(note 1,2)

OLV

Dynamic High Voltage

IHD

3.3

3.3 2

C

L

=50pF

Input(note1, 3)

V

Dynamic Low Voltage

ILD

3.3 0.8

Input(note1, 3)

1)Worstcasepackage

2)Maxnumberofoutputsdefined as(n).Datainputs aredriven0Vto3.3V,(n-1)outputsswitchingandoneoutput atGND

3)maxnumberofdatainputs(n)switching.(n-1)switching0Vto3.3V.Inputs under testswitching: 3.3Vtothreshold(V

=25oC -40 to 85oC

A

Min. Typ. Max. Min. Max.

0.3 0.8

-0.8 -0.3

),0V tothreshold(V

ILD

).f=1MHz

IHD

V

4/10

74LVQ174

AC ELECTRICAL CHARACTERISTICS

= 50 pF, RL= 500 Ω, Input tr=tf=3 ns)

(C

L

Symbol Parameter Test Condition Value Unit

V

CC

(V)

t

PropagationDelay Time

PLH

t

CKto Q

PHL

PropagationDelay Time

t

PHL

CLRtoQ
CLRpulseWidth,LOW 2.7 1.0 7.0 10.0

t

w(L)

t

CKpulse Width,HIGHor

w

LOW,2.7
SetupTime D to CKHIGH

t

sL

t

orLOW

sH

HoldTimeD toCK HIGH

t

hL

orLOW

t

hH

t

f

t
t

1) Skewisdefinedas theabsolutevalue ofthedifferencebetweentheactualpropagation delay foranytwooutputsofthesamedeviceswitchingin the
same direction, either HIGHorLOW(t

2) Parameterguaranteed bydesign
(*) Voltagerangeis 3.3V±0.3V

Recovery Time CLR to CK 2.7 0.5 3.5 3.5

REM

MaximumClock Frequency 2.7 60 150 50

MAX

Outputto OutputSkew

OSLH

Time(note 1, 2)

OSHL

=|t

OSLH

2.7 7.0 15.0 17.0

(*)

3.3

2.7 8.5 16.0 18.0

(*)

3.3

(*)

3.3

(*)

3.3

2.7 -0.5 8.0 10.0

(*)

3.3

2.7 0.5 4.0 4.5

(*)

3.3

(*)

3.3

(*)

3.3

2.7 0.5 1.0 1.5 ns

(*)

3.3

|,t

PLHm-tPLHn

OSHL

=|t

PHLm-tpHLn

|)

T

=25oC -40 to 85oC

A

Min. Typ. Max. Min. Max.

5.5 11.0 12.0

7.0 12.0 13.0

1.0 5.5 7.0

1.0 7.0 10.0 ns

1.0 5.5 7.0

-0.4 6.5 7.0

0.4 3.0 3.0

0.4 2.5 2.5

90 150 70

0.5 1.0 1.5

ns

ns

ns

ns

ns

ns

MHz

CAPACITIVE CHARACTERISTICS

Symbol Parameter Test Conditions Value Unit

T

V

CC

(V)

InputCapacitance

C

IN

C

PD

Power Dissipation

3.3

3.3 fIN= 10 MHz 23 pF

Capacitance (note 1)

1)CPDisdefined asthevalueoftheIC’sinternalequivalentcapacitance whichiscalculatedfromtheoperatingcurrentconsumption withoutload.(Referto
TestCircuit).Average operting current canbe obtainedbythefollowingequation. I

(opr)= CPD• VCC• fIN+ICC/6(perflipflop)

CC

=25oC -40 to 85oC

A

Min. Typ. Max. Min. Max.

5

pF

5/10

74LVQ174

TESTCIRCUIT

CL= 50 pF or equivalent (includes jigand probe capacitance)
R

=500Ωorequivalent

L=R1

R

WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES, CLOCK PULSE WIDTH

(f=1MHz;50% duty cycle)

ofpulse generator (typically50Ω)

T=ZOUT

6/10

74LVQ174

WAVEFORM2: PROPAGATIONDELAYS

(f=1MHz;50% duty cycle)

WAVEFORM3: RECOVERYTIME, CLEARPULSE WIDTH (f=1MHz;50% duty cycle)

7/10

74LVQ174

SO-16 MECHANICAL DATA

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

A 1.75 0.068
a1 0.1 0.2 0.004 0.007
a2 1.65 0.064

b 0.35 0.46 0.013 0.018
b1 0.19 0.25 0.007 0.010

C 0.5 0.019

c1 45 (typ.)

D 9.8 10 0.385 0.393

E 5.8 6.2 0.228 0.244

e 1.27 0.050
e3 8.89 0.350

F 3.8 4.0 0.149 0.157

G 4.6 5.3 0.181 0.208

L 0.5 1.27 0.019 0.050

M 0.62 0.024

S 8 (max.)

mm inch

8/10

P013H

TSSOP16 MECHANICAL DATA

74LVQ174

DIM.

mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 1.1 0.433

A1 0.05 0.10 0.15 0.002 0.004 0.006

A2 0.85 0.9 0.95 0.335 0.354 0.374

b 0.19 0.30 0.0075 0.0118

c 0.09 0.20 0.0035 0.0079

D 4.9 5 5.1 0.193 0.197 0.201

E 6.25 6.4 6.5 0.246 0.252 0.256

E1 4.3 4.4 4.48 0.169 0.173 0.176

e 0.65 BSC 0.0256 BSC

K0

o

o

4

o

8

o

0

o

4

L 0.50 0.60 0.70 0.020 0.024 0.028

o

8

A2

A

A1

PIN 1 IDENTIFICATION

b

e

c

K

L

E

D

E1

1

9/10

74LVQ174

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